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comparison src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp @ 2089:037c727f35fb

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7009231: C1: Incorrect CAS code for longs on SPARC 32bit Summary: Fix CAS of longs on SPARC 32bit and cmove on SPARC 64bit. Reviewed-by: kvn
author iveresov
date Mon, 27 Dec 2010 21:51:31 -0800
parents 7601ab0e1e33
children 55f868e91c3b
comparison
equal deleted inserted replaced
2088:8d0b933dda2d 2089:037c727f35fb
1703 ShouldNotReachHere(); 1703 ShouldNotReachHere();
1704 } 1704 }
1705 } 1705 }
1706 1706
1707 1707
1708 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { 1708 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1709
1710 Assembler::Condition acond; 1709 Assembler::Condition acond;
1711 switch (condition) { 1710 switch (condition) {
1712 case lir_cond_equal: acond = Assembler::equal; break; 1711 case lir_cond_equal: acond = Assembler::equal; break;
1713 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1712 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1714 case lir_cond_less: acond = Assembler::less; break; 1713 case lir_cond_less: acond = Assembler::less; break;
1735 stack2reg(opr1, result, result->type()); 1734 stack2reg(opr1, result, result->type());
1736 } else { 1735 } else {
1737 ShouldNotReachHere(); 1736 ShouldNotReachHere();
1738 } 1737 }
1739 Label skip; 1738 Label skip;
1740 __ br(acond, false, Assembler::pt, skip); 1739 #ifdef _LP64
1740 if (type == T_INT) {
1741 __ br(acond, false, Assembler::pt, skip);
1742 } else
1743 #endif
1744 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1741 if (opr1->is_constant() && opr1->type() == T_INT) { 1745 if (opr1->is_constant() && opr1->type() == T_INT) {
1742 Register dest = result->as_register(); 1746 Register dest = result->as_register();
1743 if (Assembler::is_simm13(opr1->as_jint())) { 1747 if (Assembler::is_simm13(opr1->as_jint())) {
1744 __ delayed()->or3(G0, opr1->as_jint(), dest); 1748 __ delayed()->or3(G0, opr1->as_jint(), dest);
1745 } else { 1749 } else {
2686 Register t1 = op->tmp1()->as_register(); 2690 Register t1 = op->tmp1()->as_register();
2687 Register t2 = op->tmp2()->as_register(); 2691 Register t2 = op->tmp2()->as_register();
2688 #ifdef _LP64 2692 #ifdef _LP64
2689 __ mov(cmp_value_lo, t1); 2693 __ mov(cmp_value_lo, t1);
2690 __ mov(new_value_lo, t2); 2694 __ mov(new_value_lo, t2);
2695 // perform the compare and swap operation
2696 __ casx(addr, t1, t2);
2697 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2698 // overwritten with the original value in "addr" and will be equal to t1.
2699 __ cmp(t1, t2);
2691 #else 2700 #else
2692 // move high and low halves of long values into single registers 2701 // move high and low halves of long values into single registers
2693 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg 2702 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
2694 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half 2703 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
2695 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value 2704 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
2696 __ sllx(new_value_hi, 32, t2); 2705 __ sllx(new_value_hi, 32, t2);
2697 __ srl(new_value_lo, 0, new_value_lo); 2706 __ srl(new_value_lo, 0, new_value_lo);
2698 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap 2707 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
2699 #endif
2700 // perform the compare and swap operation 2708 // perform the compare and swap operation
2701 __ casx(addr, t1, t2); 2709 __ casx(addr, t1, t2);
2702 // generate condition code - if the swap succeeded, t2 ("new value" reg) was 2710 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2703 // overwritten with the original value in "addr" and will be equal to t1. 2711 // overwritten with the original value in "addr" and will be equal to t1.
2704 __ cmp(t1, t2); 2712 // Produce icc flag for 32bit.
2705 2713 __ sub(t1, t2, t2);
2714 __ srlx(t2, 32, t1);
2715 __ orcc(t2, t1, G0);
2716 #endif
2706 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { 2717 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2707 Register addr = op->addr()->as_pointer_register(); 2718 Register addr = op->addr()->as_pointer_register();
2708 Register cmp_value = op->cmp_value()->as_register(); 2719 Register cmp_value = op->cmp_value()->as_register();
2709 Register new_value = op->new_value()->as_register(); 2720 Register new_value = op->new_value()->as_register();
2710 Register t1 = op->tmp1()->as_register(); 2721 Register t1 = op->tmp1()->as_register();