truffle: src/cpu/sparc/vm/sparc.ad comparison

comparison src/cpu/sparc/vm/sparc.ad @ 4137:04b9a2566eec

Merge with hsx23/hotspot.

author	Thomas Wuerthinger <thomas.wuerthinger@oracle.com>
date	Sat, 17 Dec 2011 21:40:27 +0100
parents	db2e64ca2d5a
children	1dc233a8c7fe

comparison

equal deleted inserted replaced

-:9dc19b7d89a3
+:04b9a2566eec
 // Paired floating point registers--they show up in the same order as the floats,
 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
 // This class is usable for mis-aligned loads as happen in I2C adapters.
 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
-R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
+R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
 %}
 //----------DEFINITION BLOCK---------------------------------------------------
 // Define name --> value mappings to inform the ADLC of an integer valued name
 // Current support includes integer values in the range [0, 0x7FFFFFFF]
 // definitions necessary in the rest of the architecture description
 source_hpp %{
 // Must be visible to the DFA in dfa_sparc.cpp
 extern bool can_branch_register( Node *bol, Node *cmp );
+extern bool use_block_zeroing(Node* count);
 // Macros to extract hi & lo halves from a long pair.
 // G0 is not part of any long pair, so assert on that.
 // Prevents accidentally using G1 instead of G0.
 #define LONG_HI_REG(x) (x)
 #define LONG_LO_REG(x) (x)
 %}
 source %{
 #define __ _masm.
-// Block initializing store
-#define ASI_BLK_INIT_QUAD_LDD_P    0xE2
 // tertiary op of a LoadP or StoreP encoding
 #define REGP_OP true
 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
 if( !x->in(i)->is_Load() )
 return false;
 return true;
 }
 return false;
+}
+bool use_block_zeroing(Node* count) {
+// Use BIS for zeroing if count is not constant
+// or it is >= BlockZeroingLowLimit.
+return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
 }
 // ****************************************************************************
 // REQUIRED FUNCTIONALITY
 else
 klass_load_size = 3*BytesPerInstWord;
 } else {
 klass_load_size = 1*BytesPerInstWord;
 }
-if( Assembler::is_simm13(v_off) ) {
+if (Assembler::is_simm13(v_off)) {
 return klass_load_size +
 (2*BytesPerInstWord +           // ld_ptr, ld_ptr
 NativeCall::instruction_size);  // call; delay slot
 } else {
 return klass_load_size +
 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
 !(n->ideal_Opcode()==Op_ConvI2F   && ld_op==Op_LoadF) &&
 !(n->ideal_Opcode()==Op_ConvI2D   && ld_op==Op_LoadF) &&
 !(n->ideal_Opcode()==Op_PrefetchRead  && ld_op==Op_LoadI) &&
 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
+!(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
 !(n->ideal_Opcode()==Op_Load2I    && ld_op==Op_LoadD) &&
 !(n->ideal_Opcode()==Op_Load4C    && ld_op==Op_LoadD) &&
 !(n->ideal_Opcode()==Op_Load4S    && ld_op==Op_LoadD) &&
 !(n->ideal_Opcode()==Op_Load8B    && ld_op==Op_LoadD) &&
 !(n->rule() == loadUB_rule)) {
 void emit_lo(CodeBuffer &cbuf, int val) {  }
 void emit_hi(CodeBuffer &cbuf, int val) {  }
 //=============================================================================
-const bool Matcher::constant_table_absolute_addressing = false;
+const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
-const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask;
+int Compile::ConstantTable::calculate_table_base_offset() const {
+if (UseRDPCForConstantTableBase) {
+// The table base offset might be less but then it fits into
+// simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
+return Assembler::min_simm13();
+} else {
+int offset = -(size() / 2);
+if (!Assembler::is_simm13(offset)) {
+offset = Assembler::min_simm13();
+}
+return offset;
+}
+}
 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
 Compile* C = ra_->C;
 Compile::ConstantTable& constant_table = C->constant_table();
 MacroAssembler _masm(&cbuf);
 Register r = as_Register(ra_->get_encode(this));
-CodeSection* cs = __ code()->consts();
+CodeSection* consts_section = __ code()->consts();
-int consts_size = cs->align_at_start(cs->size());
+int consts_size = consts_section->align_at_start(consts_section->size());
+assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
 if (UseRDPCForConstantTableBase) {
 // For the following RDPC logic to work correctly the consts
 // section must be allocated right before the insts section.  This
 // assert checks for that.  The layout and the SECT_* constants
 // are defined in src/share/vm/asm/codeBuffer.hpp.
 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
-int offset = __ offset();
+int insts_offset = __ offset();
+// Layout:
+//
+// |----------- consts section ------------|----------- insts section -----------...
+// |------ constant table -----|- padding -|------------------x----
+//                                                            \ current PC (RDPC instruction)
+// |<------------- consts_size ----------->|<- insts_offset ->|
+//                                                            \ table base
+// The table base offset is later added to the load displacement
+// so it has to be negative.
+int table_base_offset = -(consts_size + insts_offset);
 int disp;
 // If the displacement from the current PC to the constant table
 // base fits into simm13 we set the constant table base to the
 // current PC.
-if (__ is_simm13(-(consts_size + offset))) {
+if (Assembler::is_simm13(table_base_offset)) {
-constant_table.set_table_base_offset(-(consts_size + offset));
+constant_table.set_table_base_offset(table_base_offset);
 disp = 0;
 } else {
-// If the offset of the top constant (last entry in the table)
+// Otherwise we set the constant table base offset to the
-// fits into simm13 we set the constant table base to the actual
+// maximum negative displacement of load instructions to keep
-// table base.
+// the disp as small as possible:
-if (__ is_simm13(constant_table.top_offset())) {
+//
-constant_table.set_table_base_offset(0);
+// |<------------- consts_size ----------->|<- insts_offset ->|
-disp = consts_size + offset;
+// |<--------- min_simm13 --------->|<-------- disp --------->|
-} else {
+//                                  \ table base
-// Otherwise we set the constant table base in the middle of the
+table_base_offset = Assembler::min_simm13();
-// constant table.
+constant_table.set_table_base_offset(table_base_offset);
-int half_consts_size = consts_size / 2;
+disp = (consts_size + insts_offset) + table_base_offset;
-assert(half_consts_size * 2 == consts_size, "sanity");
-constant_table.set_table_base_offset(-half_consts_size);  // table base offset gets added to the load displacement.
-disp = half_consts_size + offset;
-}
 }
 __ rdpc(r);
 if (disp != 0) {
 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
 }
 }
 else {
 // Materialize the constant table base.
-assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
+address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
-address baseaddr = cs->start() + -(constant_table.table_base_offset());
 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
 AddressLiteral base(baseaddr, rspec);
 __ set(base, r);
 }
 }
 __ sethi(-framesize & ~0x3ff, G3);
 __ add(G3, -framesize & 0x3ff, G3);
 __ save(SP, G3, SP);
 }
 C->set_frame_complete( __ offset() );
+if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
+// NOTE: We set the table base offset here because users might be
+// emitted before MachConstantBaseNode.
+Compile::ConstantTable& constant_table = C->constant_table();
+constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
+}
 }
 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
 return MachNode::size(ra_);
 }
 src_second_rc = rc_float;
 }
 // --------------------------------------
 // Check for float->int copy; requires a trip through memory
-if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
+if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
 int offset = frame::register_save_words*wordSize;
-if( cbuf ) {
+if (cbuf) {
 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
 }
 #ifndef PRODUCT
-else if( !do_size ) {
+else if (!do_size) {
-if( size != 0 ) st->print("\n\t");
+if (size != 0) st->print("\n\t");
 st->print(  "SUB    R_SP,16,R_SP\n");
 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
 st->print("\tADD    R_SP,16,R_SP\n");
 }
 #endif
 size += 16;
+}
+// Check for float->int copy on T4
+if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
+// Further check for aligned-adjacent pair, so we can use a double move
+if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
+return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
+size  =  impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
+}
+// Check for int->float copy on T4
+if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
+// Further check for aligned-adjacent pair, so we can use a double move
+if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
+return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
+size  =  impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
 }
 // --------------------------------------
 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
 // In such cases, I have to do the big-endian swap.  For aligned targets, the
 }
 #endif
 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 MacroAssembler _masm(&cbuf);
-Label L;
 Register G5_ic_reg  = reg_to_register_object(Matcher::inline_cache_reg_encode());
 Register temp_reg   = G3;
 assert( G5_ic_reg != temp_reg, "conflicting registers" );
 // Load klass from receiver
 // Is this branch offset short enough that a short branch can be used?
 //
 // NOTE: If the platform does not provide any short branch variants, then
 //       this method should return false for offset 0.
-bool Matcher::is_short_branch_offset(int rule, int offset) {
+bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
-return false;
+// The passed offset is relative to address of the branch.
+// Don't need to adjust the offset.
+return UseCBCond && Assembler::is_simm12(offset);
 }
 const bool Matcher::isSimpleConstant64(jlong value) {
 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
 // Depends on optimizations in MacroAssembler::setx.
 // No scaling for the parameter the ClearArray node.
 const bool Matcher::init_array_count_is_in_bytes = true;
 // Threshold size for cleararray.
 const int Matcher::init_array_short_size = 8 * BytesPerLong;
+// No additional cost for CMOVL.
+const int Matcher::long_cmove_cost() { return 0; }
+// CMOVF/CMOVD are expensive on T4 and on SPARC64.
+const int Matcher::float_cmove_cost() {
+return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
+}
 // Should the Matcher clone shifts on addressing modes, expecting them to
 // be subsumed into complex addressing expressions or compute them into
 // registers?  True for Intel but false for most RISCs
 const bool Matcher::clone_shift_expressions = false;
 ShouldNotReachHere();
 return RegMask();
 }
 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
-return L7_REGP_mask;
+return L7_REGP_mask();
 }
 %}
 emit_form3_mem_reg(cbuf, this, $primary, -1,
 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
 %}
 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
-assert( Assembler::is_simm13($mem$$disp  ), "need disp and disp+4" );
+assert(Assembler::is_simm13($mem$$disp  ), "need disp and disp+4");
-assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
+assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
 guarantee($mem$$index == R_G0_enc, "double index?");
 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg );
 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
 %}
 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
-assert( Assembler::is_simm13($mem$$disp  ), "need disp and disp+4" );
+assert(Assembler::is_simm13($mem$$disp  ), "need disp and disp+4");
-assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
+assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
 guarantee($mem$$index == R_G0_enc, "double index?");
 // Load long with 2 instructions
 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg+0 );
 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
 %}
 MacroAssembler _masm(&cbuf);
 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
 __ delayed()->nop();
 %}
-enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
+enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
 MacroAssembler _masm(&cbuf);
-Label &L = *($labl$$label);
+Label* L = $labl$$label;
 Assembler::Predict predict_taken =
-cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
-__ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
+__ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
 __ delayed()->nop();
 %}
-enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
+enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
 MacroAssembler _masm(&cbuf);
-Label &L = *($labl$$label);
+Label* L = $labl$$label;
 Assembler::Predict predict_taken =
-cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
-__ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
+__ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
-__ delayed()->nop();
-%}
-enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
-MacroAssembler _masm(&cbuf);
-Label &L = *($labl$$label);
-Assembler::Predict predict_taken =
-cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
-__ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
-__ delayed()->nop();
-%}
-enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
-MacroAssembler _masm(&cbuf);
-Label &L = *($labl$$label);
-Assembler::Predict predict_taken =
-cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
-__ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
-__ delayed()->nop();
-%}
-enc_class enc_ba( Label labl ) %{
-MacroAssembler _masm(&cbuf);
-Label &L = *($labl$$label);
-__ ba(false, L);
-__ delayed()->nop();
-%}
-enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
-MacroAssembler _masm(&cbuf);
-Label &L = *$labl$$label;
-Assembler::Predict predict_taken =
-cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
-__ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
 __ delayed()->nop();
 %}
 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
 int op = (Assembler::arith_op << 30) |
 } else {
 klass_load_size = 1*BytesPerInstWord;
 }
 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
-if( __ is_simm13(v_off) ) {
+if (Assembler::is_simm13(v_off)) {
 __ ld_ptr(G3, v_off, G5_method);
 } else {
 // Generate 2 instructions
 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
 __ or3(G5_method, v_off & 0x3ff, G5_method);
 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
 %}
-// Compiler ensures base is doubleword aligned and cnt is count of doublewords
-enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
-MacroAssembler _masm(&cbuf);
-Register    nof_bytes_arg   = reg_to_register_object($cnt$$reg);
-Register    nof_bytes_tmp    = reg_to_register_object($temp$$reg);
-Register    base_pointer_arg = reg_to_register_object($base$$reg);
-Label loop;
-__ mov(nof_bytes_arg, nof_bytes_tmp);
-// Loop and clear, walking backwards through the array.
-// nof_bytes_tmp (if >0) is always the number of bytes to zero
-__ bind(loop);
-__ deccc(nof_bytes_tmp, 8);
-__ br(Assembler::greaterEqual, true, Assembler::pt, loop);
-__ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
-// %%%% this mini-loop must not cross a cache boundary!
-%}
 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
 Label Ldone, Lloop;
 MacroAssembler _masm(&cbuf);
 __ cmp(str1_reg, str2_reg); //same char[] ?
 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
 __ delayed()->add(G0, 1, result_reg);
-__ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone);
+__ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
 __ delayed()->add(G0, 1, result_reg); // count == 0
 //rename registers
 Register limit_reg =    cnt_reg;
 Register  chr1_reg = result_reg;
 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
 // Compare char[] arrays aligned to 4 bytes.
 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
 chr1_reg, chr2_reg, Ldone);
-__ ba(false,Ldone);
+__ ba(Ldone);
 __ delayed()->add(G0, 1, result_reg);
 // char by char compare
 __ bind(Lchar);
 __ add(str1_reg, limit_reg, str1_reg);
 // return false if the two arrays are not equal length
 __ cmp(tmp1_reg, tmp2_reg);
 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
 __ delayed()->mov(G0, result_reg);     // not equal
-__ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone);
+__ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
 // load array addresses
 __ add(ary1_reg, base_offset, ary1_reg);
 __ add(ary2_reg, base_offset, ary2_reg);
 //----------Operand Attributes-------------------------------------------------
 op_attrib op_cost(1);          // Required cost attribute
 //----------Instruction Attributes---------------------------------------------
 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
-ins_attrib ins_size(32);       // Required size attribute (in bits)
+ins_attrib ins_size(32);           // Required size attribute (in bits)
-ins_attrib ins_pc_relative(0); // Required PC Relative flag
+ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
-ins_attrib ins_short_branch(0); // Required flag: is this instruction a
+ins_attrib ins_short_branch(0);    // Required flag: is this instruction a
 // non-matching short branch variant of some
 // long branch?
 //----------OPERANDS-----------------------------------------------------------
 // Operand definitions must precede instruction definitions for correct parsing
 // in the ADLC because operands constitute user defined types which are used in
 interface(CONST_INTER);
 %}
 // Integer Immediate: 8-bit
 operand immI8() %{
-predicate(Assembler::is_simm(n->get_int(), 8));
+predicate(Assembler::is_simm8(n->get_int()));
 match(ConI);
 op_cost(0);
 format %{ %}
 interface(CONST_INTER);
 %}
 interface(CONST_INTER);
 %}
 // Integer Immediate: 16-bit
 operand immI16() %{
-predicate(Assembler::is_simm(n->get_int(), 16));
+predicate(Assembler::is_simm16(n->get_int()));
 match(ConI);
 op_cost(0);
 format %{ %}
 interface(CONST_INTER);
 %}
 interface(CONST_INTER);
 %}
 // Integer Immediate: 11-bit
 operand immI11() %{
-predicate(Assembler::is_simm(n->get_int(),11));
+predicate(Assembler::is_simm11(n->get_int()));
+match(ConI);
+op_cost(0);
+format %{ %}
+interface(CONST_INTER);
+%}
+// Integer Immediate: 5-bit
+operand immI5() %{
+predicate(Assembler::is_simm5(n->get_int()));
 match(ConI);
 op_cost(0);
 format %{ %}
 interface(CONST_INTER);
 %}
 operand immL0() %{
 predicate(n->get_long() == 0L);
 match(ConL);
 op_cost(0);
 // formats are generated automatically for constants and base registers
+format %{ %}
+interface(CONST_INTER);
+%}
+// Integer Immediate: 5-bit
+operand immL5() %{
+predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
+match(ConL);
+op_cost(0);
 format %{ %}
 interface(CONST_INTER);
 %}
 // Long Immediate: 13-bit
 op1 : E(read);
 BR  : R;
 MS  : R;
 %}
+// Compare and branch
+pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
+instruction_count(2); has_delay_slot;
+cr    : E(write);
+src1  : R(read);
+src2  : R(read);
+IALU  : R;
+BR    : R;
+%}
+// Compare and branch
+pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
+instruction_count(2); has_delay_slot;
+cr    : E(write);
+src1  : R(read);
+IALU  : R;
+BR    : R;
+%}
+// Compare and branch using cbcond
+pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
+single_instruction;
+src1  : E(read);
+src2  : E(read);
+IALU  : R;
+BR    : R;
+%}
+// Compare and branch using cbcond
+pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
+single_instruction;
+src1  : E(read);
+IALU  : R;
+BR    : R;
+%}
 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
 single_instruction_with_delay_slot;
 cr    : E(read);
 BR    : R;
 %}
 // Must be safe to execute with invalid address (cannot fault).
 instruct prefetchr( memory mem ) %{
 match( PrefetchRead mem );
 ins_cost(MEMORY_REF_COST);
+size(4);
 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
 opcode(Assembler::prefetch_op3);
 ins_encode( form3_mem_prefetch_read( mem ) );
 ins_pipe(iload_mem);
 %}
 instruct prefetchw( memory mem ) %{
-predicate(AllocatePrefetchStyle != 3 );
 match( PrefetchWrite mem );
 ins_cost(MEMORY_REF_COST);
+size(4);
 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
 opcode(Assembler::prefetch_op3);
 ins_encode( form3_mem_prefetch_write( mem ) );
 ins_pipe(iload_mem);
 %}
-// Use BIS instruction to prefetch.
+// Prefetch instructions for allocation.
-instruct prefetchw_bis( memory mem ) %{
-predicate(AllocatePrefetchStyle == 3);
+instruct prefetchAlloc( memory mem ) %{
-match( PrefetchWrite mem );
+predicate(AllocatePrefetchInstr == 0);
+match( PrefetchAllocation mem );
 ins_cost(MEMORY_REF_COST);
+size(4);
-format %{ "STXA   G0,$mem\t! // Block initializing store" %}
-ins_encode %{
+format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
-Register base = as_Register($mem$$base);
+opcode(Assembler::prefetch_op3);
-int disp = $mem$$disp;
+ins_encode( form3_mem_prefetch_write( mem ) );
-if (disp != 0) {
+ins_pipe(iload_mem);
-__ add(base, AllocatePrefetchStepSize, base);
+%}
-}
-__ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P);
+// Use BIS instruction to prefetch for allocation.
+// Could fault, need space at the end of TLAB.
+instruct prefetchAlloc_bis( iRegP dst ) %{
+predicate(AllocatePrefetchInstr == 1);
+match( PrefetchAllocation dst );
+ins_cost(MEMORY_REF_COST);
+size(4);
+format %{ "STXA   [$dst]\t! // Prefetch allocation using BIS" %}
+ins_encode %{
+__ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
 %}
 ins_pipe(istore_mem_reg);
 %}
+// Next code is used for finding next cache line address to prefetch.
+#ifndef _LP64
+instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
+match(Set dst (CastX2P (AndI (CastP2X src) mask)));
+ins_cost(DEFAULT_COST);
+size(4);
+format %{ "AND    $src,$mask,$dst\t! next cache line address" %}
+ins_encode %{
+__ and3($src$$Register, $mask$$constant, $dst$$Register);
+%}
+ins_pipe(ialu_reg_imm);
+%}
+#else
+instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
+match(Set dst (CastX2P (AndL (CastP2X src) mask)));
+ins_cost(DEFAULT_COST);
+size(4);
+format %{ "AND    $src,$mask,$dst\t! next cache line address" %}
+ins_encode %{
+__ and3($src$$Register, $mask$$constant, $dst$$Register);
+%}
+ins_pipe(ialu_reg_imm);
+%}
+#endif
 //----------Store Instructions-------------------------------------------------
 // Store Byte
 instruct storeB(memory mem, iRegI src) %{
 match(Set mem (StoreB mem src));
 ins_encode( enc_membar_acquire );
 ins_pipe(long_memory_op);
 %}
 instruct membar_acquire_lock() %{
-match(MemBarAcquire);
+match(MemBarAcquireLock);
-predicate(Matcher::prior_fast_lock(n));
 ins_cost(0);
 size(0);
 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
 ins_encode( );
 ins_encode( enc_membar_release );
 ins_pipe(long_memory_op);
 %}
 instruct membar_release_lock() %{
-match(MemBarRelease);
+match(MemBarReleaseLock);
-predicate(Matcher::post_fast_unlock(n));
 ins_cost(0);
 size(0);
 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
 ins_encode( );
 "MOVlt  $tmp,$p\t! p' < 0 ? p'+y : p'" %}
 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
 ins_pipe( cadd_cmpltmask );
 %}
+//-----------------------------------------------------------------
+// Direct raw moves between float and general registers using VIS3.
+//  ins_pipe(faddF_reg);
+instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
+predicate(UseVIS >= 3);
+match(Set dst (MoveF2I src));
+format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
+ins_encode %{
+__ movstouw($src$$FloatRegister, $dst$$Register);
+%}
+ins_pipe(ialu_reg_reg);
+%}
+instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
+predicate(UseVIS >= 3);
+match(Set dst (MoveI2F src));
+format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
+ins_encode %{
+__ movwtos($src$$Register, $dst$$FloatRegister);
+%}
+ins_pipe(ialu_reg_reg);
+%}
+instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
+predicate(UseVIS >= 3);
+match(Set dst (MoveD2L src));
+format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
+ins_encode %{
+__ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
+%}
+ins_pipe(ialu_reg_reg);
+%}
+instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
+predicate(UseVIS >= 3);
+match(Set dst (MoveL2D src));
+format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
+ins_encode %{
+__ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
+%}
+ins_pipe(ialu_reg_reg);
+%}
+// Raw moves between float and general registers using stack.
+instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
+match(Set dst (MoveF2I src));
+effect(DEF dst, USE src);
+ins_cost(MEMORY_REF_COST);
+size(4);
+format %{ "LDUW   $src,$dst\t! MoveF2I" %}
+opcode(Assembler::lduw_op3);
+ins_encode(simple_form3_mem_reg( src, dst ) );
+ins_pipe(iload_mem);
+%}
+instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
+match(Set dst (MoveI2F src));
+effect(DEF dst, USE src);
+ins_cost(MEMORY_REF_COST);
+size(4);
+format %{ "LDF    $src,$dst\t! MoveI2F" %}
+opcode(Assembler::ldf_op3);
+ins_encode(simple_form3_mem_reg(src, dst));
+ins_pipe(floadF_stk);
+%}
+instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
+match(Set dst (MoveD2L src));
+effect(DEF dst, USE src);
+ins_cost(MEMORY_REF_COST);
+size(4);
+format %{ "LDX    $src,$dst\t! MoveD2L" %}
+opcode(Assembler::ldx_op3);
+ins_encode(simple_form3_mem_reg( src, dst ) );
+ins_pipe(iload_mem);
+%}
+instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
+match(Set dst (MoveL2D src));
+effect(DEF dst, USE src);
+ins_cost(MEMORY_REF_COST);
+size(4);
+format %{ "LDDF   $src,$dst\t! MoveL2D" %}
+opcode(Assembler::lddf_op3);
+ins_encode(simple_form3_mem_reg(src, dst));
+ins_pipe(floadD_stk);
+%}
+instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
+match(Set dst (MoveF2I src));
+effect(DEF dst, USE src);
+ins_cost(MEMORY_REF_COST);
+size(4);
+format %{ "STF   $src,$dst\t! MoveF2I" %}
+opcode(Assembler::stf_op3);
+ins_encode(simple_form3_mem_reg(dst, src));
+ins_pipe(fstoreF_stk_reg);
+%}
+instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
+match(Set dst (MoveI2F src));
+effect(DEF dst, USE src);
+ins_cost(MEMORY_REF_COST);
+size(4);
+format %{ "STW    $src,$dst\t! MoveI2F" %}
+opcode(Assembler::stw_op3);
+ins_encode(simple_form3_mem_reg( dst, src ) );
+ins_pipe(istore_mem_reg);
+%}
+instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
+match(Set dst (MoveD2L src));
+effect(DEF dst, USE src);
+ins_cost(MEMORY_REF_COST);
+size(4);
+format %{ "STDF   $src,$dst\t! MoveD2L" %}
+opcode(Assembler::stdf_op3);
+ins_encode(simple_form3_mem_reg(dst, src));
+ins_pipe(fstoreD_stk_reg);
+%}
+instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
+match(Set dst (MoveL2D src));
+effect(DEF dst, USE src);
+ins_cost(MEMORY_REF_COST);
+size(4);
+format %{ "STX    $src,$dst\t! MoveL2D" %}
+opcode(Assembler::stx_op3);
+ins_encode(simple_form3_mem_reg( dst, src ) );
+ins_pipe(istore_mem_reg);
+%}
 //----------Arithmetic Conversion Instructions---------------------------------
 // The conversions operations are all Alpha sorted.  Please keep it that way!
 instruct convD2F_reg(regF dst, regD src) %{
 match(Set dst (ConvD2F src));
 "skip:" %}
 ins_encode(form_d2i_helper(src,dst));
 ins_pipe(fcvtD2I);
 %}
-instruct convD2I_reg(stackSlotI dst, regD src) %{
+instruct convD2I_stk(stackSlotI dst, regD src) %{
 match(Set dst (ConvD2I src));
 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
 expand %{
 regF tmp;
 convD2I_helper(tmp, src);
 regF_to_stkI(dst, tmp);
 %}
 %}
+instruct convD2I_reg(iRegI dst, regD src) %{
+predicate(UseVIS >= 3);
+match(Set dst (ConvD2I src));
+ins_cost(DEFAULT_COST*2 + BRANCH_COST);
+expand %{
+regF tmp;
+convD2I_helper(tmp, src);
+MoveF2I_reg_reg(dst, tmp);
+%}
+%}
 // Convert a double to a long in a double register.
 // If the double is a NAN, stuff a zero in instead.
 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
 effect(DEF dst, USE src, KILL fcc0);
 "skip:" %}
 ins_encode(form_d2l_helper(src,dst));
 ins_pipe(fcvtD2L);
 %}
+instruct convD2L_stk(stackSlotL dst, regD src) %{
-// Double to Long conversion
-instruct convD2L_reg(stackSlotL dst, regD src) %{
 match(Set dst (ConvD2L src));
 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
 expand %{
 regD tmp;
 convD2L_helper(tmp, src);
 regD_to_stkL(dst, tmp);
 %}
 %}
+instruct convD2L_reg(iRegL dst, regD src) %{
+predicate(UseVIS >= 3);
+match(Set dst (ConvD2L src));
+ins_cost(DEFAULT_COST*2 + BRANCH_COST);
+expand %{
+regD tmp;
+convD2L_helper(tmp, src);
+MoveD2L_reg_reg(dst, tmp);
+%}
+%}
 instruct convF2D_reg(regD dst, regF src) %{
 match(Set dst (ConvF2D src));
 format %{ "FSTOD  $src,$dst" %}
 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
 ins_encode(form3_opf_rs2F_rdD(src, dst));
 ins_pipe(fcvtF2D);
 %}
+// Convert a float to an int in a float register.
+// If the float is a NAN, stuff a zero in instead.
 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
 effect(DEF dst, USE src, KILL fcc0);
 format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
 "FSTOI  $src,$dst\t! convert in delay slot\n\t"
 "skip:" %}
 ins_encode(form_f2i_helper(src,dst));
 ins_pipe(fcvtF2I);
 %}
-instruct convF2I_reg(stackSlotI dst, regF src) %{
+instruct convF2I_stk(stackSlotI dst, regF src) %{
 match(Set dst (ConvF2I src));
 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
 expand %{
 regF tmp;
 convF2I_helper(tmp, src);
 regF_to_stkI(dst, tmp);
 %}
 %}
+instruct convF2I_reg(iRegI dst, regF src) %{
+predicate(UseVIS >= 3);
+match(Set dst (ConvF2I src));
+ins_cost(DEFAULT_COST*2 + BRANCH_COST);
+expand %{
+regF tmp;
+convF2I_helper(tmp, src);
+MoveF2I_reg_reg(dst, tmp);
+%}
+%}
+// Convert a float to a long in a float register.
+// If the float is a NAN, stuff a zero in instead.
 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
 effect(DEF dst, USE src, KILL fcc0);
 format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
 "FSTOX  $src,$dst\t! convert in delay slot\n\t"
 "skip:" %}
 ins_encode(form_f2l_helper(src,dst));
 ins_pipe(fcvtF2L);
 %}
-// Float to Long conversion
+instruct convF2L_stk(stackSlotL dst, regF src) %{
-instruct convF2L_reg(stackSlotL dst, regF src) %{
 match(Set dst (ConvF2L src));
 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
 expand %{
 regD tmp;
 convF2L_helper(tmp, src);
 regD_to_stkL(dst, tmp);
 %}
 %}
+instruct convF2L_reg(iRegL dst, regF src) %{
+predicate(UseVIS >= 3);
+match(Set dst (ConvF2L src));
+ins_cost(DEFAULT_COST*2 + BRANCH_COST);
+expand %{
+regD tmp;
+convF2L_helper(tmp, src);
+MoveD2L_reg_reg(dst, tmp);
+%}
+%}
 instruct convI2D_helper(regD dst, regF tmp) %{
 effect(USE tmp, DEF dst);
 format %{ "FITOD  $tmp,$dst" %}
 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
 ins_pipe(fcvtI2D);
 %}
-instruct convI2D_reg(stackSlotI src, regD dst) %{
+instruct convI2D_stk(stackSlotI src, regD dst) %{
 match(Set dst (ConvI2D src));
 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
 expand %{
 regF tmp;
-stkI_to_regF( tmp, src);
+stkI_to_regF(tmp, src);
-convI2D_helper( dst, tmp);
+convI2D_helper(dst, tmp);
 %}
 %}
-instruct convI2D_mem( regD_low dst, memory mem ) %{
+instruct convI2D_reg(regD_low dst, iRegI src) %{
+predicate(UseVIS >= 3);
+match(Set dst (ConvI2D src));
+expand %{
+regF tmp;
+MoveI2F_reg_reg(tmp, src);
+convI2D_helper(dst, tmp);
+%}
+%}
+instruct convI2D_mem(regD_low dst, memory mem) %{
 match(Set dst (ConvI2D (LoadI mem)));
 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
 size(8);
 format %{ "LDF    $mem,$dst\n\t"
 "FITOD  $dst,$dst" %}
 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
 ins_pipe(fcvtI2F);
 %}
-instruct convI2F_reg( regF dst, stackSlotI src ) %{
+instruct convI2F_stk(regF dst, stackSlotI src) %{
 match(Set dst (ConvI2F src));
 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
 expand %{
 regF tmp;
 stkI_to_regF(tmp,src);
+convI2F_helper(dst, tmp);
+%}
+%}
+instruct convI2F_reg(regF dst, iRegI src) %{
+predicate(UseVIS >= 3);
+match(Set dst (ConvI2F src));
+ins_cost(DEFAULT_COST);
+expand %{
+regF tmp;
+MoveI2F_reg_reg(tmp, src);
 convI2F_helper(dst, tmp);
 %}
 %}
 instruct convI2F_mem( regF dst, memory mem ) %{
 size(4);
 format %{ "SRL    $src,0,$dst\t! zero-extend long" %}
 opcode(Assembler::srl_op3, Assembler::arith_op);
 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
 ins_pipe(ialu_reg_reg);
-%}
-instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
-match(Set dst (MoveF2I src));
-effect(DEF dst, USE src);
-ins_cost(MEMORY_REF_COST);
-size(4);
-format %{ "LDUW   $src,$dst\t! MoveF2I" %}
-opcode(Assembler::lduw_op3);
-ins_encode(simple_form3_mem_reg( src, dst ) );
-ins_pipe(iload_mem);
-%}
-instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
-match(Set dst (MoveI2F src));
-effect(DEF dst, USE src);
-ins_cost(MEMORY_REF_COST);
-size(4);
-format %{ "LDF    $src,$dst\t! MoveI2F" %}
-opcode(Assembler::ldf_op3);
-ins_encode(simple_form3_mem_reg(src, dst));
-ins_pipe(floadF_stk);
-%}
-instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
-match(Set dst (MoveD2L src));
-effect(DEF dst, USE src);
-ins_cost(MEMORY_REF_COST);
-size(4);
-format %{ "LDX    $src,$dst\t! MoveD2L" %}
-opcode(Assembler::ldx_op3);
-ins_encode(simple_form3_mem_reg( src, dst ) );
-ins_pipe(iload_mem);
-%}
-instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
-match(Set dst (MoveL2D src));
-effect(DEF dst, USE src);
-ins_cost(MEMORY_REF_COST);
-size(4);
-format %{ "LDDF   $src,$dst\t! MoveL2D" %}
-opcode(Assembler::lddf_op3);
-ins_encode(simple_form3_mem_reg(src, dst));
-ins_pipe(floadD_stk);
-%}
-instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
-match(Set dst (MoveF2I src));
-effect(DEF dst, USE src);
-ins_cost(MEMORY_REF_COST);
-size(4);
-format %{ "STF   $src,$dst\t!MoveF2I" %}
-opcode(Assembler::stf_op3);
-ins_encode(simple_form3_mem_reg(dst, src));
-ins_pipe(fstoreF_stk_reg);
-%}
-instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
-match(Set dst (MoveI2F src));
-effect(DEF dst, USE src);
-ins_cost(MEMORY_REF_COST);
-size(4);
-format %{ "STW    $src,$dst\t!MoveI2F" %}
-opcode(Assembler::stw_op3);
-ins_encode(simple_form3_mem_reg( dst, src ) );
-ins_pipe(istore_mem_reg);
-%}
-instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
-match(Set dst (MoveD2L src));
-effect(DEF dst, USE src);
-ins_cost(MEMORY_REF_COST);
-size(4);
-format %{ "STDF   $src,$dst\t!MoveD2L" %}
-opcode(Assembler::stdf_op3);
-ins_encode(simple_form3_mem_reg(dst, src));
-ins_pipe(fstoreD_stk_reg);
-%}
-instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
-match(Set dst (MoveL2D src));
-effect(DEF dst, USE src);
-ins_cost(MEMORY_REF_COST);
-size(4);
-format %{ "STX    $src,$dst\t!MoveL2D" %}
-opcode(Assembler::stx_op3);
-ins_encode(simple_form3_mem_reg( dst, src ) );
-ins_pipe(istore_mem_reg);
 %}
 //-----------
 // Long to Double conversion using V8 opcodes.
 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
 ins_pipe(fcvtL2D);
 %}
-instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
+instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
 predicate(VM_Version::has_fast_fxtof());
 match(Set dst (ConvL2D src));
 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
 expand %{
 regD tmp;
 stkL_to_regD(tmp, src);
 convL2D_helper(dst, tmp);
 %}
 %}
-//-----------
+instruct convL2D_reg(regD dst, iRegL src) %{
-// Long to Float conversion using V8 opcodes.
+predicate(UseVIS >= 3);
-// Still useful because cheetah traps and becomes
+match(Set dst (ConvL2D src));
-// amazingly slow for some common numbers.
+expand %{
+regD tmp;
+MoveL2D_reg_reg(tmp, src);
+convL2D_helper(dst, tmp);
+%}
+%}
 // Long to Float conversion using fast fxtof
 instruct convL2F_helper(regF dst, regD tmp) %{
 effect(DEF dst, USE tmp);
 size(4);
 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
 ins_pipe(fcvtL2F);
 %}
-instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
+instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
 match(Set dst (ConvL2F src));
 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
 expand %{
 regD tmp;
 stkL_to_regD(tmp, src);
 convL2F_helper(dst, tmp);
 %}
 %}
+instruct convL2F_reg(regF dst, iRegL src) %{
+predicate(UseVIS >= 3);
+match(Set dst (ConvL2F src));
+ins_cost(DEFAULT_COST);
+expand %{
+regD tmp;
+MoveL2D_reg_reg(tmp, src);
+convL2F_helper(dst, tmp);
+%}
+%}
 //-----------
 instruct convL2I_reg(iRegI dst, iRegL src) %{
 match(Set dst (ConvL2I src));
 #ifndef _LP64
 ins_cost(350);
 format %{  "ADD    $constanttablebase, $constantoffset, O7\n\t"
 "LD     [O7 + $switch_val], O7\n\t"
-"JUMP   O7"
+"JUMP   O7" %}
-%}
 ins_encode %{
 // Calculate table address into a register.
 Register table_reg;
 Register label_reg = O7;
-if (constant_offset() == 0) {
+// If we are calculating the size of this instruction don't trust
+// zero offsets because they might change when
+// MachConstantBaseNode decides to optimize the constant table
+// base.
+if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
 table_reg = $constanttablebase;
 } else {
 table_reg = O7;
 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
 __ add($constanttablebase, con_offset, table_reg);
 // Jump to base address + switch value
 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
 __ jmp(label_reg, G0);
 __ delayed()->nop();
 %}
-ins_pc_relative(1);
 ins_pipe(ialu_reg_reg);
 %}
 // Direct Branch.  Use V8 version with longer range.
 instruct branch(label labl) %{
 effect(USE labl);
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "BA     $labl" %}
-// Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
+ins_encode %{
-opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
+Label* L = $labl$$label;
-ins_encode( enc_ba( labl ) );
+__ ba(*L);
-ins_pc_relative(1);
+__ delayed()->nop();
+%}
 ins_pipe(br);
+%}
+// Direct Branch, short with no delay slot
+instruct branch_short(label labl) %{
+match(Goto);
+predicate(UseCBCond);
+effect(USE labl);
+size(4);
+ins_cost(BRANCH_COST);
+format %{ "BA     $labl\t! short branch" %}
+ins_encode %{
+Label* L = $labl$$label;
+assert(__ use_cbcond(*L), "back to back cbcond");
+__ ba_short(*L);
+%}
+ins_short_branch(1);
+ins_avoid_back_to_back(1);
+ins_pipe(cbcond_reg_imm);
 %}
 // Conditional Direct Branch
 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
 match(If cmp icc);
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "BP$cmp   $icc,$labl" %}
 // Prim = bits 24-22, Secnd = bits 31-30
 ins_encode( enc_bp( labl, cmp, icc ) );
-ins_pc_relative(1);
 ins_pipe(br_cc);
+%}
+instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
+match(If cmp icc);
+effect(USE labl);
+ins_cost(BRANCH_COST);
+format %{ "BP$cmp  $icc,$labl" %}
+// Prim = bits 24-22, Secnd = bits 31-30
+ins_encode( enc_bp( labl, cmp, icc ) );
+ins_pipe(br_cc);
+%}
+instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
+match(If cmp pcc);
+effect(USE labl);
+size(8);
+ins_cost(BRANCH_COST);
+format %{ "BP$cmp  $pcc,$labl" %}
+ins_encode %{
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
+__ delayed()->nop();
+%}
+ins_pipe(br_cc);
+%}
+instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
+match(If cmp fcc);
+effect(USE labl);
+size(8);
+ins_cost(BRANCH_COST);
+format %{ "FBP$cmp $fcc,$labl" %}
+ins_encode %{
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
+__ delayed()->nop();
+%}
+ins_pipe(br_fcc);
+%}
+instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
+match(CountedLoopEnd cmp icc);
+effect(USE labl);
+size(8);
+ins_cost(BRANCH_COST);
+format %{ "BP$cmp   $icc,$labl\t! Loop end" %}
+// Prim = bits 24-22, Secnd = bits 31-30
+ins_encode( enc_bp( labl, cmp, icc ) );
+ins_pipe(br_cc);
+%}
+instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
+match(CountedLoopEnd cmp icc);
+effect(USE labl);
+size(8);
+ins_cost(BRANCH_COST);
+format %{ "BP$cmp  $icc,$labl\t! Loop end" %}
+// Prim = bits 24-22, Secnd = bits 31-30
+ins_encode( enc_bp( labl, cmp, icc ) );
+ins_pipe(br_cc);
+%}
+// Compare and branch instructions
+instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
+match(If cmp (CmpI op1 op2));
+effect(USE labl, KILL icc);
+size(12);
+ins_cost(BRANCH_COST);
+format %{ "CMP    $op1,$op2\t! int\n\t"
+"BP$cmp   $labl" %}
+ins_encode %{
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ cmp($op1$$Register, $op2$$Register);
+__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
+__ delayed()->nop();
+%}
+ins_pipe(cmp_br_reg_reg);
+%}
+instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
+match(If cmp (CmpI op1 op2));
+effect(USE labl, KILL icc);
+size(12);
+ins_cost(BRANCH_COST);
+format %{ "CMP    $op1,$op2\t! int\n\t"
+"BP$cmp   $labl" %}
+ins_encode %{
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ cmp($op1$$Register, $op2$$constant);
+__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
+__ delayed()->nop();
+%}
+ins_pipe(cmp_br_reg_imm);
+%}
+instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
+match(If cmp (CmpU op1 op2));
+effect(USE labl, KILL icc);
+size(12);
+ins_cost(BRANCH_COST);
+format %{ "CMP    $op1,$op2\t! unsigned\n\t"
+"BP$cmp  $labl" %}
+ins_encode %{
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ cmp($op1$$Register, $op2$$Register);
+__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
+__ delayed()->nop();
+%}
+ins_pipe(cmp_br_reg_reg);
+%}
+instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
+match(If cmp (CmpU op1 op2));
+effect(USE labl, KILL icc);
+size(12);
+ins_cost(BRANCH_COST);
+format %{ "CMP    $op1,$op2\t! unsigned\n\t"
+"BP$cmp  $labl" %}
+ins_encode %{
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ cmp($op1$$Register, $op2$$constant);
+__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
+__ delayed()->nop();
+%}
+ins_pipe(cmp_br_reg_imm);
+%}
+instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
+match(If cmp (CmpL op1 op2));
+effect(USE labl, KILL xcc);
+size(12);
+ins_cost(BRANCH_COST);
+format %{ "CMP    $op1,$op2\t! long\n\t"
+"BP$cmp   $labl" %}
+ins_encode %{
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ cmp($op1$$Register, $op2$$Register);
+__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
+__ delayed()->nop();
+%}
+ins_pipe(cmp_br_reg_reg);
+%}
+instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
+match(If cmp (CmpL op1 op2));
+effect(USE labl, KILL xcc);
+size(12);
+ins_cost(BRANCH_COST);
+format %{ "CMP    $op1,$op2\t! long\n\t"
+"BP$cmp   $labl" %}
+ins_encode %{
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ cmp($op1$$Register, $op2$$constant);
+__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
+__ delayed()->nop();
+%}
+ins_pipe(cmp_br_reg_imm);
+%}
+// Compare Pointers and branch
+instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
+match(If cmp (CmpP op1 op2));
+effect(USE labl, KILL pcc);
+size(12);
+ins_cost(BRANCH_COST);
+format %{ "CMP    $op1,$op2\t! ptr\n\t"
+"B$cmp   $labl" %}
+ins_encode %{
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ cmp($op1$$Register, $op2$$Register);
+__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
+__ delayed()->nop();
+%}
+ins_pipe(cmp_br_reg_reg);
+%}
+instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
+match(If cmp (CmpP op1 null));
+effect(USE labl, KILL pcc);
+size(12);
+ins_cost(BRANCH_COST);
+format %{ "CMP    $op1,0\t! ptr\n\t"
+"B$cmp   $labl" %}
+ins_encode %{
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ cmp($op1$$Register, G0);
+// bpr() is not used here since it has shorter distance.
+__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
+__ delayed()->nop();
+%}
+ins_pipe(cmp_br_reg_reg);
+%}
+instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
+match(If cmp (CmpN op1 op2));
+effect(USE labl, KILL icc);
+size(12);
+ins_cost(BRANCH_COST);
+format %{ "CMP    $op1,$op2\t! compressed ptr\n\t"
+"BP$cmp   $labl" %}
+ins_encode %{
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ cmp($op1$$Register, $op2$$Register);
+__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
+__ delayed()->nop();
+%}
+ins_pipe(cmp_br_reg_reg);
+%}
+instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
+match(If cmp (CmpN op1 null));
+effect(USE labl, KILL icc);
+size(12);
+ins_cost(BRANCH_COST);
+format %{ "CMP    $op1,0\t! compressed ptr\n\t"
+"BP$cmp   $labl" %}
+ins_encode %{
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ cmp($op1$$Register, G0);
+__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
+__ delayed()->nop();
+%}
+ins_pipe(cmp_br_reg_reg);
+%}
+// Loop back branch
+instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
+match(CountedLoopEnd cmp (CmpI op1 op2));
+effect(USE labl, KILL icc);
+size(12);
+ins_cost(BRANCH_COST);
+format %{ "CMP    $op1,$op2\t! int\n\t"
+"BP$cmp   $labl\t! Loop end" %}
+ins_encode %{
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ cmp($op1$$Register, $op2$$Register);
+__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
+__ delayed()->nop();
+%}
+ins_pipe(cmp_br_reg_reg);
+%}
+instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
+match(CountedLoopEnd cmp (CmpI op1 op2));
+effect(USE labl, KILL icc);
+size(12);
+ins_cost(BRANCH_COST);
+format %{ "CMP    $op1,$op2\t! int\n\t"
+"BP$cmp   $labl\t! Loop end" %}
+ins_encode %{
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ cmp($op1$$Register, $op2$$constant);
+__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
+__ delayed()->nop();
+%}
+ins_pipe(cmp_br_reg_imm);
+%}
+// Short compare and branch instructions
+instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
+match(If cmp (CmpI op1 op2));
+predicate(UseCBCond);
+effect(USE labl, KILL icc);
+size(4);
+ins_cost(BRANCH_COST);
+format %{ "CWB$cmp  $op1,$op2,$labl\t! int" %}
+ins_encode %{
+Label* L = $labl$$label;
+assert(__ use_cbcond(*L), "back to back cbcond");
+__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
+%}
+ins_short_branch(1);
+ins_avoid_back_to_back(1);
+ins_pipe(cbcond_reg_reg);
+%}
+instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
+match(If cmp (CmpI op1 op2));
+predicate(UseCBCond);
+effect(USE labl, KILL icc);
+size(4);
+ins_cost(BRANCH_COST);
+format %{ "CWB$cmp  $op1,$op2,$labl\t! int" %}
+ins_encode %{
+Label* L = $labl$$label;
+assert(__ use_cbcond(*L), "back to back cbcond");
+__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
+%}
+ins_short_branch(1);
+ins_avoid_back_to_back(1);
+ins_pipe(cbcond_reg_imm);
+%}
+instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
+match(If cmp (CmpU op1 op2));
+predicate(UseCBCond);
+effect(USE labl, KILL icc);
+size(4);
+ins_cost(BRANCH_COST);
+format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
+ins_encode %{
+Label* L = $labl$$label;
+assert(__ use_cbcond(*L), "back to back cbcond");
+__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
+%}
+ins_short_branch(1);
+ins_avoid_back_to_back(1);
+ins_pipe(cbcond_reg_reg);
+%}
+instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
+match(If cmp (CmpU op1 op2));
+predicate(UseCBCond);
+effect(USE labl, KILL icc);
+size(4);
+ins_cost(BRANCH_COST);
+format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
+ins_encode %{
+Label* L = $labl$$label;
+assert(__ use_cbcond(*L), "back to back cbcond");
+__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
+%}
+ins_short_branch(1);
+ins_avoid_back_to_back(1);
+ins_pipe(cbcond_reg_imm);
+%}
+instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
+match(If cmp (CmpL op1 op2));
+predicate(UseCBCond);
+effect(USE labl, KILL xcc);
+size(4);
+ins_cost(BRANCH_COST);
+format %{ "CXB$cmp  $op1,$op2,$labl\t! long" %}
+ins_encode %{
+Label* L = $labl$$label;
+assert(__ use_cbcond(*L), "back to back cbcond");
+__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
+%}
+ins_short_branch(1);
+ins_avoid_back_to_back(1);
+ins_pipe(cbcond_reg_reg);
+%}
+instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
+match(If cmp (CmpL op1 op2));
+predicate(UseCBCond);
+effect(USE labl, KILL xcc);
+size(4);
+ins_cost(BRANCH_COST);
+format %{ "CXB$cmp  $op1,$op2,$labl\t! long" %}
+ins_encode %{
+Label* L = $labl$$label;
+assert(__ use_cbcond(*L), "back to back cbcond");
+__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
+%}
+ins_short_branch(1);
+ins_avoid_back_to_back(1);
+ins_pipe(cbcond_reg_imm);
+%}
+// Compare Pointers and branch
+instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
+match(If cmp (CmpP op1 op2));
+predicate(UseCBCond);
+effect(USE labl, KILL pcc);
+size(4);
+ins_cost(BRANCH_COST);
+#ifdef _LP64
+format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
+#else
+format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
+#endif
+ins_encode %{
+Label* L = $labl$$label;
+assert(__ use_cbcond(*L), "back to back cbcond");
+__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
+%}
+ins_short_branch(1);
+ins_avoid_back_to_back(1);
+ins_pipe(cbcond_reg_reg);
+%}
+instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
+match(If cmp (CmpP op1 null));
+predicate(UseCBCond);
+effect(USE labl, KILL pcc);
+size(4);
+ins_cost(BRANCH_COST);
+#ifdef _LP64
+format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
+#else
+format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
+#endif
+ins_encode %{
+Label* L = $labl$$label;
+assert(__ use_cbcond(*L), "back to back cbcond");
+__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
+%}
+ins_short_branch(1);
+ins_avoid_back_to_back(1);
+ins_pipe(cbcond_reg_reg);
+%}
+instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
+match(If cmp (CmpN op1 op2));
+predicate(UseCBCond);
+effect(USE labl, KILL icc);
+size(4);
+ins_cost(BRANCH_COST);
+format %{ "CWB$cmp  $op1,op2,$labl\t! compressed ptr" %}
+ins_encode %{
+Label* L = $labl$$label;
+assert(__ use_cbcond(*L), "back to back cbcond");
+__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
+%}
+ins_short_branch(1);
+ins_avoid_back_to_back(1);
+ins_pipe(cbcond_reg_reg);
+%}
+instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
+match(If cmp (CmpN op1 null));
+predicate(UseCBCond);
+effect(USE labl, KILL icc);
+size(4);
+ins_cost(BRANCH_COST);
+format %{ "CWB$cmp  $op1,0,$labl\t! compressed ptr" %}
+ins_encode %{
+Label* L = $labl$$label;
+assert(__ use_cbcond(*L), "back to back cbcond");
+__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
+%}
+ins_short_branch(1);
+ins_avoid_back_to_back(1);
+ins_pipe(cbcond_reg_reg);
+%}
+// Loop back branch
+instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
+match(CountedLoopEnd cmp (CmpI op1 op2));
+predicate(UseCBCond);
+effect(USE labl, KILL icc);
+size(4);
+ins_cost(BRANCH_COST);
+format %{ "CWB$cmp  $op1,$op2,$labl\t! Loop end" %}
+ins_encode %{
+Label* L = $labl$$label;
+assert(__ use_cbcond(*L), "back to back cbcond");
+__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
+%}
+ins_short_branch(1);
+ins_avoid_back_to_back(1);
+ins_pipe(cbcond_reg_reg);
+%}
+instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
+match(CountedLoopEnd cmp (CmpI op1 op2));
+predicate(UseCBCond);
+effect(USE labl, KILL icc);
+size(4);
+ins_cost(BRANCH_COST);
+format %{ "CWB$cmp  $op1,$op2,$labl\t! Loop end" %}
+ins_encode %{
+Label* L = $labl$$label;
+assert(__ use_cbcond(*L), "back to back cbcond");
+__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
+%}
+ins_short_branch(1);
+ins_avoid_back_to_back(1);
+ins_pipe(cbcond_reg_imm);
 %}
 // Branch-on-register tests all 64 bits.  We assume that values
 // in 64-bit registers always remains zero or sign extended
 // unless our code munges the high bits.  Interrupts can chop
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "BR$cmp   $op1,$labl" %}
 ins_encode( enc_bpr( labl, cmp, op1 ) );
-ins_pc_relative(1);
 ins_pipe(br_reg);
 %}
 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
 match(If cmp (CmpP op1 null));
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "BR$cmp   $op1,$labl" %}
 ins_encode( enc_bpr( labl, cmp, op1 ) );
-ins_pc_relative(1);
 ins_pipe(br_reg);
 %}
 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
 match(If cmp (CmpL op1 zero));
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "BR$cmp   $op1,$labl" %}
 ins_encode( enc_bpr( labl, cmp, op1 ) );
-ins_pc_relative(1);
 ins_pipe(br_reg);
 %}
-instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
-match(If cmp icc);
-effect(USE labl);
-format %{ "BP$cmp  $icc,$labl" %}
-// Prim = bits 24-22, Secnd = bits 31-30
-ins_encode( enc_bp( labl, cmp, icc ) );
-ins_pc_relative(1);
-ins_pipe(br_cc);
-%}
-instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
-match(If cmp pcc);
-effect(USE labl);
-size(8);
-ins_cost(BRANCH_COST);
-format %{ "BP$cmp  $pcc,$labl" %}
-// Prim = bits 24-22, Secnd = bits 31-30
-ins_encode( enc_bpx( labl, cmp, pcc ) );
-ins_pc_relative(1);
-ins_pipe(br_cc);
-%}
-instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
-match(If cmp fcc);
-effect(USE labl);
-size(8);
-ins_cost(BRANCH_COST);
-format %{ "FBP$cmp $fcc,$labl" %}
-// Prim = bits 24-22, Secnd = bits 31-30
-ins_encode( enc_fbp( labl, cmp, fcc ) );
-ins_pc_relative(1);
-ins_pipe(br_fcc);
-%}
-instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
-match(CountedLoopEnd cmp icc);
-effect(USE labl);
-size(8);
-ins_cost(BRANCH_COST);
-format %{ "BP$cmp   $icc,$labl\t! Loop end" %}
-// Prim = bits 24-22, Secnd = bits 31-30
-ins_encode( enc_bp( labl, cmp, icc ) );
-ins_pc_relative(1);
-ins_pipe(br_cc);
-%}
-instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
-match(CountedLoopEnd cmp icc);
-effect(USE labl);
-size(8);
-ins_cost(BRANCH_COST);
-format %{ "BP$cmp  $icc,$labl\t! Loop end" %}
-// Prim = bits 24-22, Secnd = bits 31-30
-ins_encode( enc_bp( labl, cmp, icc ) );
-ins_pc_relative(1);
-ins_pipe(br_cc);
-%}
 // ============================================================================
 // Long Compare
 //
 // Currently we hold longs in 2 registers.  Comparing such values efficiently
 effect(USE labl);
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "BP$cmp   $xcc,$labl" %}
-// Prim = bits 24-22, Secnd = bits 31-30
+ins_encode %{
-ins_encode( enc_bpl( labl, cmp, xcc ) );
+Label* L = $labl$$label;
-ins_pc_relative(1);
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
+__ delayed()->nop();
+%}
 ins_pipe(br_cc);
 %}
 // Manifest a CmpL3 result in an integer register.  Very painful.
 // This is the test to avoid.
 size(8);
 ins_cost(CALL_COST);
 format %{ "CALL,static  ; NOP ==> " %}
 ins_encode( Java_Static_Call( meth ), call_epilog );
-ins_pc_relative(1);
 ins_pipe(simple_call);
 %}
 // Call Java Static Instruction (method handle version)
 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
 match(CallStaticJava);
 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
 effect(USE meth, KILL l7_mh_SP_save);
-size(8);
+size(16);
 ins_cost(CALL_COST);
 format %{ "CALL,static/MethodHandle" %}
 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
-ins_pc_relative(1);
 ins_pipe(simple_call);
 %}
 // Call Java Dynamic Instruction
 instruct CallDynamicJavaDirect( method meth ) %{
 ins_cost(CALL_COST);
 format %{ "SET    (empty),R_G5\n\t"
 "CALL,dynamic  ; NOP ==> " %}
 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
-ins_pc_relative(1);
 ins_pipe(call);
 %}
 // Call Runtime Instruction
 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
 effect(USE meth, KILL l7);
 ins_cost(CALL_COST);
 format %{ "CALL,runtime" %}
 ins_encode( Java_To_Runtime( meth ),
 call_epilog, adjust_long_from_native_call );
-ins_pc_relative(1);
 ins_pipe(simple_call);
 %}
 // Call runtime without safepoint - same as CallRuntime
 instruct CallLeafDirect(method meth, l7RegP l7) %{
 ins_cost(CALL_COST);
 format %{ "CALL,runtime leaf" %}
 ins_encode( Java_To_Runtime( meth ),
 call_epilog,
 adjust_long_from_native_call );
-ins_pc_relative(1);
 ins_pipe(simple_call);
 %}
 // Call runtime without safepoint - same as CallLeaf
 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
 ins_cost(CALL_COST);
 format %{ "CALL,runtime leaf nofp" %}
 ins_encode( Java_To_Runtime( meth ),
 call_epilog,
 adjust_long_from_native_call );
-ins_pc_relative(1);
 ins_pipe(simple_call);
 %}
 // Tail Call; Jump from runtime stub to Java code.
 // Also known as an 'interprocedural jump'.
 match(Set pcc (FastLock object box));
 effect(KILL scratch, TEMP scratch2);
 ins_cost(100);
-size(4*112);       // conservative overestimation ...
 format %{ "FASTLOCK  $object, $box; KILL $scratch, $scratch2, $box" %}
 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
 ins_pipe(long_memory_op);
 %}
 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
 match(Set pcc (FastUnlock object box));
 effect(KILL scratch, TEMP scratch2);
 ins_cost(100);
-size(4*120);       // conservative overestimation ...
 format %{ "FASTUNLOCK  $object, $box; KILL $scratch, $scratch2, $box" %}
 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
 ins_pipe(long_memory_op);
 %}
-// Count and Base registers are fixed because the allocator cannot
+// The encodings are generic.
-// kill unknown registers.  The encodings are generic.
 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
+predicate(!use_block_zeroing(n->in(2)) );
 match(Set dummy (ClearArray cnt base));
 effect(TEMP temp, KILL ccr);
 ins_cost(300);
 format %{ "MOV    $cnt,$temp\n"
 "loop:   SUBcc  $temp,8,$temp\t! Count down a dword of bytes\n"
 "        BRge   loop\t\t! Clearing loop\n"
 "        STX    G0,[$base+$temp]\t! delay slot" %}
-ins_encode( enc_Clear_Array(cnt, base, temp) );
+ins_encode %{
+// Compiler ensures base is doubleword aligned and cnt is count of doublewords
+Register nof_bytes_arg    = $cnt$$Register;
+Register nof_bytes_tmp    = $temp$$Register;
+Register base_pointer_arg = $base$$Register;
+Label loop;
+__ mov(nof_bytes_arg, nof_bytes_tmp);
+// Loop and clear, walking backwards through the array.
+// nof_bytes_tmp (if >0) is always the number of bytes to zero
+__ bind(loop);
+__ deccc(nof_bytes_tmp, 8);
+__ br(Assembler::greaterEqual, true, Assembler::pt, loop);
+__ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
+// %%%% this mini-loop must not cross a cache boundary!
+%}
+ins_pipe(long_memory_op);
+%}
+instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
+predicate(use_block_zeroing(n->in(2)));
+match(Set dummy (ClearArray cnt base));
+effect(USE_KILL cnt, USE_KILL base, KILL ccr);
+ins_cost(300);
+format %{ "CLEAR  [$base, $cnt]\t! ClearArray" %}
+ins_encode %{
+assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
+Register to    = $base$$Register;
+Register count = $cnt$$Register;
+Label Ldone;
+__ nop(); // Separate short branches
+// Use BIS for zeroing (temp is not used).
+__ bis_zeroing(to, count, G0, Ldone);
+__ bind(Ldone);
+%}
+ins_pipe(long_memory_op);
+%}
+instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
+predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
+match(Set dummy (ClearArray cnt base));
+effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
+ins_cost(300);
+format %{ "CLEAR  [$base, $cnt]\t! ClearArray" %}
+ins_encode %{
+assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
+Register to    = $base$$Register;
+Register count = $cnt$$Register;
+Register temp  = $tmp$$Register;
+Label Ldone;
+__ nop(); // Separate short branches
+// Use BIS for zeroing
+__ bis_zeroing(to, count, temp, Ldone);
+__ bind(Ldone);
+%}
 ins_pipe(long_memory_op);
 %}
 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
 o7RegI tmp, flagsReg ccr) %{
 __ popc(Rdst, Rdst);
 %}
 ins_pipe(ialu_reg);
 %}
-instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{
+instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
 predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
 match(Set dst (CountTrailingZerosL src));
 effect(TEMP dst, KILL cr);
 // return popc(~x & (x - 1));

Mercurial > hg > truffle

comparison src/cpu/sparc/vm/sparc.ad @ 4137:04b9a2566eec