Mercurial > hg > truffle
comparison src/cpu/x86/vm/x86_32.ad @ 17726:085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
Reviewed-by: kvn, iveresov
author | rbackman |
---|---|
date | Thu, 23 Jan 2014 12:08:28 +0100 |
parents | 4d4ea046d32a |
children | 8a8ff6b577ed |
comparison
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deleted
inserted
replaced
17725:b4ce4e9eb97d | 17726:085b304a1cc5 |
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1532 | 1532 |
1533 const RegMask Matcher::method_handle_invoke_SP_save_mask() { | 1533 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
1534 return EBP_REG_mask(); | 1534 return EBP_REG_mask(); |
1535 } | 1535 } |
1536 | 1536 |
1537 const RegMask Matcher::mathExactI_result_proj_mask() { | |
1538 return EAX_REG_mask(); | |
1539 } | |
1540 | |
1541 const RegMask Matcher::mathExactL_result_proj_mask() { | |
1542 ShouldNotReachHere(); | |
1543 return RegMask(); | |
1544 } | |
1545 | |
1546 const RegMask Matcher::mathExactI_flags_proj_mask() { | |
1547 return INT_FLAGS_mask(); | |
1548 } | |
1549 | |
1550 // Returns true if the high 32 bits of the value is known to be zero. | 1537 // Returns true if the high 32 bits of the value is known to be zero. |
1551 bool is_operand_hi32_zero(Node* n) { | 1538 bool is_operand_hi32_zero(Node* n) { |
1552 int opc = n->Opcode(); | 1539 int opc = n->Opcode(); |
1553 if (opc == Op_AndL) { | 1540 if (opc == Op_AndL) { |
1554 Node* o2 = n->in(2); | 1541 Node* o2 = n->in(2); |
6997 %} | 6984 %} |
6998 | 6985 |
6999 //----------Arithmetic Instructions-------------------------------------------- | 6986 //----------Arithmetic Instructions-------------------------------------------- |
7000 //----------Addition Instructions---------------------------------------------- | 6987 //----------Addition Instructions---------------------------------------------- |
7001 | 6988 |
7002 instruct addExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr) | |
7003 %{ | |
7004 match(AddExactI dst src); | |
7005 effect(DEF cr); | |
7006 | |
7007 format %{ "ADD $dst, $src\t# addExact int" %} | |
7008 ins_encode %{ | |
7009 __ addl($dst$$Register, $src$$Register); | |
7010 %} | |
7011 ins_pipe(ialu_reg_reg); | |
7012 %} | |
7013 | |
7014 instruct addExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr) | |
7015 %{ | |
7016 match(AddExactI dst src); | |
7017 effect(DEF cr); | |
7018 | |
7019 format %{ "ADD $dst, $src\t# addExact int" %} | |
7020 ins_encode %{ | |
7021 __ addl($dst$$Register, $src$$constant); | |
7022 %} | |
7023 ins_pipe(ialu_reg_reg); | |
7024 %} | |
7025 | |
7026 instruct addExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr) | |
7027 %{ | |
7028 match(AddExactI dst (LoadI src)); | |
7029 effect(DEF cr); | |
7030 | |
7031 ins_cost(125); | |
7032 format %{ "ADD $dst,$src\t# addExact int" %} | |
7033 ins_encode %{ | |
7034 __ addl($dst$$Register, $src$$Address); | |
7035 %} | |
7036 ins_pipe( ialu_reg_mem ); | |
7037 %} | |
7038 | |
7039 | |
7040 // Integer Addition Instructions | 6989 // Integer Addition Instructions |
7041 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ | 6990 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
7042 match(Set dst (AddI dst src)); | 6991 match(Set dst (AddI dst src)); |
7043 effect(KILL cr); | 6992 effect(KILL cr); |
7044 | 6993 |
7344 ins_pipe( pipe_cmpxchg ); | 7293 ins_pipe( pipe_cmpxchg ); |
7345 %} | 7294 %} |
7346 | 7295 |
7347 //----------Subtraction Instructions------------------------------------------- | 7296 //----------Subtraction Instructions------------------------------------------- |
7348 | 7297 |
7349 instruct subExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr) | |
7350 %{ | |
7351 match(SubExactI dst src); | |
7352 effect(DEF cr); | |
7353 | |
7354 format %{ "SUB $dst, $src\t# subExact int" %} | |
7355 ins_encode %{ | |
7356 __ subl($dst$$Register, $src$$Register); | |
7357 %} | |
7358 ins_pipe(ialu_reg_reg); | |
7359 %} | |
7360 | |
7361 instruct subExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr) | |
7362 %{ | |
7363 match(SubExactI dst src); | |
7364 effect(DEF cr); | |
7365 | |
7366 format %{ "SUB $dst, $src\t# subExact int" %} | |
7367 ins_encode %{ | |
7368 __ subl($dst$$Register, $src$$constant); | |
7369 %} | |
7370 ins_pipe(ialu_reg_reg); | |
7371 %} | |
7372 | |
7373 instruct subExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr) | |
7374 %{ | |
7375 match(SubExactI dst (LoadI src)); | |
7376 effect(DEF cr); | |
7377 | |
7378 ins_cost(125); | |
7379 format %{ "SUB $dst,$src\t# subExact int" %} | |
7380 ins_encode %{ | |
7381 __ subl($dst$$Register, $src$$Address); | |
7382 %} | |
7383 ins_pipe( ialu_reg_mem ); | |
7384 %} | |
7385 | |
7386 // Integer Subtraction Instructions | 7298 // Integer Subtraction Instructions |
7387 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ | 7299 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
7388 match(Set dst (SubI dst src)); | 7300 match(Set dst (SubI dst src)); |
7389 effect(KILL cr); | 7301 effect(KILL cr); |
7390 | 7302 |
7447 size(2); | 7359 size(2); |
7448 format %{ "NEG $dst" %} | 7360 format %{ "NEG $dst" %} |
7449 opcode(0xF7,0x03); // Opcode F7 /3 | 7361 opcode(0xF7,0x03); // Opcode F7 /3 |
7450 ins_encode( OpcP, RegOpc( dst ) ); | 7362 ins_encode( OpcP, RegOpc( dst ) ); |
7451 ins_pipe( ialu_reg ); | 7363 ins_pipe( ialu_reg ); |
7452 %} | |
7453 | |
7454 instruct negExactI_eReg(eAXRegI dst, eFlagsReg cr) %{ | |
7455 match(NegExactI dst); | |
7456 effect(DEF cr); | |
7457 | |
7458 format %{ "NEG $dst\t# negExact int"%} | |
7459 ins_encode %{ | |
7460 __ negl($dst$$Register); | |
7461 %} | |
7462 ins_pipe(ialu_reg); | |
7463 %} | 7364 %} |
7464 | 7365 |
7465 //----------Multiplication/Division Instructions------------------------------- | 7366 //----------Multiplication/Division Instructions------------------------------- |
7466 // Integer Multiplication Instructions | 7367 // Integer Multiplication Instructions |
7467 // Multiply Register | 7368 // Multiply Register |
7670 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" | 7571 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" |
7671 "ADD EDX,$tmp" %} | 7572 "ADD EDX,$tmp" %} |
7672 ins_encode( long_multiply_con( dst, src, tmp ) ); | 7573 ins_encode( long_multiply_con( dst, src, tmp ) ); |
7673 ins_pipe( pipe_slow ); | 7574 ins_pipe( pipe_slow ); |
7674 %} | 7575 %} |
7675 | |
7676 instruct mulExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr) | |
7677 %{ | |
7678 match(MulExactI dst src); | |
7679 effect(DEF cr); | |
7680 | |
7681 ins_cost(300); | |
7682 format %{ "IMUL $dst, $src\t# mulExact int" %} | |
7683 ins_encode %{ | |
7684 __ imull($dst$$Register, $src$$Register); | |
7685 %} | |
7686 ins_pipe(ialu_reg_reg_alu0); | |
7687 %} | |
7688 | |
7689 instruct mulExactI_eReg_imm(eAXRegI dst, rRegI src, immI imm, eFlagsReg cr) | |
7690 %{ | |
7691 match(MulExactI src imm); | |
7692 effect(DEF cr); | |
7693 | |
7694 ins_cost(300); | |
7695 format %{ "IMUL $dst, $src, $imm\t# mulExact int" %} | |
7696 ins_encode %{ | |
7697 __ imull($dst$$Register, $src$$Register, $imm$$constant); | |
7698 %} | |
7699 ins_pipe(ialu_reg_reg_alu0); | |
7700 %} | |
7701 | |
7702 instruct mulExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr) | |
7703 %{ | |
7704 match(MulExactI dst (LoadI src)); | |
7705 effect(DEF cr); | |
7706 | |
7707 ins_cost(350); | |
7708 format %{ "IMUL $dst, $src\t# mulExact int" %} | |
7709 ins_encode %{ | |
7710 __ imull($dst$$Register, $src$$Address); | |
7711 %} | |
7712 ins_pipe(ialu_reg_mem_alu0); | |
7713 %} | |
7714 | |
7715 | 7576 |
7716 // Integer DIV with Register | 7577 // Integer DIV with Register |
7717 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | 7578 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ |
7718 match(Set rax (DivI rax div)); | 7579 match(Set rax (DivI rax div)); |
7719 effect(KILL rdx, KILL cr); | 7580 effect(KILL rdx, KILL cr); |
8576 | 8437 |
8577 /* If I enable this, I encourage spilling in the inner loop of compress. | 8438 /* If I enable this, I encourage spilling in the inner loop of compress. |
8578 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{ | 8439 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{ |
8579 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); | 8440 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); |
8580 */ | 8441 */ |
8442 //----------Overflow Math Instructions----------------------------------------- | |
8443 | |
8444 instruct overflowAddI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2) | |
8445 %{ | |
8446 match(Set cr (OverflowAddI op1 op2)); | |
8447 effect(DEF cr, USE_KILL op1, USE op2); | |
8448 | |
8449 format %{ "ADD $op1, $op2\t# overflow check int" %} | |
8450 | |
8451 ins_encode %{ | |
8452 __ addl($op1$$Register, $op2$$Register); | |
8453 %} | |
8454 ins_pipe(ialu_reg_reg); | |
8455 %} | |
8456 | |
8457 instruct overflowAddI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2) | |
8458 %{ | |
8459 match(Set cr (OverflowAddI op1 op2)); | |
8460 effect(DEF cr, USE_KILL op1, USE op2); | |
8461 | |
8462 format %{ "ADD $op1, $op2\t# overflow check int" %} | |
8463 | |
8464 ins_encode %{ | |
8465 __ addl($op1$$Register, $op2$$constant); | |
8466 %} | |
8467 ins_pipe(ialu_reg_reg); | |
8468 %} | |
8469 | |
8470 instruct overflowSubI_rReg(eFlagsReg cr, rRegI op1, rRegI op2) | |
8471 %{ | |
8472 match(Set cr (OverflowSubI op1 op2)); | |
8473 | |
8474 format %{ "CMP $op1, $op2\t# overflow check int" %} | |
8475 ins_encode %{ | |
8476 __ cmpl($op1$$Register, $op2$$Register); | |
8477 %} | |
8478 ins_pipe(ialu_reg_reg); | |
8479 %} | |
8480 | |
8481 instruct overflowSubI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2) | |
8482 %{ | |
8483 match(Set cr (OverflowSubI op1 op2)); | |
8484 | |
8485 format %{ "CMP $op1, $op2\t# overflow check int" %} | |
8486 ins_encode %{ | |
8487 __ cmpl($op1$$Register, $op2$$constant); | |
8488 %} | |
8489 ins_pipe(ialu_reg_reg); | |
8490 %} | |
8491 | |
8492 instruct overflowNegI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2) | |
8493 %{ | |
8494 match(Set cr (OverflowSubI zero op2)); | |
8495 effect(DEF cr, USE_KILL op2); | |
8496 | |
8497 format %{ "NEG $op2\t# overflow check int" %} | |
8498 ins_encode %{ | |
8499 __ negl($op2$$Register); | |
8500 %} | |
8501 ins_pipe(ialu_reg_reg); | |
8502 %} | |
8503 | |
8504 instruct overflowMulI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2) | |
8505 %{ | |
8506 match(Set cr (OverflowMulI op1 op2)); | |
8507 effect(DEF cr, USE_KILL op1, USE op2); | |
8508 | |
8509 format %{ "IMUL $op1, $op2\t# overflow check int" %} | |
8510 ins_encode %{ | |
8511 __ imull($op1$$Register, $op2$$Register); | |
8512 %} | |
8513 ins_pipe(ialu_reg_reg_alu0); | |
8514 %} | |
8515 | |
8516 instruct overflowMulI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2, rRegI tmp) | |
8517 %{ | |
8518 match(Set cr (OverflowMulI op1 op2)); | |
8519 effect(DEF cr, TEMP tmp, USE op1, USE op2); | |
8520 | |
8521 format %{ "IMUL $tmp, $op1, $op2\t# overflow check int" %} | |
8522 ins_encode %{ | |
8523 __ imull($tmp$$Register, $op1$$Register, $op2$$constant); | |
8524 %} | |
8525 ins_pipe(ialu_reg_reg_alu0); | |
8526 %} | |
8581 | 8527 |
8582 //----------Long Instructions------------------------------------------------ | 8528 //----------Long Instructions------------------------------------------------ |
8583 // Add Long Register with Register | 8529 // Add Long Register with Register |
8584 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | 8530 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ |
8585 match(Set dst (AddL dst src)); | 8531 match(Set dst (AddL dst src)); |