Mercurial > hg > truffle
comparison src/cpu/x86/vm/assembler_x86.cpp @ 20886:0e647427eee4
Merge with dc41766b35e11348281b76fd70b456b6ba3cf7e9
author | Michael Van De Vanter <michael.van.de.vanter@oracle.com> |
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date | Fri, 10 Apr 2015 16:58:26 -0700 |
parents | 7848fc12602b |
children |
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20885:e7ece52e1ff3 | 20886:0e647427eee4 |
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3866 emit_int8(0x58); | 3866 emit_int8(0x58); |
3867 emit_int8((unsigned char)(0xC0 | encode)); | 3867 emit_int8((unsigned char)(0xC0 | encode)); |
3868 } | 3868 } |
3869 | 3869 |
3870 // Carry-Less Multiplication Quadword | 3870 // Carry-Less Multiplication Quadword |
3871 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) { | |
3872 assert(VM_Version::supports_clmul(), ""); | |
3873 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); | |
3874 emit_int8(0x44); | |
3875 emit_int8((unsigned char)(0xC0 | encode)); | |
3876 emit_int8((unsigned char)mask); | |
3877 } | |
3878 | |
3879 // Carry-Less Multiplication Quadword | |
3871 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) { | 3880 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) { |
3872 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), ""); | 3881 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), ""); |
3873 bool vector256 = false; | 3882 bool vector256 = false; |
3874 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); | 3883 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); |
3875 emit_int8(0x44); | 3884 emit_int8(0x44); |
4940 void Assembler::addq(Register dst, Register src) { | 4949 void Assembler::addq(Register dst, Register src) { |
4941 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | 4950 (void) prefixq_and_encode(dst->encoding(), src->encoding()); |
4942 emit_arith(0x03, 0xC0, dst, src); | 4951 emit_arith(0x03, 0xC0, dst, src); |
4943 } | 4952 } |
4944 | 4953 |
4954 void Assembler::adcxq(Register dst, Register src) { | |
4955 //assert(VM_Version::supports_adx(), "adx instructions not supported"); | |
4956 emit_int8((unsigned char)0x66); | |
4957 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4958 emit_int8(0x0F); | |
4959 emit_int8(0x38); | |
4960 emit_int8((unsigned char)0xF6); | |
4961 emit_int8((unsigned char)(0xC0 | encode)); | |
4962 } | |
4963 | |
4964 void Assembler::adoxq(Register dst, Register src) { | |
4965 //assert(VM_Version::supports_adx(), "adx instructions not supported"); | |
4966 emit_int8((unsigned char)0xF3); | |
4967 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4968 emit_int8(0x0F); | |
4969 emit_int8(0x38); | |
4970 emit_int8((unsigned char)0xF6); | |
4971 emit_int8((unsigned char)(0xC0 | encode)); | |
4972 } | |
4973 | |
4945 void Assembler::andq(Address dst, int32_t imm32) { | 4974 void Assembler::andq(Address dst, int32_t imm32) { |
4946 InstructionMark im(this); | 4975 InstructionMark im(this); |
4947 prefixq(dst); | 4976 prefixq(dst); |
4948 emit_int8((unsigned char)0x81); | 4977 emit_int8((unsigned char)0x81); |
4949 emit_operand(rsp, dst, 4); | 4978 emit_operand(rsp, dst, 4); |
5444 | 5473 |
5445 void Assembler::movzwq(Register dst, Register src) { | 5474 void Assembler::movzwq(Register dst, Register src) { |
5446 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 5475 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
5447 emit_int8((unsigned char)0x0F); | 5476 emit_int8((unsigned char)0x0F); |
5448 emit_int8((unsigned char)0xB7); | 5477 emit_int8((unsigned char)0xB7); |
5478 emit_int8((unsigned char)(0xC0 | encode)); | |
5479 } | |
5480 | |
5481 void Assembler::mulq(Address src) { | |
5482 InstructionMark im(this); | |
5483 prefixq(src); | |
5484 emit_int8((unsigned char)0xF7); | |
5485 emit_operand(rsp, src); | |
5486 } | |
5487 | |
5488 void Assembler::mulq(Register src) { | |
5489 int encode = prefixq_and_encode(src->encoding()); | |
5490 emit_int8((unsigned char)0xF7); | |
5491 emit_int8((unsigned char)(0xE0 | encode)); | |
5492 } | |
5493 | |
5494 void Assembler::mulxq(Register dst1, Register dst2, Register src) { | |
5495 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); | |
5496 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, true, false); | |
5497 emit_int8((unsigned char)0xF6); | |
5449 emit_int8((unsigned char)(0xC0 | encode)); | 5498 emit_int8((unsigned char)(0xC0 | encode)); |
5450 } | 5499 } |
5451 | 5500 |
5452 void Assembler::negq(Register dst) { | 5501 void Assembler::negq(Register dst) { |
5453 int encode = prefixq_and_encode(dst->encoding()); | 5502 int encode = prefixq_and_encode(dst->encoding()); |
5575 emit_int8((unsigned char)0xC1); | 5624 emit_int8((unsigned char)0xC1); |
5576 emit_int8((unsigned char)(0xD0 | encode)); | 5625 emit_int8((unsigned char)(0xD0 | encode)); |
5577 emit_int8(imm8); | 5626 emit_int8(imm8); |
5578 } | 5627 } |
5579 } | 5628 } |
5629 | |
5630 void Assembler::rorq(Register dst, int imm8) { | |
5631 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5632 int encode = prefixq_and_encode(dst->encoding()); | |
5633 if (imm8 == 1) { | |
5634 emit_int8((unsigned char)0xD1); | |
5635 emit_int8((unsigned char)(0xC8 | encode)); | |
5636 } else { | |
5637 emit_int8((unsigned char)0xC1); | |
5638 emit_int8((unsigned char)(0xc8 | encode)); | |
5639 emit_int8(imm8); | |
5640 } | |
5641 } | |
5642 | |
5643 void Assembler::rorxq(Register dst, Register src, int imm8) { | |
5644 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); | |
5645 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, true, false); | |
5646 emit_int8((unsigned char)0xF0); | |
5647 emit_int8((unsigned char)(0xC0 | encode)); | |
5648 emit_int8(imm8); | |
5649 } | |
5650 | |
5580 void Assembler::sarq(Register dst, int imm8) { | 5651 void Assembler::sarq(Register dst, int imm8) { |
5581 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | 5652 assert(isShiftCount(imm8 >> 1), "illegal shift count"); |
5582 int encode = prefixq_and_encode(dst->encoding()); | 5653 int encode = prefixq_and_encode(dst->encoding()); |
5583 if (imm8 == 1) { | 5654 if (imm8 == 1) { |
5584 emit_int8((unsigned char)0xD1); | 5655 emit_int8((unsigned char)0xD1); |