Mercurial > hg > truffle
comparison src/cpu/x86/vm/x86_64.ad @ 4759:127b3692c168
7116452: Add support for AVX instructions
Summary: Added support for AVX extension to the x86 instruction set.
Reviewed-by: never
author | kvn |
---|---|
date | Wed, 14 Dec 2011 14:54:38 -0800 |
parents | db2e64ca2d5a |
children | 65149e74c706 |
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4758:d725f0affb1a | 4759:127b3692c168 |
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550 #define RELOC_DISP32 Assembler::disp32_operand | 550 #define RELOC_DISP32 Assembler::disp32_operand |
551 | 551 |
552 #define __ _masm. | 552 #define __ _masm. |
553 | 553 |
554 static int preserve_SP_size() { | 554 static int preserve_SP_size() { |
555 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg) | 555 return 3; // rex.w, op, rm(reg/reg) |
556 } | 556 } |
557 | 557 |
558 // !!!!! Special hack to get all types of calls to specify the byte offset | 558 // !!!!! Special hack to get all types of calls to specify the byte offset |
559 // from the start of the call to the point where the return address | 559 // from the start of the call to the point where the return address |
560 // will point. | 560 // will point. |
795 } | 795 } |
796 } | 796 } |
797 } | 797 } |
798 } | 798 } |
799 | 799 |
800 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc) | |
801 { | |
802 if (dstenc != srcenc) { | |
803 if (dstenc < 8) { | |
804 if (srcenc >= 8) { | |
805 emit_opcode(cbuf, Assembler::REX_B); | |
806 srcenc -= 8; | |
807 } | |
808 } else { | |
809 if (srcenc < 8) { | |
810 emit_opcode(cbuf, Assembler::REX_R); | |
811 } else { | |
812 emit_opcode(cbuf, Assembler::REX_RB); | |
813 srcenc -= 8; | |
814 } | |
815 dstenc -= 8; | |
816 } | |
817 | |
818 emit_opcode(cbuf, 0x8B); | |
819 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
820 } | |
821 } | |
822 | |
823 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
824 if( dst_encoding == src_encoding ) { | |
825 // reg-reg copy, use an empty encoding | |
826 } else { | |
827 MacroAssembler _masm(&cbuf); | |
828 | |
829 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding)); | |
830 } | |
831 } | |
832 | |
833 // This could be in MacroAssembler but it's fairly C2 specific | 800 // This could be in MacroAssembler but it's fairly C2 specific |
834 void emit_cmpfp_fixup(MacroAssembler& _masm) { | 801 void emit_cmpfp_fixup(MacroAssembler& _masm) { |
835 Label exit; | 802 Label exit; |
836 __ jccb(Assembler::noParity, exit); | 803 __ jccb(Assembler::noParity, exit); |
837 __ pushf(); | 804 __ pushf(); |
805 // | |
806 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
807 // zero OF,AF,SF for NaN values. | |
808 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
809 // values returns 'less than' result (CF is set). | |
810 // Leave the rest of flags unchanged. | |
811 // | |
812 // 7 6 5 4 3 2 1 0 | |
813 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
814 // 0 0 1 0 1 0 1 1 (0x2B) | |
815 // | |
838 __ andq(Address(rsp, 0), 0xffffff2b); | 816 __ andq(Address(rsp, 0), 0xffffff2b); |
839 __ popf(); | 817 __ popf(); |
840 __ bind(exit); | 818 __ bind(exit); |
841 __ nop(); // (target for branch to avoid branch to branch) | 819 } |
820 | |
821 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
822 Label done; | |
823 __ movl(dst, -1); | |
824 __ jcc(Assembler::parity, done); | |
825 __ jcc(Assembler::below, done); | |
826 __ setb(Assembler::notEqual, dst); | |
827 __ movzbl(dst, dst); | |
828 __ bind(done); | |
842 } | 829 } |
843 | 830 |
844 | 831 |
845 //============================================================================= | 832 //============================================================================= |
846 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; | 833 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
1272 if ((src_first & 1) == 0 && src_first + 1 == src_second && | 1259 if ((src_first & 1) == 0 && src_first + 1 == src_second && |
1273 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | 1260 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { |
1274 // 64-bit | 1261 // 64-bit |
1275 int offset = ra_->reg2offset(src_first); | 1262 int offset = ra_->reg2offset(src_first); |
1276 if (cbuf) { | 1263 if (cbuf) { |
1277 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | 1264 MacroAssembler _masm(cbuf); |
1278 if (Matcher::_regEncode[dst_first] >= 8) { | 1265 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
1279 emit_opcode(*cbuf, Assembler::REX_R); | |
1280 } | |
1281 emit_opcode(*cbuf, 0x0F); | |
1282 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
1283 encode_RegMem(*cbuf, | |
1284 Matcher::_regEncode[dst_first], | |
1285 RSP_enc, 0x4, 0, offset, | |
1286 false); | |
1287 #ifndef PRODUCT | 1266 #ifndef PRODUCT |
1288 } else if (!do_size) { | 1267 } else if (!do_size) { |
1289 st->print("%s %s, [rsp + #%d]\t# spill", | 1268 st->print("%s %s, [rsp + #%d]\t# spill", |
1290 UseXmmLoadAndClearUpper ? "movsd " : "movlpd", | 1269 UseXmmLoadAndClearUpper ? "movsd " : "movlpd", |
1291 Matcher::regName[dst_first], | 1270 Matcher::regName[dst_first], |
1292 offset); | 1271 offset); |
1293 #endif | 1272 #endif |
1294 } | 1273 } |
1295 return | 1274 return |
1296 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | 1275 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + |
1297 ((Matcher::_regEncode[dst_first] < 8) | 1276 ((Matcher::_regEncode[dst_first] >= 8) |
1298 ? 5 | 1277 ? 6 |
1299 : 6); // REX | 1278 : (5 + ((UseAVX>0)?1:0))); // REX |
1300 } else { | 1279 } else { |
1301 // 32-bit | 1280 // 32-bit |
1302 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | 1281 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); |
1303 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | 1282 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); |
1304 int offset = ra_->reg2offset(src_first); | 1283 int offset = ra_->reg2offset(src_first); |
1305 if (cbuf) { | 1284 if (cbuf) { |
1306 emit_opcode(*cbuf, 0xF3); | 1285 MacroAssembler _masm(cbuf); |
1307 if (Matcher::_regEncode[dst_first] >= 8) { | 1286 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
1308 emit_opcode(*cbuf, Assembler::REX_R); | |
1309 } | |
1310 emit_opcode(*cbuf, 0x0F); | |
1311 emit_opcode(*cbuf, 0x10); | |
1312 encode_RegMem(*cbuf, | |
1313 Matcher::_regEncode[dst_first], | |
1314 RSP_enc, 0x4, 0, offset, | |
1315 false); | |
1316 #ifndef PRODUCT | 1287 #ifndef PRODUCT |
1317 } else if (!do_size) { | 1288 } else if (!do_size) { |
1318 st->print("movss %s, [rsp + #%d]\t# spill", | 1289 st->print("movss %s, [rsp + #%d]\t# spill", |
1319 Matcher::regName[dst_first], | 1290 Matcher::regName[dst_first], |
1320 offset); | 1291 offset); |
1321 #endif | 1292 #endif |
1322 } | 1293 } |
1323 return | 1294 return |
1324 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | 1295 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + |
1325 ((Matcher::_regEncode[dst_first] < 8) | 1296 ((Matcher::_regEncode[dst_first] >= 8) |
1326 ? 5 | 1297 ? 6 |
1327 : 6); // REX | 1298 : (5 + ((UseAVX>0)?1:0))); // REX |
1328 } | 1299 } |
1329 } | 1300 } |
1330 } else if (src_first_rc == rc_int) { | 1301 } else if (src_first_rc == rc_int) { |
1331 // gpr -> | 1302 // gpr -> |
1332 if (dst_first_rc == rc_stack) { | 1303 if (dst_first_rc == rc_stack) { |
1448 // gpr -> xmm | 1419 // gpr -> xmm |
1449 if ((src_first & 1) == 0 && src_first + 1 == src_second && | 1420 if ((src_first & 1) == 0 && src_first + 1 == src_second && |
1450 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | 1421 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { |
1451 // 64-bit | 1422 // 64-bit |
1452 if (cbuf) { | 1423 if (cbuf) { |
1453 emit_opcode(*cbuf, 0x66); | 1424 MacroAssembler _masm(cbuf); |
1454 if (Matcher::_regEncode[dst_first] < 8) { | 1425 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); |
1455 if (Matcher::_regEncode[src_first] < 8) { | |
1456 emit_opcode(*cbuf, Assembler::REX_W); | |
1457 } else { | |
1458 emit_opcode(*cbuf, Assembler::REX_WB); | |
1459 } | |
1460 } else { | |
1461 if (Matcher::_regEncode[src_first] < 8) { | |
1462 emit_opcode(*cbuf, Assembler::REX_WR); | |
1463 } else { | |
1464 emit_opcode(*cbuf, Assembler::REX_WRB); | |
1465 } | |
1466 } | |
1467 emit_opcode(*cbuf, 0x0F); | |
1468 emit_opcode(*cbuf, 0x6E); | |
1469 emit_rm(*cbuf, 0x3, | |
1470 Matcher::_regEncode[dst_first] & 7, | |
1471 Matcher::_regEncode[src_first] & 7); | |
1472 #ifndef PRODUCT | 1426 #ifndef PRODUCT |
1473 } else if (!do_size) { | 1427 } else if (!do_size) { |
1474 st->print("movdq %s, %s\t# spill", | 1428 st->print("movdq %s, %s\t# spill", |
1475 Matcher::regName[dst_first], | 1429 Matcher::regName[dst_first], |
1476 Matcher::regName[src_first]); | 1430 Matcher::regName[src_first]); |
1480 } else { | 1434 } else { |
1481 // 32-bit | 1435 // 32-bit |
1482 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | 1436 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); |
1483 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | 1437 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); |
1484 if (cbuf) { | 1438 if (cbuf) { |
1485 emit_opcode(*cbuf, 0x66); | 1439 MacroAssembler _masm(cbuf); |
1486 if (Matcher::_regEncode[dst_first] < 8) { | 1440 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); |
1487 if (Matcher::_regEncode[src_first] >= 8) { | |
1488 emit_opcode(*cbuf, Assembler::REX_B); | |
1489 } | |
1490 } else { | |
1491 if (Matcher::_regEncode[src_first] < 8) { | |
1492 emit_opcode(*cbuf, Assembler::REX_R); | |
1493 } else { | |
1494 emit_opcode(*cbuf, Assembler::REX_RB); | |
1495 } | |
1496 } | |
1497 emit_opcode(*cbuf, 0x0F); | |
1498 emit_opcode(*cbuf, 0x6E); | |
1499 emit_rm(*cbuf, 0x3, | |
1500 Matcher::_regEncode[dst_first] & 7, | |
1501 Matcher::_regEncode[src_first] & 7); | |
1502 #ifndef PRODUCT | 1441 #ifndef PRODUCT |
1503 } else if (!do_size) { | 1442 } else if (!do_size) { |
1504 st->print("movdl %s, %s\t# spill", | 1443 st->print("movdl %s, %s\t# spill", |
1505 Matcher::regName[dst_first], | 1444 Matcher::regName[dst_first], |
1506 Matcher::regName[src_first]); | 1445 Matcher::regName[src_first]); |
1507 #endif | 1446 #endif |
1508 } | 1447 } |
1509 return | 1448 return |
1510 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | 1449 (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8) |
1511 ? 4 | 1450 ? 5 |
1512 : 5; // REX | 1451 : (4 + ((UseAVX>0)?1:0)); // REX |
1513 } | 1452 } |
1514 } | 1453 } |
1515 } else if (src_first_rc == rc_float) { | 1454 } else if (src_first_rc == rc_float) { |
1516 // xmm -> | 1455 // xmm -> |
1517 if (dst_first_rc == rc_stack) { | 1456 if (dst_first_rc == rc_stack) { |
1519 if ((src_first & 1) == 0 && src_first + 1 == src_second && | 1458 if ((src_first & 1) == 0 && src_first + 1 == src_second && |
1520 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | 1459 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { |
1521 // 64-bit | 1460 // 64-bit |
1522 int offset = ra_->reg2offset(dst_first); | 1461 int offset = ra_->reg2offset(dst_first); |
1523 if (cbuf) { | 1462 if (cbuf) { |
1524 emit_opcode(*cbuf, 0xF2); | 1463 MacroAssembler _masm(cbuf); |
1525 if (Matcher::_regEncode[src_first] >= 8) { | 1464 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); |
1526 emit_opcode(*cbuf, Assembler::REX_R); | |
1527 } | |
1528 emit_opcode(*cbuf, 0x0F); | |
1529 emit_opcode(*cbuf, 0x11); | |
1530 encode_RegMem(*cbuf, | |
1531 Matcher::_regEncode[src_first], | |
1532 RSP_enc, 0x4, 0, offset, | |
1533 false); | |
1534 #ifndef PRODUCT | 1465 #ifndef PRODUCT |
1535 } else if (!do_size) { | 1466 } else if (!do_size) { |
1536 st->print("movsd [rsp + #%d], %s\t# spill", | 1467 st->print("movsd [rsp + #%d], %s\t# spill", |
1537 offset, | 1468 offset, |
1538 Matcher::regName[src_first]); | 1469 Matcher::regName[src_first]); |
1539 #endif | 1470 #endif |
1540 } | 1471 } |
1541 return | 1472 return |
1542 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | 1473 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + |
1543 ((Matcher::_regEncode[src_first] < 8) | 1474 ((Matcher::_regEncode[src_first] >= 8) |
1544 ? 5 | 1475 ? 6 |
1545 : 6); // REX | 1476 : (5 + ((UseAVX>0)?1:0))); // REX |
1546 } else { | 1477 } else { |
1547 // 32-bit | 1478 // 32-bit |
1548 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | 1479 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); |
1549 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | 1480 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); |
1550 int offset = ra_->reg2offset(dst_first); | 1481 int offset = ra_->reg2offset(dst_first); |
1551 if (cbuf) { | 1482 if (cbuf) { |
1552 emit_opcode(*cbuf, 0xF3); | 1483 MacroAssembler _masm(cbuf); |
1553 if (Matcher::_regEncode[src_first] >= 8) { | 1484 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); |
1554 emit_opcode(*cbuf, Assembler::REX_R); | |
1555 } | |
1556 emit_opcode(*cbuf, 0x0F); | |
1557 emit_opcode(*cbuf, 0x11); | |
1558 encode_RegMem(*cbuf, | |
1559 Matcher::_regEncode[src_first], | |
1560 RSP_enc, 0x4, 0, offset, | |
1561 false); | |
1562 #ifndef PRODUCT | 1485 #ifndef PRODUCT |
1563 } else if (!do_size) { | 1486 } else if (!do_size) { |
1564 st->print("movss [rsp + #%d], %s\t# spill", | 1487 st->print("movss [rsp + #%d], %s\t# spill", |
1565 offset, | 1488 offset, |
1566 Matcher::regName[src_first]); | 1489 Matcher::regName[src_first]); |
1567 #endif | 1490 #endif |
1568 } | 1491 } |
1569 return | 1492 return |
1570 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | 1493 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + |
1571 ((Matcher::_regEncode[src_first] < 8) | 1494 ((Matcher::_regEncode[src_first] >=8) |
1572 ? 5 | 1495 ? 6 |
1573 : 6); // REX | 1496 : (5 + ((UseAVX>0)?1:0))); // REX |
1574 } | 1497 } |
1575 } else if (dst_first_rc == rc_int) { | 1498 } else if (dst_first_rc == rc_int) { |
1576 // xmm -> gpr | 1499 // xmm -> gpr |
1577 if ((src_first & 1) == 0 && src_first + 1 == src_second && | 1500 if ((src_first & 1) == 0 && src_first + 1 == src_second && |
1578 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | 1501 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { |
1579 // 64-bit | 1502 // 64-bit |
1580 if (cbuf) { | 1503 if (cbuf) { |
1581 emit_opcode(*cbuf, 0x66); | 1504 MacroAssembler _masm(cbuf); |
1582 if (Matcher::_regEncode[dst_first] < 8) { | 1505 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); |
1583 if (Matcher::_regEncode[src_first] < 8) { | |
1584 emit_opcode(*cbuf, Assembler::REX_W); | |
1585 } else { | |
1586 emit_opcode(*cbuf, Assembler::REX_WR); // attention! | |
1587 } | |
1588 } else { | |
1589 if (Matcher::_regEncode[src_first] < 8) { | |
1590 emit_opcode(*cbuf, Assembler::REX_WB); // attention! | |
1591 } else { | |
1592 emit_opcode(*cbuf, Assembler::REX_WRB); | |
1593 } | |
1594 } | |
1595 emit_opcode(*cbuf, 0x0F); | |
1596 emit_opcode(*cbuf, 0x7E); | |
1597 emit_rm(*cbuf, 0x3, | |
1598 Matcher::_regEncode[src_first] & 7, | |
1599 Matcher::_regEncode[dst_first] & 7); | |
1600 #ifndef PRODUCT | 1506 #ifndef PRODUCT |
1601 } else if (!do_size) { | 1507 } else if (!do_size) { |
1602 st->print("movdq %s, %s\t# spill", | 1508 st->print("movdq %s, %s\t# spill", |
1603 Matcher::regName[dst_first], | 1509 Matcher::regName[dst_first], |
1604 Matcher::regName[src_first]); | 1510 Matcher::regName[src_first]); |
1608 } else { | 1514 } else { |
1609 // 32-bit | 1515 // 32-bit |
1610 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | 1516 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); |
1611 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | 1517 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); |
1612 if (cbuf) { | 1518 if (cbuf) { |
1613 emit_opcode(*cbuf, 0x66); | 1519 MacroAssembler _masm(cbuf); |
1614 if (Matcher::_regEncode[dst_first] < 8) { | 1520 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); |
1615 if (Matcher::_regEncode[src_first] >= 8) { | |
1616 emit_opcode(*cbuf, Assembler::REX_R); // attention! | |
1617 } | |
1618 } else { | |
1619 if (Matcher::_regEncode[src_first] < 8) { | |
1620 emit_opcode(*cbuf, Assembler::REX_B); // attention! | |
1621 } else { | |
1622 emit_opcode(*cbuf, Assembler::REX_RB); | |
1623 } | |
1624 } | |
1625 emit_opcode(*cbuf, 0x0F); | |
1626 emit_opcode(*cbuf, 0x7E); | |
1627 emit_rm(*cbuf, 0x3, | |
1628 Matcher::_regEncode[src_first] & 7, | |
1629 Matcher::_regEncode[dst_first] & 7); | |
1630 #ifndef PRODUCT | 1521 #ifndef PRODUCT |
1631 } else if (!do_size) { | 1522 } else if (!do_size) { |
1632 st->print("movdl %s, %s\t# spill", | 1523 st->print("movdl %s, %s\t# spill", |
1633 Matcher::regName[dst_first], | 1524 Matcher::regName[dst_first], |
1634 Matcher::regName[src_first]); | 1525 Matcher::regName[src_first]); |
1635 #endif | 1526 #endif |
1636 } | 1527 } |
1637 return | 1528 return |
1638 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | 1529 (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8) |
1639 ? 4 | 1530 ? 5 |
1640 : 5; // REX | 1531 : (4 + ((UseAVX>0)?1:0)); // REX |
1641 } | 1532 } |
1642 } else if (dst_first_rc == rc_float) { | 1533 } else if (dst_first_rc == rc_float) { |
1643 // xmm -> xmm | 1534 // xmm -> xmm |
1644 if ((src_first & 1) == 0 && src_first + 1 == src_second && | 1535 if ((src_first & 1) == 0 && src_first + 1 == src_second && |
1645 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | 1536 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { |
1646 // 64-bit | 1537 // 64-bit |
1647 if (cbuf) { | 1538 if (cbuf) { |
1648 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2); | 1539 MacroAssembler _masm(cbuf); |
1649 if (Matcher::_regEncode[dst_first] < 8) { | 1540 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); |
1650 if (Matcher::_regEncode[src_first] >= 8) { | |
1651 emit_opcode(*cbuf, Assembler::REX_B); | |
1652 } | |
1653 } else { | |
1654 if (Matcher::_regEncode[src_first] < 8) { | |
1655 emit_opcode(*cbuf, Assembler::REX_R); | |
1656 } else { | |
1657 emit_opcode(*cbuf, Assembler::REX_RB); | |
1658 } | |
1659 } | |
1660 emit_opcode(*cbuf, 0x0F); | |
1661 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
1662 emit_rm(*cbuf, 0x3, | |
1663 Matcher::_regEncode[dst_first] & 7, | |
1664 Matcher::_regEncode[src_first] & 7); | |
1665 #ifndef PRODUCT | 1541 #ifndef PRODUCT |
1666 } else if (!do_size) { | 1542 } else if (!do_size) { |
1667 st->print("%s %s, %s\t# spill", | 1543 st->print("%s %s, %s\t# spill", |
1668 UseXmmRegToRegMoveAll ? "movapd" : "movsd ", | 1544 UseXmmRegToRegMoveAll ? "movapd" : "movsd ", |
1669 Matcher::regName[dst_first], | 1545 Matcher::regName[dst_first], |
1670 Matcher::regName[src_first]); | 1546 Matcher::regName[src_first]); |
1671 #endif | 1547 #endif |
1672 } | 1548 } |
1673 return | 1549 return |
1674 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | 1550 (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8) |
1675 ? 4 | 1551 ? 5 |
1676 : 5; // REX | 1552 : (4 + ((UseAVX>0)?1:0)); // REX |
1677 } else { | 1553 } else { |
1678 // 32-bit | 1554 // 32-bit |
1679 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | 1555 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); |
1680 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | 1556 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); |
1681 if (cbuf) { | 1557 if (cbuf) { |
1682 if (!UseXmmRegToRegMoveAll) | 1558 MacroAssembler _masm(cbuf); |
1683 emit_opcode(*cbuf, 0xF3); | 1559 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); |
1684 if (Matcher::_regEncode[dst_first] < 8) { | |
1685 if (Matcher::_regEncode[src_first] >= 8) { | |
1686 emit_opcode(*cbuf, Assembler::REX_B); | |
1687 } | |
1688 } else { | |
1689 if (Matcher::_regEncode[src_first] < 8) { | |
1690 emit_opcode(*cbuf, Assembler::REX_R); | |
1691 } else { | |
1692 emit_opcode(*cbuf, Assembler::REX_RB); | |
1693 } | |
1694 } | |
1695 emit_opcode(*cbuf, 0x0F); | |
1696 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
1697 emit_rm(*cbuf, 0x3, | |
1698 Matcher::_regEncode[dst_first] & 7, | |
1699 Matcher::_regEncode[src_first] & 7); | |
1700 #ifndef PRODUCT | 1560 #ifndef PRODUCT |
1701 } else if (!do_size) { | 1561 } else if (!do_size) { |
1702 st->print("%s %s, %s\t# spill", | 1562 st->print("%s %s, %s\t# spill", |
1703 UseXmmRegToRegMoveAll ? "movaps" : "movss ", | 1563 UseXmmRegToRegMoveAll ? "movaps" : "movss ", |
1704 Matcher::regName[dst_first], | 1564 Matcher::regName[dst_first], |
1705 Matcher::regName[src_first]); | 1565 Matcher::regName[src_first]); |
1706 #endif | 1566 #endif |
1707 } | 1567 } |
1708 return | 1568 return ((UseAVX>0) ? 5: |
1709 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | 1569 ((Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8) |
1710 ? (UseXmmRegToRegMoveAll ? 3 : 4) | 1570 ? (UseXmmRegToRegMoveAll ? 4 : 5) |
1711 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX | 1571 : (UseXmmRegToRegMoveAll ? 3 : 4))); // REX |
1712 } | 1572 } |
1713 } | 1573 } |
1714 } | 1574 } |
1715 | 1575 |
1716 assert(0," foo "); | 1576 assert(0," foo "); |
2203 %{ | 2063 %{ |
2204 emit_opcode(cbuf, $opcode$$constant); | 2064 emit_opcode(cbuf, $opcode$$constant); |
2205 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | 2065 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); |
2206 %} | 2066 %} |
2207 | 2067 |
2208 enc_class cmpfp_fixup() %{ | |
2209 MacroAssembler _masm(&cbuf); | |
2210 emit_cmpfp_fixup(_masm); | |
2211 %} | |
2212 | |
2213 enc_class cmpfp3(rRegI dst) | |
2214 %{ | |
2215 int dstenc = $dst$$reg; | |
2216 | |
2217 // movl $dst, -1 | |
2218 if (dstenc >= 8) { | |
2219 emit_opcode(cbuf, Assembler::REX_B); | |
2220 } | |
2221 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
2222 emit_d32(cbuf, -1); | |
2223 | |
2224 // jp,s done | |
2225 emit_opcode(cbuf, 0x7A); | |
2226 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A); | |
2227 | |
2228 // jb,s done | |
2229 emit_opcode(cbuf, 0x72); | |
2230 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
2231 | |
2232 // setne $dst | |
2233 if (dstenc >= 4) { | |
2234 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
2235 } | |
2236 emit_opcode(cbuf, 0x0F); | |
2237 emit_opcode(cbuf, 0x95); | |
2238 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
2239 | |
2240 // movzbl $dst, $dst | |
2241 if (dstenc >= 4) { | |
2242 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
2243 } | |
2244 emit_opcode(cbuf, 0x0F); | |
2245 emit_opcode(cbuf, 0xB6); | |
2246 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
2247 %} | |
2248 | |
2249 enc_class cdql_enc(no_rax_rdx_RegI div) | 2068 enc_class cdql_enc(no_rax_rdx_RegI div) |
2250 %{ | 2069 %{ |
2251 // Full implementation of Java idiv and irem; checks for | 2070 // Full implementation of Java idiv and irem; checks for |
2252 // special case as described in JVM spec., p.243 & p.271. | 2071 // special case as described in JVM spec., p.243 & p.271. |
2253 // | 2072 // |
2470 // CMOV | 2289 // CMOV |
2471 $$$emit8$primary; | 2290 $$$emit8$primary; |
2472 emit_cc(cbuf, $secondary, $cop$$cmpcode); | 2291 emit_cc(cbuf, $secondary, $cop$$cmpcode); |
2473 %} | 2292 %} |
2474 | 2293 |
2475 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src) | |
2476 %{ | |
2477 // Invert sense of branch from sense of cmov | |
2478 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1); | |
2479 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8) | |
2480 ? (UseXmmRegToRegMoveAll ? 3 : 4) | |
2481 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX | |
2482 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src) | |
2483 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3); | |
2484 if ($dst$$reg < 8) { | |
2485 if ($src$$reg >= 8) { | |
2486 emit_opcode(cbuf, Assembler::REX_B); | |
2487 } | |
2488 } else { | |
2489 if ($src$$reg < 8) { | |
2490 emit_opcode(cbuf, Assembler::REX_R); | |
2491 } else { | |
2492 emit_opcode(cbuf, Assembler::REX_RB); | |
2493 } | |
2494 } | |
2495 emit_opcode(cbuf, 0x0F); | |
2496 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
2497 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
2498 %} | |
2499 | |
2500 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src) | |
2501 %{ | |
2502 // Invert sense of branch from sense of cmov | |
2503 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1); | |
2504 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX | |
2505 | |
2506 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src) | |
2507 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2); | |
2508 if ($dst$$reg < 8) { | |
2509 if ($src$$reg >= 8) { | |
2510 emit_opcode(cbuf, Assembler::REX_B); | |
2511 } | |
2512 } else { | |
2513 if ($src$$reg < 8) { | |
2514 emit_opcode(cbuf, Assembler::REX_R); | |
2515 } else { | |
2516 emit_opcode(cbuf, Assembler::REX_RB); | |
2517 } | |
2518 } | |
2519 emit_opcode(cbuf, 0x0F); | |
2520 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
2521 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
2522 %} | |
2523 | |
2524 enc_class enc_PartialSubtypeCheck() | 2294 enc_class enc_PartialSubtypeCheck() |
2525 %{ | 2295 %{ |
2526 Register Rrdi = as_Register(RDI_enc); // result register | 2296 Register Rrdi = as_Register(RDI_enc); // result register |
2527 Register Rrax = as_Register(RAX_enc); // super class | 2297 Register Rrax = as_Register(RAX_enc); // super class |
2528 Register Rrcx = as_Register(RCX_enc); // killed | 2298 Register Rrcx = as_Register(RCX_enc); // killed |
2746 // This next line should be generated from ADLC | 2516 // This next line should be generated from ADLC |
2747 if ($src->constant_is_oop()) { | 2517 if ($src->constant_is_oop()) { |
2748 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64); | 2518 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64); |
2749 } else { | 2519 } else { |
2750 emit_d64(cbuf, $src$$constant); | 2520 emit_d64(cbuf, $src$$constant); |
2751 } | |
2752 %} | |
2753 | |
2754 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2755 enc_class enc_copy(rRegI dst, rRegI src) | |
2756 %{ | |
2757 encode_copy(cbuf, $dst$$reg, $src$$reg); | |
2758 %} | |
2759 | |
2760 // Encode xmm reg-reg copy. If it is useless, then empty encoding. | |
2761 enc_class enc_CopyXD( RegD dst, RegD src ) %{ | |
2762 encode_CopyXD( cbuf, $dst$$reg, $src$$reg ); | |
2763 %} | |
2764 | |
2765 enc_class enc_copy_always(rRegI dst, rRegI src) | |
2766 %{ | |
2767 int srcenc = $src$$reg; | |
2768 int dstenc = $dst$$reg; | |
2769 | |
2770 if (dstenc < 8) { | |
2771 if (srcenc >= 8) { | |
2772 emit_opcode(cbuf, Assembler::REX_B); | |
2773 srcenc -= 8; | |
2774 } | |
2775 } else { | |
2776 if (srcenc < 8) { | |
2777 emit_opcode(cbuf, Assembler::REX_R); | |
2778 } else { | |
2779 emit_opcode(cbuf, Assembler::REX_RB); | |
2780 srcenc -= 8; | |
2781 } | |
2782 dstenc -= 8; | |
2783 } | |
2784 | |
2785 emit_opcode(cbuf, 0x8B); | |
2786 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
2787 %} | |
2788 | |
2789 enc_class enc_copy_wide(rRegL dst, rRegL src) | |
2790 %{ | |
2791 int srcenc = $src$$reg; | |
2792 int dstenc = $dst$$reg; | |
2793 | |
2794 if (dstenc != srcenc) { | |
2795 if (dstenc < 8) { | |
2796 if (srcenc < 8) { | |
2797 emit_opcode(cbuf, Assembler::REX_W); | |
2798 } else { | |
2799 emit_opcode(cbuf, Assembler::REX_WB); | |
2800 srcenc -= 8; | |
2801 } | |
2802 } else { | |
2803 if (srcenc < 8) { | |
2804 emit_opcode(cbuf, Assembler::REX_WR); | |
2805 } else { | |
2806 emit_opcode(cbuf, Assembler::REX_WRB); | |
2807 srcenc -= 8; | |
2808 } | |
2809 dstenc -= 8; | |
2810 } | |
2811 emit_opcode(cbuf, 0x8B); | |
2812 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
2813 } | 2521 } |
2814 %} | 2522 %} |
2815 | 2523 |
2816 enc_class Con32(immI src) | 2524 enc_class Con32(immI src) |
2817 %{ | 2525 %{ |
3210 emit_opcode(cbuf, 0xB6); | 2918 emit_opcode(cbuf, 0xB6); |
3211 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | 2919 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); |
3212 %} | 2920 %} |
3213 | 2921 |
3214 enc_class Push_ResultXD(regD dst) %{ | 2922 enc_class Push_ResultXD(regD dst) %{ |
3215 int dstenc = $dst$$reg; | 2923 MacroAssembler _masm(&cbuf); |
3216 | 2924 __ fstp_d(Address(rsp, 0)); |
3217 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP] | 2925 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
3218 | 2926 __ addptr(rsp, 8); |
3219 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp] | |
3220 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
3221 if (dstenc >= 8) { | |
3222 emit_opcode(cbuf, Assembler::REX_R); | |
3223 } | |
3224 emit_opcode (cbuf, 0x0F ); | |
3225 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 ); | |
3226 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false); | |
3227 | |
3228 // add rsp,8 | |
3229 emit_opcode(cbuf, Assembler::REX_W); | |
3230 emit_opcode(cbuf,0x83); | |
3231 emit_rm(cbuf,0x3, 0x0, RSP_enc); | |
3232 emit_d8(cbuf,0x08); | |
3233 %} | 2927 %} |
3234 | 2928 |
3235 enc_class Push_SrcXD(regD src) %{ | 2929 enc_class Push_SrcXD(regD src) %{ |
3236 int srcenc = $src$$reg; | |
3237 | |
3238 // subq rsp,#8 | |
3239 emit_opcode(cbuf, Assembler::REX_W); | |
3240 emit_opcode(cbuf, 0x83); | |
3241 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
3242 emit_d8(cbuf, 0x8); | |
3243 | |
3244 // movsd [rsp],src | |
3245 emit_opcode(cbuf, 0xF2); | |
3246 if (srcenc >= 8) { | |
3247 emit_opcode(cbuf, Assembler::REX_R); | |
3248 } | |
3249 emit_opcode(cbuf, 0x0F); | |
3250 emit_opcode(cbuf, 0x11); | |
3251 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); | |
3252 | |
3253 // fldd [rsp] | |
3254 emit_opcode(cbuf, 0x66); | |
3255 emit_opcode(cbuf, 0xDD); | |
3256 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false); | |
3257 %} | |
3258 | |
3259 | |
3260 enc_class movq_ld(regD dst, memory mem) %{ | |
3261 MacroAssembler _masm(&cbuf); | 2930 MacroAssembler _masm(&cbuf); |
3262 __ movq($dst$$XMMRegister, $mem$$Address); | 2931 __ subptr(rsp, 8); |
3263 %} | 2932 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
3264 | 2933 __ fld_d(Address(rsp, 0)); |
3265 enc_class movq_st(memory mem, regD src) %{ | 2934 %} |
3266 MacroAssembler _masm(&cbuf); | 2935 |
3267 __ movq($mem$$Address, $src$$XMMRegister); | |
3268 %} | |
3269 | |
3270 enc_class pshufd_8x8(regF dst, regF src) %{ | |
3271 MacroAssembler _masm(&cbuf); | |
3272 | |
3273 encode_CopyXD(cbuf, $dst$$reg, $src$$reg); | |
3274 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg)); | |
3275 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00); | |
3276 %} | |
3277 | |
3278 enc_class pshufd_4x16(regF dst, regF src) %{ | |
3279 MacroAssembler _masm(&cbuf); | |
3280 | |
3281 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00); | |
3282 %} | |
3283 | |
3284 enc_class pshufd(regD dst, regD src, int mode) %{ | |
3285 MacroAssembler _masm(&cbuf); | |
3286 | |
3287 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode); | |
3288 %} | |
3289 | |
3290 enc_class pxor(regD dst, regD src) %{ | |
3291 MacroAssembler _masm(&cbuf); | |
3292 | |
3293 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg)); | |
3294 %} | |
3295 | |
3296 enc_class mov_i2x(regD dst, rRegI src) %{ | |
3297 MacroAssembler _masm(&cbuf); | |
3298 | |
3299 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg)); | |
3300 %} | |
3301 | 2936 |
3302 // obj: object to lock | 2937 // obj: object to lock |
3303 // box: box address (header location) -- killed | 2938 // box: box address (header location) -- killed |
3304 // tmp: rax -- killed | 2939 // tmp: rax -- killed |
3305 // scr: rbx -- killed | 2940 // scr: rbx -- killed |
3532 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4), | 3167 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4), |
3533 runtime_call_Relocation::spec(), | 3168 runtime_call_Relocation::spec(), |
3534 RELOC_DISP32); | 3169 RELOC_DISP32); |
3535 %} | 3170 %} |
3536 | 3171 |
3537 enc_class absF_encoding(regF dst) | |
3538 %{ | |
3539 int dstenc = $dst$$reg; | |
3540 address signmask_address = (address) StubRoutines::x86::float_sign_mask(); | |
3541 | |
3542 cbuf.set_insts_mark(); | |
3543 if (dstenc >= 8) { | |
3544 emit_opcode(cbuf, Assembler::REX_R); | |
3545 dstenc -= 8; | |
3546 } | |
3547 // XXX reg_mem doesn't support RIP-relative addressing yet | |
3548 emit_opcode(cbuf, 0x0F); | |
3549 emit_opcode(cbuf, 0x54); | |
3550 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
3551 emit_d32_reloc(cbuf, signmask_address); | |
3552 %} | |
3553 | |
3554 enc_class absD_encoding(regD dst) | |
3555 %{ | |
3556 int dstenc = $dst$$reg; | |
3557 address signmask_address = (address) StubRoutines::x86::double_sign_mask(); | |
3558 | |
3559 cbuf.set_insts_mark(); | |
3560 emit_opcode(cbuf, 0x66); | |
3561 if (dstenc >= 8) { | |
3562 emit_opcode(cbuf, Assembler::REX_R); | |
3563 dstenc -= 8; | |
3564 } | |
3565 // XXX reg_mem doesn't support RIP-relative addressing yet | |
3566 emit_opcode(cbuf, 0x0F); | |
3567 emit_opcode(cbuf, 0x54); | |
3568 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
3569 emit_d32_reloc(cbuf, signmask_address); | |
3570 %} | |
3571 | |
3572 enc_class negF_encoding(regF dst) | |
3573 %{ | |
3574 int dstenc = $dst$$reg; | |
3575 address signflip_address = (address) StubRoutines::x86::float_sign_flip(); | |
3576 | |
3577 cbuf.set_insts_mark(); | |
3578 if (dstenc >= 8) { | |
3579 emit_opcode(cbuf, Assembler::REX_R); | |
3580 dstenc -= 8; | |
3581 } | |
3582 // XXX reg_mem doesn't support RIP-relative addressing yet | |
3583 emit_opcode(cbuf, 0x0F); | |
3584 emit_opcode(cbuf, 0x57); | |
3585 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
3586 emit_d32_reloc(cbuf, signflip_address); | |
3587 %} | |
3588 | |
3589 enc_class negD_encoding(regD dst) | |
3590 %{ | |
3591 int dstenc = $dst$$reg; | |
3592 address signflip_address = (address) StubRoutines::x86::double_sign_flip(); | |
3593 | |
3594 cbuf.set_insts_mark(); | |
3595 emit_opcode(cbuf, 0x66); | |
3596 if (dstenc >= 8) { | |
3597 emit_opcode(cbuf, Assembler::REX_R); | |
3598 dstenc -= 8; | |
3599 } | |
3600 // XXX reg_mem doesn't support RIP-relative addressing yet | |
3601 emit_opcode(cbuf, 0x0F); | |
3602 emit_opcode(cbuf, 0x57); | |
3603 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
3604 emit_d32_reloc(cbuf, signflip_address); | |
3605 %} | |
3606 | |
3607 enc_class f2i_fixup(rRegI dst, regF src) | |
3608 %{ | |
3609 int dstenc = $dst$$reg; | |
3610 int srcenc = $src$$reg; | |
3611 | |
3612 // cmpl $dst, #0x80000000 | |
3613 if (dstenc >= 8) { | |
3614 emit_opcode(cbuf, Assembler::REX_B); | |
3615 } | |
3616 emit_opcode(cbuf, 0x81); | |
3617 emit_rm(cbuf, 0x3, 0x7, dstenc & 7); | |
3618 emit_d32(cbuf, 0x80000000); | |
3619 | |
3620 // jne,s done | |
3621 emit_opcode(cbuf, 0x75); | |
3622 if (srcenc < 8 && dstenc < 8) { | |
3623 emit_d8(cbuf, 0xF); | |
3624 } else if (srcenc >= 8 && dstenc >= 8) { | |
3625 emit_d8(cbuf, 0x11); | |
3626 } else { | |
3627 emit_d8(cbuf, 0x10); | |
3628 } | |
3629 | |
3630 // subq rsp, #8 | |
3631 emit_opcode(cbuf, Assembler::REX_W); | |
3632 emit_opcode(cbuf, 0x83); | |
3633 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
3634 emit_d8(cbuf, 8); | |
3635 | |
3636 // movss [rsp], $src | |
3637 emit_opcode(cbuf, 0xF3); | |
3638 if (srcenc >= 8) { | |
3639 emit_opcode(cbuf, Assembler::REX_R); | |
3640 } | |
3641 emit_opcode(cbuf, 0x0F); | |
3642 emit_opcode(cbuf, 0x11); | |
3643 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
3644 | |
3645 // call f2i_fixup | |
3646 cbuf.set_insts_mark(); | |
3647 emit_opcode(cbuf, 0xE8); | |
3648 emit_d32_reloc(cbuf, | |
3649 (int) | |
3650 (StubRoutines::x86::f2i_fixup() - cbuf.insts_end() - 4), | |
3651 runtime_call_Relocation::spec(), | |
3652 RELOC_DISP32); | |
3653 | |
3654 // popq $dst | |
3655 if (dstenc >= 8) { | |
3656 emit_opcode(cbuf, Assembler::REX_B); | |
3657 } | |
3658 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
3659 | |
3660 // done: | |
3661 %} | |
3662 | |
3663 enc_class f2l_fixup(rRegL dst, regF src) | |
3664 %{ | |
3665 int dstenc = $dst$$reg; | |
3666 int srcenc = $src$$reg; | |
3667 address const_address = (address) StubRoutines::x86::double_sign_flip(); | |
3668 | |
3669 // cmpq $dst, [0x8000000000000000] | |
3670 cbuf.set_insts_mark(); | |
3671 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
3672 emit_opcode(cbuf, 0x39); | |
3673 // XXX reg_mem doesn't support RIP-relative addressing yet | |
3674 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101 | |
3675 emit_d32_reloc(cbuf, const_address); | |
3676 | |
3677 | |
3678 // jne,s done | |
3679 emit_opcode(cbuf, 0x75); | |
3680 if (srcenc < 8 && dstenc < 8) { | |
3681 emit_d8(cbuf, 0xF); | |
3682 } else if (srcenc >= 8 && dstenc >= 8) { | |
3683 emit_d8(cbuf, 0x11); | |
3684 } else { | |
3685 emit_d8(cbuf, 0x10); | |
3686 } | |
3687 | |
3688 // subq rsp, #8 | |
3689 emit_opcode(cbuf, Assembler::REX_W); | |
3690 emit_opcode(cbuf, 0x83); | |
3691 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
3692 emit_d8(cbuf, 8); | |
3693 | |
3694 // movss [rsp], $src | |
3695 emit_opcode(cbuf, 0xF3); | |
3696 if (srcenc >= 8) { | |
3697 emit_opcode(cbuf, Assembler::REX_R); | |
3698 } | |
3699 emit_opcode(cbuf, 0x0F); | |
3700 emit_opcode(cbuf, 0x11); | |
3701 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
3702 | |
3703 // call f2l_fixup | |
3704 cbuf.set_insts_mark(); | |
3705 emit_opcode(cbuf, 0xE8); | |
3706 emit_d32_reloc(cbuf, | |
3707 (int) | |
3708 (StubRoutines::x86::f2l_fixup() - cbuf.insts_end() - 4), | |
3709 runtime_call_Relocation::spec(), | |
3710 RELOC_DISP32); | |
3711 | |
3712 // popq $dst | |
3713 if (dstenc >= 8) { | |
3714 emit_opcode(cbuf, Assembler::REX_B); | |
3715 } | |
3716 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
3717 | |
3718 // done: | |
3719 %} | |
3720 | |
3721 enc_class d2i_fixup(rRegI dst, regD src) | |
3722 %{ | |
3723 int dstenc = $dst$$reg; | |
3724 int srcenc = $src$$reg; | |
3725 | |
3726 // cmpl $dst, #0x80000000 | |
3727 if (dstenc >= 8) { | |
3728 emit_opcode(cbuf, Assembler::REX_B); | |
3729 } | |
3730 emit_opcode(cbuf, 0x81); | |
3731 emit_rm(cbuf, 0x3, 0x7, dstenc & 7); | |
3732 emit_d32(cbuf, 0x80000000); | |
3733 | |
3734 // jne,s done | |
3735 emit_opcode(cbuf, 0x75); | |
3736 if (srcenc < 8 && dstenc < 8) { | |
3737 emit_d8(cbuf, 0xF); | |
3738 } else if (srcenc >= 8 && dstenc >= 8) { | |
3739 emit_d8(cbuf, 0x11); | |
3740 } else { | |
3741 emit_d8(cbuf, 0x10); | |
3742 } | |
3743 | |
3744 // subq rsp, #8 | |
3745 emit_opcode(cbuf, Assembler::REX_W); | |
3746 emit_opcode(cbuf, 0x83); | |
3747 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
3748 emit_d8(cbuf, 8); | |
3749 | |
3750 // movsd [rsp], $src | |
3751 emit_opcode(cbuf, 0xF2); | |
3752 if (srcenc >= 8) { | |
3753 emit_opcode(cbuf, Assembler::REX_R); | |
3754 } | |
3755 emit_opcode(cbuf, 0x0F); | |
3756 emit_opcode(cbuf, 0x11); | |
3757 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
3758 | |
3759 // call d2i_fixup | |
3760 cbuf.set_insts_mark(); | |
3761 emit_opcode(cbuf, 0xE8); | |
3762 emit_d32_reloc(cbuf, | |
3763 (int) | |
3764 (StubRoutines::x86::d2i_fixup() - cbuf.insts_end() - 4), | |
3765 runtime_call_Relocation::spec(), | |
3766 RELOC_DISP32); | |
3767 | |
3768 // popq $dst | |
3769 if (dstenc >= 8) { | |
3770 emit_opcode(cbuf, Assembler::REX_B); | |
3771 } | |
3772 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
3773 | |
3774 // done: | |
3775 %} | |
3776 | |
3777 enc_class d2l_fixup(rRegL dst, regD src) | |
3778 %{ | |
3779 int dstenc = $dst$$reg; | |
3780 int srcenc = $src$$reg; | |
3781 address const_address = (address) StubRoutines::x86::double_sign_flip(); | |
3782 | |
3783 // cmpq $dst, [0x8000000000000000] | |
3784 cbuf.set_insts_mark(); | |
3785 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
3786 emit_opcode(cbuf, 0x39); | |
3787 // XXX reg_mem doesn't support RIP-relative addressing yet | |
3788 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101 | |
3789 emit_d32_reloc(cbuf, const_address); | |
3790 | |
3791 | |
3792 // jne,s done | |
3793 emit_opcode(cbuf, 0x75); | |
3794 if (srcenc < 8 && dstenc < 8) { | |
3795 emit_d8(cbuf, 0xF); | |
3796 } else if (srcenc >= 8 && dstenc >= 8) { | |
3797 emit_d8(cbuf, 0x11); | |
3798 } else { | |
3799 emit_d8(cbuf, 0x10); | |
3800 } | |
3801 | |
3802 // subq rsp, #8 | |
3803 emit_opcode(cbuf, Assembler::REX_W); | |
3804 emit_opcode(cbuf, 0x83); | |
3805 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
3806 emit_d8(cbuf, 8); | |
3807 | |
3808 // movsd [rsp], $src | |
3809 emit_opcode(cbuf, 0xF2); | |
3810 if (srcenc >= 8) { | |
3811 emit_opcode(cbuf, Assembler::REX_R); | |
3812 } | |
3813 emit_opcode(cbuf, 0x0F); | |
3814 emit_opcode(cbuf, 0x11); | |
3815 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
3816 | |
3817 // call d2l_fixup | |
3818 cbuf.set_insts_mark(); | |
3819 emit_opcode(cbuf, 0xE8); | |
3820 emit_d32_reloc(cbuf, | |
3821 (int) | |
3822 (StubRoutines::x86::d2l_fixup() - cbuf.insts_end() - 4), | |
3823 runtime_call_Relocation::spec(), | |
3824 RELOC_DISP32); | |
3825 | |
3826 // popq $dst | |
3827 if (dstenc >= 8) { | |
3828 emit_opcode(cbuf, Assembler::REX_B); | |
3829 } | |
3830 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
3831 | |
3832 // done: | |
3833 %} | |
3834 %} | 3172 %} |
3835 | 3173 |
3836 | 3174 |
3837 | 3175 |
3838 //----------FRAME-------------------------------------------------------------- | 3176 //----------FRAME-------------------------------------------------------------- |
6154 %{ | 5492 %{ |
6155 match(Set dst (LoadF mem)); | 5493 match(Set dst (LoadF mem)); |
6156 | 5494 |
6157 ins_cost(145); // XXX | 5495 ins_cost(145); // XXX |
6158 format %{ "movss $dst, $mem\t# float" %} | 5496 format %{ "movss $dst, $mem\t# float" %} |
6159 opcode(0xF3, 0x0F, 0x10); | 5497 ins_encode %{ |
6160 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | 5498 __ movflt($dst$$XMMRegister, $mem$$Address); |
5499 %} | |
6161 ins_pipe(pipe_slow); // XXX | 5500 ins_pipe(pipe_slow); // XXX |
6162 %} | 5501 %} |
6163 | 5502 |
6164 // Load Double | 5503 // Load Double |
6165 instruct loadD_partial(regD dst, memory mem) | 5504 instruct loadD_partial(regD dst, memory mem) |
6167 predicate(!UseXmmLoadAndClearUpper); | 5506 predicate(!UseXmmLoadAndClearUpper); |
6168 match(Set dst (LoadD mem)); | 5507 match(Set dst (LoadD mem)); |
6169 | 5508 |
6170 ins_cost(145); // XXX | 5509 ins_cost(145); // XXX |
6171 format %{ "movlpd $dst, $mem\t# double" %} | 5510 format %{ "movlpd $dst, $mem\t# double" %} |
6172 opcode(0x66, 0x0F, 0x12); | 5511 ins_encode %{ |
6173 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | 5512 __ movdbl($dst$$XMMRegister, $mem$$Address); |
5513 %} | |
6174 ins_pipe(pipe_slow); // XXX | 5514 ins_pipe(pipe_slow); // XXX |
6175 %} | 5515 %} |
6176 | 5516 |
6177 instruct loadD(regD dst, memory mem) | 5517 instruct loadD(regD dst, memory mem) |
6178 %{ | 5518 %{ |
6179 predicate(UseXmmLoadAndClearUpper); | 5519 predicate(UseXmmLoadAndClearUpper); |
6180 match(Set dst (LoadD mem)); | 5520 match(Set dst (LoadD mem)); |
6181 | 5521 |
6182 ins_cost(145); // XXX | 5522 ins_cost(145); // XXX |
6183 format %{ "movsd $dst, $mem\t# double" %} | 5523 format %{ "movsd $dst, $mem\t# double" %} |
6184 opcode(0xF2, 0x0F, 0x10); | 5524 ins_encode %{ |
6185 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | 5525 __ movdbl($dst$$XMMRegister, $mem$$Address); |
5526 %} | |
6186 ins_pipe(pipe_slow); // XXX | 5527 ins_pipe(pipe_slow); // XXX |
6187 %} | 5528 %} |
6188 | 5529 |
6189 // Load Aligned Packed Byte to XMM register | 5530 // Load Aligned Packed Byte to XMM register |
6190 instruct loadA8B(regD dst, memory mem) %{ | 5531 instruct loadA8B(regD dst, memory mem) %{ |
6191 match(Set dst (Load8B mem)); | 5532 match(Set dst (Load8B mem)); |
6192 ins_cost(125); | 5533 ins_cost(125); |
6193 format %{ "MOVQ $dst,$mem\t! packed8B" %} | 5534 format %{ "MOVQ $dst,$mem\t! packed8B" %} |
6194 ins_encode( movq_ld(dst, mem)); | 5535 ins_encode %{ |
5536 __ movq($dst$$XMMRegister, $mem$$Address); | |
5537 %} | |
6195 ins_pipe( pipe_slow ); | 5538 ins_pipe( pipe_slow ); |
6196 %} | 5539 %} |
6197 | 5540 |
6198 // Load Aligned Packed Short to XMM register | 5541 // Load Aligned Packed Short to XMM register |
6199 instruct loadA4S(regD dst, memory mem) %{ | 5542 instruct loadA4S(regD dst, memory mem) %{ |
6200 match(Set dst (Load4S mem)); | 5543 match(Set dst (Load4S mem)); |
6201 ins_cost(125); | 5544 ins_cost(125); |
6202 format %{ "MOVQ $dst,$mem\t! packed4S" %} | 5545 format %{ "MOVQ $dst,$mem\t! packed4S" %} |
6203 ins_encode( movq_ld(dst, mem)); | 5546 ins_encode %{ |
5547 __ movq($dst$$XMMRegister, $mem$$Address); | |
5548 %} | |
6204 ins_pipe( pipe_slow ); | 5549 ins_pipe( pipe_slow ); |
6205 %} | 5550 %} |
6206 | 5551 |
6207 // Load Aligned Packed Char to XMM register | 5552 // Load Aligned Packed Char to XMM register |
6208 instruct loadA4C(regD dst, memory mem) %{ | 5553 instruct loadA4C(regD dst, memory mem) %{ |
6209 match(Set dst (Load4C mem)); | 5554 match(Set dst (Load4C mem)); |
6210 ins_cost(125); | 5555 ins_cost(125); |
6211 format %{ "MOVQ $dst,$mem\t! packed4C" %} | 5556 format %{ "MOVQ $dst,$mem\t! packed4C" %} |
6212 ins_encode( movq_ld(dst, mem)); | 5557 ins_encode %{ |
5558 __ movq($dst$$XMMRegister, $mem$$Address); | |
5559 %} | |
6213 ins_pipe( pipe_slow ); | 5560 ins_pipe( pipe_slow ); |
6214 %} | 5561 %} |
6215 | 5562 |
6216 // Load Aligned Packed Integer to XMM register | 5563 // Load Aligned Packed Integer to XMM register |
6217 instruct load2IU(regD dst, memory mem) %{ | 5564 instruct load2IU(regD dst, memory mem) %{ |
6218 match(Set dst (Load2I mem)); | 5565 match(Set dst (Load2I mem)); |
6219 ins_cost(125); | 5566 ins_cost(125); |
6220 format %{ "MOVQ $dst,$mem\t! packed2I" %} | 5567 format %{ "MOVQ $dst,$mem\t! packed2I" %} |
6221 ins_encode( movq_ld(dst, mem)); | 5568 ins_encode %{ |
5569 __ movq($dst$$XMMRegister, $mem$$Address); | |
5570 %} | |
6222 ins_pipe( pipe_slow ); | 5571 ins_pipe( pipe_slow ); |
6223 %} | 5572 %} |
6224 | 5573 |
6225 // Load Aligned Packed Single to XMM | 5574 // Load Aligned Packed Single to XMM |
6226 instruct loadA2F(regD dst, memory mem) %{ | 5575 instruct loadA2F(regD dst, memory mem) %{ |
6227 match(Set dst (Load2F mem)); | 5576 match(Set dst (Load2F mem)); |
6228 ins_cost(145); | 5577 ins_cost(125); |
6229 format %{ "MOVQ $dst,$mem\t! packed2F" %} | 5578 format %{ "MOVQ $dst,$mem\t! packed2F" %} |
6230 ins_encode( movq_ld(dst, mem)); | 5579 ins_encode %{ |
5580 __ movq($dst$$XMMRegister, $mem$$Address); | |
5581 %} | |
6231 ins_pipe( pipe_slow ); | 5582 ins_pipe( pipe_slow ); |
6232 %} | 5583 %} |
6233 | 5584 |
6234 // Load Effective Address | 5585 // Load Effective Address |
6235 instruct leaP8(rRegP dst, indOffset8 mem) | 5586 instruct leaP8(rRegP dst, indOffset8 mem) |
6538 %{ | 5889 %{ |
6539 match(Set dst src); | 5890 match(Set dst src); |
6540 ins_cost(100); | 5891 ins_cost(100); |
6541 | 5892 |
6542 format %{ "xorps $dst, $dst\t# float 0.0" %} | 5893 format %{ "xorps $dst, $dst\t# float 0.0" %} |
6543 opcode(0x0F, 0x57); | 5894 ins_encode %{ |
6544 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | 5895 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); |
5896 %} | |
6545 ins_pipe(pipe_slow); | 5897 ins_pipe(pipe_slow); |
6546 %} | 5898 %} |
6547 | 5899 |
6548 // Use the same format since predicate() can not be used here. | 5900 // Use the same format since predicate() can not be used here. |
6549 instruct loadConD(regD dst, immD con) %{ | 5901 instruct loadConD(regD dst, immD con) %{ |
6560 %{ | 5912 %{ |
6561 match(Set dst src); | 5913 match(Set dst src); |
6562 ins_cost(100); | 5914 ins_cost(100); |
6563 | 5915 |
6564 format %{ "xorpd $dst, $dst\t# double 0.0" %} | 5916 format %{ "xorpd $dst, $dst\t# double 0.0" %} |
6565 opcode(0x66, 0x0F, 0x57); | 5917 ins_encode %{ |
6566 ins_encode(OpcP, REX_reg_reg(dst, dst), OpcS, OpcT, reg_reg(dst, dst)); | 5918 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); |
5919 %} | |
6567 ins_pipe(pipe_slow); | 5920 ins_pipe(pipe_slow); |
6568 %} | 5921 %} |
6569 | 5922 |
6570 instruct loadSSI(rRegI dst, stackSlotI src) | 5923 instruct loadSSI(rRegI dst, stackSlotI src) |
6571 %{ | 5924 %{ |
6604 %{ | 5957 %{ |
6605 match(Set dst src); | 5958 match(Set dst src); |
6606 | 5959 |
6607 ins_cost(125); | 5960 ins_cost(125); |
6608 format %{ "movss $dst, $src\t# float stk" %} | 5961 format %{ "movss $dst, $src\t# float stk" %} |
6609 opcode(0xF3, 0x0F, 0x10); | 5962 ins_encode %{ |
6610 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 5963 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); |
5964 %} | |
6611 ins_pipe(pipe_slow); // XXX | 5965 ins_pipe(pipe_slow); // XXX |
6612 %} | 5966 %} |
6613 | 5967 |
6614 // Use the same format since predicate() can not be used here. | 5968 // Use the same format since predicate() can not be used here. |
6615 instruct loadSSD(regD dst, stackSlotD src) | 5969 instruct loadSSD(regD dst, stackSlotD src) |
6970 // Store Aligned Packed Byte XMM register to memory | 6324 // Store Aligned Packed Byte XMM register to memory |
6971 instruct storeA8B(memory mem, regD src) %{ | 6325 instruct storeA8B(memory mem, regD src) %{ |
6972 match(Set mem (Store8B mem src)); | 6326 match(Set mem (Store8B mem src)); |
6973 ins_cost(145); | 6327 ins_cost(145); |
6974 format %{ "MOVQ $mem,$src\t! packed8B" %} | 6328 format %{ "MOVQ $mem,$src\t! packed8B" %} |
6975 ins_encode( movq_st(mem, src)); | 6329 ins_encode %{ |
6330 __ movq($mem$$Address, $src$$XMMRegister); | |
6331 %} | |
6976 ins_pipe( pipe_slow ); | 6332 ins_pipe( pipe_slow ); |
6977 %} | 6333 %} |
6978 | 6334 |
6979 // Store Aligned Packed Char/Short XMM register to memory | 6335 // Store Aligned Packed Char/Short XMM register to memory |
6980 instruct storeA4C(memory mem, regD src) %{ | 6336 instruct storeA4C(memory mem, regD src) %{ |
6981 match(Set mem (Store4C mem src)); | 6337 match(Set mem (Store4C mem src)); |
6982 ins_cost(145); | 6338 ins_cost(145); |
6983 format %{ "MOVQ $mem,$src\t! packed4C" %} | 6339 format %{ "MOVQ $mem,$src\t! packed4C" %} |
6984 ins_encode( movq_st(mem, src)); | 6340 ins_encode %{ |
6341 __ movq($mem$$Address, $src$$XMMRegister); | |
6342 %} | |
6985 ins_pipe( pipe_slow ); | 6343 ins_pipe( pipe_slow ); |
6986 %} | 6344 %} |
6987 | 6345 |
6988 // Store Aligned Packed Integer XMM register to memory | 6346 // Store Aligned Packed Integer XMM register to memory |
6989 instruct storeA2I(memory mem, regD src) %{ | 6347 instruct storeA2I(memory mem, regD src) %{ |
6990 match(Set mem (Store2I mem src)); | 6348 match(Set mem (Store2I mem src)); |
6991 ins_cost(145); | 6349 ins_cost(145); |
6992 format %{ "MOVQ $mem,$src\t! packed2I" %} | 6350 format %{ "MOVQ $mem,$src\t! packed2I" %} |
6993 ins_encode( movq_st(mem, src)); | 6351 ins_encode %{ |
6352 __ movq($mem$$Address, $src$$XMMRegister); | |
6353 %} | |
6994 ins_pipe( pipe_slow ); | 6354 ins_pipe( pipe_slow ); |
6995 %} | 6355 %} |
6996 | 6356 |
6997 // Store CMS card-mark Immediate | 6357 // Store CMS card-mark Immediate |
6998 instruct storeImmCM0_reg(memory mem, immI0 zero) | 6358 instruct storeImmCM0_reg(memory mem, immI0 zero) |
7022 // Store Aligned Packed Single Float XMM register to memory | 6382 // Store Aligned Packed Single Float XMM register to memory |
7023 instruct storeA2F(memory mem, regD src) %{ | 6383 instruct storeA2F(memory mem, regD src) %{ |
7024 match(Set mem (Store2F mem src)); | 6384 match(Set mem (Store2F mem src)); |
7025 ins_cost(145); | 6385 ins_cost(145); |
7026 format %{ "MOVQ $mem,$src\t! packed2F" %} | 6386 format %{ "MOVQ $mem,$src\t! packed2F" %} |
7027 ins_encode( movq_st(mem, src)); | 6387 ins_encode %{ |
6388 __ movq($mem$$Address, $src$$XMMRegister); | |
6389 %} | |
7028 ins_pipe( pipe_slow ); | 6390 ins_pipe( pipe_slow ); |
7029 %} | 6391 %} |
7030 | 6392 |
7031 // Store Float | 6393 // Store Float |
7032 instruct storeF(memory mem, regF src) | 6394 instruct storeF(memory mem, regF src) |
7033 %{ | 6395 %{ |
7034 match(Set mem (StoreF mem src)); | 6396 match(Set mem (StoreF mem src)); |
7035 | 6397 |
7036 ins_cost(95); // XXX | 6398 ins_cost(95); // XXX |
7037 format %{ "movss $mem, $src\t# float" %} | 6399 format %{ "movss $mem, $src\t# float" %} |
7038 opcode(0xF3, 0x0F, 0x11); | 6400 ins_encode %{ |
7039 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem)); | 6401 __ movflt($mem$$Address, $src$$XMMRegister); |
6402 %} | |
7040 ins_pipe(pipe_slow); // XXX | 6403 ins_pipe(pipe_slow); // XXX |
7041 %} | 6404 %} |
7042 | 6405 |
7043 // Store immediate Float value (it is faster than store from XMM register) | 6406 // Store immediate Float value (it is faster than store from XMM register) |
7044 instruct storeF0(memory mem, immF0 zero) | 6407 instruct storeF0(memory mem, immF0 zero) |
7070 %{ | 6433 %{ |
7071 match(Set mem (StoreD mem src)); | 6434 match(Set mem (StoreD mem src)); |
7072 | 6435 |
7073 ins_cost(95); // XXX | 6436 ins_cost(95); // XXX |
7074 format %{ "movsd $mem, $src\t# double" %} | 6437 format %{ "movsd $mem, $src\t# double" %} |
7075 opcode(0xF2, 0x0F, 0x11); | 6438 ins_encode %{ |
7076 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem)); | 6439 __ movdbl($mem$$Address, $src$$XMMRegister); |
6440 %} | |
7077 ins_pipe(pipe_slow); // XXX | 6441 ins_pipe(pipe_slow); // XXX |
7078 %} | 6442 %} |
7079 | 6443 |
7080 // Store immediate double 0.0 (it is faster than store from XMM register) | 6444 // Store immediate double 0.0 (it is faster than store from XMM register) |
7081 instruct storeD0_imm(memory mem, immD0 src) | 6445 instruct storeD0_imm(memory mem, immD0 src) |
7140 %{ | 6504 %{ |
7141 match(Set dst src); | 6505 match(Set dst src); |
7142 | 6506 |
7143 ins_cost(95); // XXX | 6507 ins_cost(95); // XXX |
7144 format %{ "movss $dst, $src\t# float stk" %} | 6508 format %{ "movss $dst, $src\t# float stk" %} |
7145 opcode(0xF3, 0x0F, 0x11); | 6509 ins_encode %{ |
7146 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | 6510 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); |
6511 %} | |
7147 ins_pipe(pipe_slow); // XXX | 6512 ins_pipe(pipe_slow); // XXX |
7148 %} | 6513 %} |
7149 | 6514 |
7150 instruct storeSSD(stackSlotD dst, regD src) | 6515 instruct storeSSD(stackSlotD dst, regD src) |
7151 %{ | 6516 %{ |
7152 match(Set dst src); | 6517 match(Set dst src); |
7153 | 6518 |
7154 ins_cost(95); // XXX | 6519 ins_cost(95); // XXX |
7155 format %{ "movsd $dst, $src\t# double stk" %} | 6520 format %{ "movsd $dst, $src\t# double stk" %} |
7156 opcode(0xF2, 0x0F, 0x11); | 6521 ins_encode %{ |
7157 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | 6522 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); |
6523 %} | |
7158 ins_pipe(pipe_slow); // XXX | 6524 ins_pipe(pipe_slow); // XXX |
7159 %} | 6525 %} |
7160 | 6526 |
7161 //----------BSWAP Instructions------------------------------------------------- | 6527 //----------BSWAP Instructions------------------------------------------------- |
7162 instruct bytes_reverse_int(rRegI dst) %{ | 6528 instruct bytes_reverse_int(rRegI dst) %{ |
7449 instruct castX2P(rRegP dst, rRegL src) | 6815 instruct castX2P(rRegP dst, rRegL src) |
7450 %{ | 6816 %{ |
7451 match(Set dst (CastX2P src)); | 6817 match(Set dst (CastX2P src)); |
7452 | 6818 |
7453 format %{ "movq $dst, $src\t# long->ptr" %} | 6819 format %{ "movq $dst, $src\t# long->ptr" %} |
7454 ins_encode(enc_copy_wide(dst, src)); | 6820 ins_encode %{ |
6821 if ($dst$$reg != $src$$reg) { | |
6822 __ movptr($dst$$Register, $src$$Register); | |
6823 } | |
6824 %} | |
7455 ins_pipe(ialu_reg_reg); // XXX | 6825 ins_pipe(ialu_reg_reg); // XXX |
7456 %} | 6826 %} |
7457 | 6827 |
7458 instruct castP2X(rRegL dst, rRegP src) | 6828 instruct castP2X(rRegL dst, rRegP src) |
7459 %{ | 6829 %{ |
7460 match(Set dst (CastP2X src)); | 6830 match(Set dst (CastP2X src)); |
7461 | 6831 |
7462 format %{ "movq $dst, $src\t# ptr -> long" %} | 6832 format %{ "movq $dst, $src\t# ptr -> long" %} |
7463 ins_encode(enc_copy_wide(dst, src)); | 6833 ins_encode %{ |
6834 if ($dst$$reg != $src$$reg) { | |
6835 __ movptr($dst$$Register, $src$$Register); | |
6836 } | |
6837 %} | |
7464 ins_pipe(ialu_reg_reg); // XXX | 6838 ins_pipe(ialu_reg_reg); // XXX |
7465 %} | 6839 %} |
7466 | 6840 |
7467 | 6841 |
7468 // Convert oop pointer into compressed form | 6842 // Convert oop pointer into compressed form |
7811 | 7185 |
7812 ins_cost(200); // XXX | 7186 ins_cost(200); // XXX |
7813 format %{ "jn$cop skip\t# signed cmove float\n\t" | 7187 format %{ "jn$cop skip\t# signed cmove float\n\t" |
7814 "movss $dst, $src\n" | 7188 "movss $dst, $src\n" |
7815 "skip:" %} | 7189 "skip:" %} |
7816 ins_encode(enc_cmovf_branch(cop, dst, src)); | 7190 ins_encode %{ |
7191 Label Lskip; | |
7192 // Invert sense of branch from sense of CMOV | |
7193 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
7194 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
7195 __ bind(Lskip); | |
7196 %} | |
7817 ins_pipe(pipe_slow); | 7197 ins_pipe(pipe_slow); |
7818 %} | 7198 %} |
7819 | 7199 |
7820 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) | 7200 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) |
7821 // %{ | 7201 // %{ |
7835 | 7215 |
7836 ins_cost(200); // XXX | 7216 ins_cost(200); // XXX |
7837 format %{ "jn$cop skip\t# unsigned cmove float\n\t" | 7217 format %{ "jn$cop skip\t# unsigned cmove float\n\t" |
7838 "movss $dst, $src\n" | 7218 "movss $dst, $src\n" |
7839 "skip:" %} | 7219 "skip:" %} |
7840 ins_encode(enc_cmovf_branch(cop, dst, src)); | 7220 ins_encode %{ |
7221 Label Lskip; | |
7222 // Invert sense of branch from sense of CMOV | |
7223 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
7224 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
7225 __ bind(Lskip); | |
7226 %} | |
7841 ins_pipe(pipe_slow); | 7227 ins_pipe(pipe_slow); |
7842 %} | 7228 %} |
7843 | 7229 |
7844 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{ | 7230 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{ |
7845 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | 7231 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
7855 | 7241 |
7856 ins_cost(200); // XXX | 7242 ins_cost(200); // XXX |
7857 format %{ "jn$cop skip\t# signed cmove double\n\t" | 7243 format %{ "jn$cop skip\t# signed cmove double\n\t" |
7858 "movsd $dst, $src\n" | 7244 "movsd $dst, $src\n" |
7859 "skip:" %} | 7245 "skip:" %} |
7860 ins_encode(enc_cmovd_branch(cop, dst, src)); | 7246 ins_encode %{ |
7247 Label Lskip; | |
7248 // Invert sense of branch from sense of CMOV | |
7249 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
7250 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
7251 __ bind(Lskip); | |
7252 %} | |
7861 ins_pipe(pipe_slow); | 7253 ins_pipe(pipe_slow); |
7862 %} | 7254 %} |
7863 | 7255 |
7864 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) | 7256 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) |
7865 %{ | 7257 %{ |
7867 | 7259 |
7868 ins_cost(200); // XXX | 7260 ins_cost(200); // XXX |
7869 format %{ "jn$cop skip\t# unsigned cmove double\n\t" | 7261 format %{ "jn$cop skip\t# unsigned cmove double\n\t" |
7870 "movsd $dst, $src\n" | 7262 "movsd $dst, $src\n" |
7871 "skip:" %} | 7263 "skip:" %} |
7872 ins_encode(enc_cmovd_branch(cop, dst, src)); | 7264 ins_encode %{ |
7265 Label Lskip; | |
7266 // Invert sense of branch from sense of CMOV | |
7267 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
7268 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
7269 __ bind(Lskip); | |
7270 %} | |
7873 ins_pipe(pipe_slow); | 7271 ins_pipe(pipe_slow); |
7874 %} | 7272 %} |
7875 | 7273 |
7876 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ | 7274 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ |
7877 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | 7275 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
10189 format %{ "ucomiss $src1, $src2\n\t" | 9587 format %{ "ucomiss $src1, $src2\n\t" |
10190 "jnp,s exit\n\t" | 9588 "jnp,s exit\n\t" |
10191 "pushfq\t# saw NaN, set CF\n\t" | 9589 "pushfq\t# saw NaN, set CF\n\t" |
10192 "andq [rsp], #0xffffff2b\n\t" | 9590 "andq [rsp], #0xffffff2b\n\t" |
10193 "popfq\n" | 9591 "popfq\n" |
10194 "exit: nop\t# avoid branch to branch" %} | 9592 "exit:" %} |
10195 opcode(0x0F, 0x2E); | 9593 ins_encode %{ |
10196 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2), | 9594 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
10197 cmpfp_fixup); | 9595 emit_cmpfp_fixup(_masm); |
9596 %} | |
10198 ins_pipe(pipe_slow); | 9597 ins_pipe(pipe_slow); |
10199 %} | 9598 %} |
10200 | 9599 |
10201 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{ | 9600 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{ |
10202 match(Set cr (CmpF src1 src2)); | 9601 match(Set cr (CmpF src1 src2)); |
10203 | 9602 |
10204 ins_cost(145); | 9603 ins_cost(100); |
10205 format %{ "ucomiss $src1, $src2" %} | 9604 format %{ "ucomiss $src1, $src2" %} |
10206 ins_encode %{ | 9605 ins_encode %{ |
10207 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | 9606 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
10208 %} | 9607 %} |
10209 ins_pipe(pipe_slow); | 9608 ins_pipe(pipe_slow); |
10217 format %{ "ucomiss $src1, $src2\n\t" | 9616 format %{ "ucomiss $src1, $src2\n\t" |
10218 "jnp,s exit\n\t" | 9617 "jnp,s exit\n\t" |
10219 "pushfq\t# saw NaN, set CF\n\t" | 9618 "pushfq\t# saw NaN, set CF\n\t" |
10220 "andq [rsp], #0xffffff2b\n\t" | 9619 "andq [rsp], #0xffffff2b\n\t" |
10221 "popfq\n" | 9620 "popfq\n" |
10222 "exit: nop\t# avoid branch to branch" %} | 9621 "exit:" %} |
10223 opcode(0x0F, 0x2E); | 9622 ins_encode %{ |
10224 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2), | 9623 __ ucomiss($src1$$XMMRegister, $src2$$Address); |
10225 cmpfp_fixup); | 9624 emit_cmpfp_fixup(_masm); |
9625 %} | |
10226 ins_pipe(pipe_slow); | 9626 ins_pipe(pipe_slow); |
10227 %} | 9627 %} |
10228 | 9628 |
10229 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{ | 9629 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{ |
10230 match(Set cr (CmpF src1 (LoadF src2))); | 9630 match(Set cr (CmpF src1 (LoadF src2))); |
10231 | 9631 |
10232 ins_cost(100); | 9632 ins_cost(100); |
10233 format %{ "ucomiss $src1, $src2" %} | 9633 format %{ "ucomiss $src1, $src2" %} |
10234 opcode(0x0F, 0x2E); | 9634 ins_encode %{ |
10235 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2)); | 9635 __ ucomiss($src1$$XMMRegister, $src2$$Address); |
9636 %} | |
10236 ins_pipe(pipe_slow); | 9637 ins_pipe(pipe_slow); |
10237 %} | 9638 %} |
10238 | 9639 |
10239 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{ | 9640 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{ |
10240 match(Set cr (CmpF src con)); | 9641 match(Set cr (CmpF src con)); |
10243 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" | 9644 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
10244 "jnp,s exit\n\t" | 9645 "jnp,s exit\n\t" |
10245 "pushfq\t# saw NaN, set CF\n\t" | 9646 "pushfq\t# saw NaN, set CF\n\t" |
10246 "andq [rsp], #0xffffff2b\n\t" | 9647 "andq [rsp], #0xffffff2b\n\t" |
10247 "popfq\n" | 9648 "popfq\n" |
10248 "exit: nop\t# avoid branch to branch" %} | 9649 "exit:" %} |
10249 ins_encode %{ | 9650 ins_encode %{ |
10250 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | 9651 __ ucomiss($src$$XMMRegister, $constantaddress($con)); |
10251 emit_cmpfp_fixup(_masm); | 9652 emit_cmpfp_fixup(_masm); |
10252 %} | 9653 %} |
10253 ins_pipe(pipe_slow); | 9654 ins_pipe(pipe_slow); |
10271 format %{ "ucomisd $src1, $src2\n\t" | 9672 format %{ "ucomisd $src1, $src2\n\t" |
10272 "jnp,s exit\n\t" | 9673 "jnp,s exit\n\t" |
10273 "pushfq\t# saw NaN, set CF\n\t" | 9674 "pushfq\t# saw NaN, set CF\n\t" |
10274 "andq [rsp], #0xffffff2b\n\t" | 9675 "andq [rsp], #0xffffff2b\n\t" |
10275 "popfq\n" | 9676 "popfq\n" |
10276 "exit: nop\t# avoid branch to branch" %} | 9677 "exit:" %} |
10277 opcode(0x66, 0x0F, 0x2E); | 9678 ins_encode %{ |
10278 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2), | 9679 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
10279 cmpfp_fixup); | 9680 emit_cmpfp_fixup(_masm); |
9681 %} | |
10280 ins_pipe(pipe_slow); | 9682 ins_pipe(pipe_slow); |
10281 %} | 9683 %} |
10282 | 9684 |
10283 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{ | 9685 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{ |
10284 match(Set cr (CmpD src1 src2)); | 9686 match(Set cr (CmpD src1 src2)); |
10299 format %{ "ucomisd $src1, $src2\n\t" | 9701 format %{ "ucomisd $src1, $src2\n\t" |
10300 "jnp,s exit\n\t" | 9702 "jnp,s exit\n\t" |
10301 "pushfq\t# saw NaN, set CF\n\t" | 9703 "pushfq\t# saw NaN, set CF\n\t" |
10302 "andq [rsp], #0xffffff2b\n\t" | 9704 "andq [rsp], #0xffffff2b\n\t" |
10303 "popfq\n" | 9705 "popfq\n" |
10304 "exit: nop\t# avoid branch to branch" %} | 9706 "exit:" %} |
10305 opcode(0x66, 0x0F, 0x2E); | 9707 ins_encode %{ |
10306 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2), | 9708 __ ucomisd($src1$$XMMRegister, $src2$$Address); |
10307 cmpfp_fixup); | 9709 emit_cmpfp_fixup(_masm); |
9710 %} | |
10308 ins_pipe(pipe_slow); | 9711 ins_pipe(pipe_slow); |
10309 %} | 9712 %} |
10310 | 9713 |
10311 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{ | 9714 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{ |
10312 match(Set cr (CmpD src1 (LoadD src2))); | 9715 match(Set cr (CmpD src1 (LoadD src2))); |
10313 | 9716 |
10314 ins_cost(100); | 9717 ins_cost(100); |
10315 format %{ "ucomisd $src1, $src2" %} | 9718 format %{ "ucomisd $src1, $src2" %} |
10316 opcode(0x66, 0x0F, 0x2E); | 9719 ins_encode %{ |
10317 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2)); | 9720 __ ucomisd($src1$$XMMRegister, $src2$$Address); |
9721 %} | |
10318 ins_pipe(pipe_slow); | 9722 ins_pipe(pipe_slow); |
10319 %} | 9723 %} |
10320 | 9724 |
10321 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{ | 9725 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{ |
10322 match(Set cr (CmpD src con)); | 9726 match(Set cr (CmpD src con)); |
10325 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" | 9729 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
10326 "jnp,s exit\n\t" | 9730 "jnp,s exit\n\t" |
10327 "pushfq\t# saw NaN, set CF\n\t" | 9731 "pushfq\t# saw NaN, set CF\n\t" |
10328 "andq [rsp], #0xffffff2b\n\t" | 9732 "andq [rsp], #0xffffff2b\n\t" |
10329 "popfq\n" | 9733 "popfq\n" |
10330 "exit: nop\t# avoid branch to branch" %} | 9734 "exit:" %} |
10331 ins_encode %{ | 9735 ins_encode %{ |
10332 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | 9736 __ ucomisd($src$$XMMRegister, $constantaddress($con)); |
10333 emit_cmpfp_fixup(_masm); | 9737 emit_cmpfp_fixup(_masm); |
10334 %} | 9738 %} |
10335 ins_pipe(pipe_slow); | 9739 ins_pipe(pipe_slow); |
10357 "jp,s done\n\t" | 9761 "jp,s done\n\t" |
10358 "jb,s done\n\t" | 9762 "jb,s done\n\t" |
10359 "setne $dst\n\t" | 9763 "setne $dst\n\t" |
10360 "movzbl $dst, $dst\n" | 9764 "movzbl $dst, $dst\n" |
10361 "done:" %} | 9765 "done:" %} |
10362 | 9766 ins_encode %{ |
10363 opcode(0x0F, 0x2E); | 9767 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
10364 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2), | 9768 emit_cmpfp3(_masm, $dst$$Register); |
10365 cmpfp3(dst)); | 9769 %} |
10366 ins_pipe(pipe_slow); | 9770 ins_pipe(pipe_slow); |
10367 %} | 9771 %} |
10368 | 9772 |
10369 // Compare into -1,0,1 | 9773 // Compare into -1,0,1 |
10370 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) | 9774 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) |
10378 "jp,s done\n\t" | 9782 "jp,s done\n\t" |
10379 "jb,s done\n\t" | 9783 "jb,s done\n\t" |
10380 "setne $dst\n\t" | 9784 "setne $dst\n\t" |
10381 "movzbl $dst, $dst\n" | 9785 "movzbl $dst, $dst\n" |
10382 "done:" %} | 9786 "done:" %} |
10383 | 9787 ins_encode %{ |
10384 opcode(0x0F, 0x2E); | 9788 __ ucomiss($src1$$XMMRegister, $src2$$Address); |
10385 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2), | 9789 emit_cmpfp3(_masm, $dst$$Register); |
10386 cmpfp3(dst)); | 9790 %} |
10387 ins_pipe(pipe_slow); | 9791 ins_pipe(pipe_slow); |
10388 %} | 9792 %} |
10389 | 9793 |
10390 // Compare into -1,0,1 | 9794 // Compare into -1,0,1 |
10391 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{ | 9795 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{ |
10399 "jb,s done\n\t" | 9803 "jb,s done\n\t" |
10400 "setne $dst\n\t" | 9804 "setne $dst\n\t" |
10401 "movzbl $dst, $dst\n" | 9805 "movzbl $dst, $dst\n" |
10402 "done:" %} | 9806 "done:" %} |
10403 ins_encode %{ | 9807 ins_encode %{ |
10404 Label L_done; | |
10405 Register Rdst = $dst$$Register; | |
10406 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | 9808 __ ucomiss($src$$XMMRegister, $constantaddress($con)); |
10407 __ movl(Rdst, -1); | 9809 emit_cmpfp3(_masm, $dst$$Register); |
10408 __ jcc(Assembler::parity, L_done); | |
10409 __ jcc(Assembler::below, L_done); | |
10410 __ setb(Assembler::notEqual, Rdst); | |
10411 __ movzbl(Rdst, Rdst); | |
10412 __ bind(L_done); | |
10413 %} | 9810 %} |
10414 ins_pipe(pipe_slow); | 9811 ins_pipe(pipe_slow); |
10415 %} | 9812 %} |
10416 | 9813 |
10417 // Compare into -1,0,1 | 9814 // Compare into -1,0,1 |
10426 "jp,s done\n\t" | 9823 "jp,s done\n\t" |
10427 "jb,s done\n\t" | 9824 "jb,s done\n\t" |
10428 "setne $dst\n\t" | 9825 "setne $dst\n\t" |
10429 "movzbl $dst, $dst\n" | 9826 "movzbl $dst, $dst\n" |
10430 "done:" %} | 9827 "done:" %} |
10431 | 9828 ins_encode %{ |
10432 opcode(0x66, 0x0F, 0x2E); | 9829 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
10433 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2), | 9830 emit_cmpfp3(_masm, $dst$$Register); |
10434 cmpfp3(dst)); | 9831 %} |
10435 ins_pipe(pipe_slow); | 9832 ins_pipe(pipe_slow); |
10436 %} | 9833 %} |
10437 | 9834 |
10438 // Compare into -1,0,1 | 9835 // Compare into -1,0,1 |
10439 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) | 9836 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) |
10447 "jp,s done\n\t" | 9844 "jp,s done\n\t" |
10448 "jb,s done\n\t" | 9845 "jb,s done\n\t" |
10449 "setne $dst\n\t" | 9846 "setne $dst\n\t" |
10450 "movzbl $dst, $dst\n" | 9847 "movzbl $dst, $dst\n" |
10451 "done:" %} | 9848 "done:" %} |
10452 | 9849 ins_encode %{ |
10453 opcode(0x66, 0x0F, 0x2E); | 9850 __ ucomisd($src1$$XMMRegister, $src2$$Address); |
10454 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2), | 9851 emit_cmpfp3(_masm, $dst$$Register); |
10455 cmpfp3(dst)); | 9852 %} |
10456 ins_pipe(pipe_slow); | 9853 ins_pipe(pipe_slow); |
10457 %} | 9854 %} |
10458 | 9855 |
10459 // Compare into -1,0,1 | 9856 // Compare into -1,0,1 |
10460 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{ | 9857 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{ |
10468 "jb,s done\n\t" | 9865 "jb,s done\n\t" |
10469 "setne $dst\n\t" | 9866 "setne $dst\n\t" |
10470 "movzbl $dst, $dst\n" | 9867 "movzbl $dst, $dst\n" |
10471 "done:" %} | 9868 "done:" %} |
10472 ins_encode %{ | 9869 ins_encode %{ |
10473 Register Rdst = $dst$$Register; | |
10474 Label L_done; | |
10475 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | 9870 __ ucomisd($src$$XMMRegister, $constantaddress($con)); |
10476 __ movl(Rdst, -1); | 9871 emit_cmpfp3(_masm, $dst$$Register); |
10477 __ jcc(Assembler::parity, L_done); | |
10478 __ jcc(Assembler::below, L_done); | |
10479 __ setb(Assembler::notEqual, Rdst); | |
10480 __ movzbl(Rdst, Rdst); | |
10481 __ bind(L_done); | |
10482 %} | 9872 %} |
10483 ins_pipe(pipe_slow); | 9873 ins_pipe(pipe_slow); |
10484 %} | 9874 %} |
10485 | 9875 |
10486 instruct addF_reg(regF dst, regF src) | 9876 instruct addF_reg(regF dst, regF src) |
10487 %{ | 9877 %{ |
10488 match(Set dst (AddF dst src)); | 9878 match(Set dst (AddF dst src)); |
10489 | 9879 |
10490 format %{ "addss $dst, $src" %} | 9880 format %{ "addss $dst, $src" %} |
10491 ins_cost(150); // XXX | 9881 ins_cost(150); // XXX |
10492 opcode(0xF3, 0x0F, 0x58); | 9882 ins_encode %{ |
10493 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 9883 __ addss($dst$$XMMRegister, $src$$XMMRegister); |
9884 %} | |
10494 ins_pipe(pipe_slow); | 9885 ins_pipe(pipe_slow); |
10495 %} | 9886 %} |
10496 | 9887 |
10497 instruct addF_mem(regF dst, memory src) | 9888 instruct addF_mem(regF dst, memory src) |
10498 %{ | 9889 %{ |
10499 match(Set dst (AddF dst (LoadF src))); | 9890 match(Set dst (AddF dst (LoadF src))); |
10500 | 9891 |
10501 format %{ "addss $dst, $src" %} | 9892 format %{ "addss $dst, $src" %} |
10502 ins_cost(150); // XXX | 9893 ins_cost(150); // XXX |
10503 opcode(0xF3, 0x0F, 0x58); | 9894 ins_encode %{ |
10504 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 9895 __ addss($dst$$XMMRegister, $src$$Address); |
9896 %} | |
10505 ins_pipe(pipe_slow); | 9897 ins_pipe(pipe_slow); |
10506 %} | 9898 %} |
10507 | 9899 |
10508 instruct addF_imm(regF dst, immF con) %{ | 9900 instruct addF_imm(regF dst, immF con) %{ |
10509 match(Set dst (AddF dst con)); | 9901 match(Set dst (AddF dst con)); |
10519 %{ | 9911 %{ |
10520 match(Set dst (AddD dst src)); | 9912 match(Set dst (AddD dst src)); |
10521 | 9913 |
10522 format %{ "addsd $dst, $src" %} | 9914 format %{ "addsd $dst, $src" %} |
10523 ins_cost(150); // XXX | 9915 ins_cost(150); // XXX |
10524 opcode(0xF2, 0x0F, 0x58); | 9916 ins_encode %{ |
10525 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 9917 __ addsd($dst$$XMMRegister, $src$$XMMRegister); |
9918 %} | |
10526 ins_pipe(pipe_slow); | 9919 ins_pipe(pipe_slow); |
10527 %} | 9920 %} |
10528 | 9921 |
10529 instruct addD_mem(regD dst, memory src) | 9922 instruct addD_mem(regD dst, memory src) |
10530 %{ | 9923 %{ |
10531 match(Set dst (AddD dst (LoadD src))); | 9924 match(Set dst (AddD dst (LoadD src))); |
10532 | 9925 |
10533 format %{ "addsd $dst, $src" %} | 9926 format %{ "addsd $dst, $src" %} |
10534 ins_cost(150); // XXX | 9927 ins_cost(150); // XXX |
10535 opcode(0xF2, 0x0F, 0x58); | 9928 ins_encode %{ |
10536 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 9929 __ addsd($dst$$XMMRegister, $src$$Address); |
9930 %} | |
10537 ins_pipe(pipe_slow); | 9931 ins_pipe(pipe_slow); |
10538 %} | 9932 %} |
10539 | 9933 |
10540 instruct addD_imm(regD dst, immD con) %{ | 9934 instruct addD_imm(regD dst, immD con) %{ |
10541 match(Set dst (AddD dst con)); | 9935 match(Set dst (AddD dst con)); |
10551 %{ | 9945 %{ |
10552 match(Set dst (SubF dst src)); | 9946 match(Set dst (SubF dst src)); |
10553 | 9947 |
10554 format %{ "subss $dst, $src" %} | 9948 format %{ "subss $dst, $src" %} |
10555 ins_cost(150); // XXX | 9949 ins_cost(150); // XXX |
10556 opcode(0xF3, 0x0F, 0x5C); | 9950 ins_encode %{ |
10557 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 9951 __ subss($dst$$XMMRegister, $src$$XMMRegister); |
9952 %} | |
10558 ins_pipe(pipe_slow); | 9953 ins_pipe(pipe_slow); |
10559 %} | 9954 %} |
10560 | 9955 |
10561 instruct subF_mem(regF dst, memory src) | 9956 instruct subF_mem(regF dst, memory src) |
10562 %{ | 9957 %{ |
10563 match(Set dst (SubF dst (LoadF src))); | 9958 match(Set dst (SubF dst (LoadF src))); |
10564 | 9959 |
10565 format %{ "subss $dst, $src" %} | 9960 format %{ "subss $dst, $src" %} |
10566 ins_cost(150); // XXX | 9961 ins_cost(150); // XXX |
10567 opcode(0xF3, 0x0F, 0x5C); | 9962 ins_encode %{ |
10568 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 9963 __ subss($dst$$XMMRegister, $src$$Address); |
9964 %} | |
10569 ins_pipe(pipe_slow); | 9965 ins_pipe(pipe_slow); |
10570 %} | 9966 %} |
10571 | 9967 |
10572 instruct subF_imm(regF dst, immF con) %{ | 9968 instruct subF_imm(regF dst, immF con) %{ |
10573 match(Set dst (SubF dst con)); | 9969 match(Set dst (SubF dst con)); |
10583 %{ | 9979 %{ |
10584 match(Set dst (SubD dst src)); | 9980 match(Set dst (SubD dst src)); |
10585 | 9981 |
10586 format %{ "subsd $dst, $src" %} | 9982 format %{ "subsd $dst, $src" %} |
10587 ins_cost(150); // XXX | 9983 ins_cost(150); // XXX |
10588 opcode(0xF2, 0x0F, 0x5C); | 9984 ins_encode %{ |
10589 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 9985 __ subsd($dst$$XMMRegister, $src$$XMMRegister); |
9986 %} | |
10590 ins_pipe(pipe_slow); | 9987 ins_pipe(pipe_slow); |
10591 %} | 9988 %} |
10592 | 9989 |
10593 instruct subD_mem(regD dst, memory src) | 9990 instruct subD_mem(regD dst, memory src) |
10594 %{ | 9991 %{ |
10595 match(Set dst (SubD dst (LoadD src))); | 9992 match(Set dst (SubD dst (LoadD src))); |
10596 | 9993 |
10597 format %{ "subsd $dst, $src" %} | 9994 format %{ "subsd $dst, $src" %} |
10598 ins_cost(150); // XXX | 9995 ins_cost(150); // XXX |
10599 opcode(0xF2, 0x0F, 0x5C); | 9996 ins_encode %{ |
10600 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 9997 __ subsd($dst$$XMMRegister, $src$$Address); |
9998 %} | |
10601 ins_pipe(pipe_slow); | 9999 ins_pipe(pipe_slow); |
10602 %} | 10000 %} |
10603 | 10001 |
10604 instruct subD_imm(regD dst, immD con) %{ | 10002 instruct subD_imm(regD dst, immD con) %{ |
10605 match(Set dst (SubD dst con)); | 10003 match(Set dst (SubD dst con)); |
10615 %{ | 10013 %{ |
10616 match(Set dst (MulF dst src)); | 10014 match(Set dst (MulF dst src)); |
10617 | 10015 |
10618 format %{ "mulss $dst, $src" %} | 10016 format %{ "mulss $dst, $src" %} |
10619 ins_cost(150); // XXX | 10017 ins_cost(150); // XXX |
10620 opcode(0xF3, 0x0F, 0x59); | 10018 ins_encode %{ |
10621 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 10019 __ mulss($dst$$XMMRegister, $src$$XMMRegister); |
10020 %} | |
10622 ins_pipe(pipe_slow); | 10021 ins_pipe(pipe_slow); |
10623 %} | 10022 %} |
10624 | 10023 |
10625 instruct mulF_mem(regF dst, memory src) | 10024 instruct mulF_mem(regF dst, memory src) |
10626 %{ | 10025 %{ |
10627 match(Set dst (MulF dst (LoadF src))); | 10026 match(Set dst (MulF dst (LoadF src))); |
10628 | 10027 |
10629 format %{ "mulss $dst, $src" %} | 10028 format %{ "mulss $dst, $src" %} |
10630 ins_cost(150); // XXX | 10029 ins_cost(150); // XXX |
10631 opcode(0xF3, 0x0F, 0x59); | 10030 ins_encode %{ |
10632 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 10031 __ mulss($dst$$XMMRegister, $src$$Address); |
10032 %} | |
10633 ins_pipe(pipe_slow); | 10033 ins_pipe(pipe_slow); |
10634 %} | 10034 %} |
10635 | 10035 |
10636 instruct mulF_imm(regF dst, immF con) %{ | 10036 instruct mulF_imm(regF dst, immF con) %{ |
10637 match(Set dst (MulF dst con)); | 10037 match(Set dst (MulF dst con)); |
10647 %{ | 10047 %{ |
10648 match(Set dst (MulD dst src)); | 10048 match(Set dst (MulD dst src)); |
10649 | 10049 |
10650 format %{ "mulsd $dst, $src" %} | 10050 format %{ "mulsd $dst, $src" %} |
10651 ins_cost(150); // XXX | 10051 ins_cost(150); // XXX |
10652 opcode(0xF2, 0x0F, 0x59); | 10052 ins_encode %{ |
10653 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 10053 __ mulsd($dst$$XMMRegister, $src$$XMMRegister); |
10054 %} | |
10654 ins_pipe(pipe_slow); | 10055 ins_pipe(pipe_slow); |
10655 %} | 10056 %} |
10656 | 10057 |
10657 instruct mulD_mem(regD dst, memory src) | 10058 instruct mulD_mem(regD dst, memory src) |
10658 %{ | 10059 %{ |
10659 match(Set dst (MulD dst (LoadD src))); | 10060 match(Set dst (MulD dst (LoadD src))); |
10660 | 10061 |
10661 format %{ "mulsd $dst, $src" %} | 10062 format %{ "mulsd $dst, $src" %} |
10662 ins_cost(150); // XXX | 10063 ins_cost(150); // XXX |
10663 opcode(0xF2, 0x0F, 0x59); | 10064 ins_encode %{ |
10664 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 10065 __ mulsd($dst$$XMMRegister, $src$$Address); |
10066 %} | |
10665 ins_pipe(pipe_slow); | 10067 ins_pipe(pipe_slow); |
10666 %} | 10068 %} |
10667 | 10069 |
10668 instruct mulD_imm(regD dst, immD con) %{ | 10070 instruct mulD_imm(regD dst, immD con) %{ |
10669 match(Set dst (MulD dst con)); | 10071 match(Set dst (MulD dst con)); |
10679 %{ | 10081 %{ |
10680 match(Set dst (DivF dst src)); | 10082 match(Set dst (DivF dst src)); |
10681 | 10083 |
10682 format %{ "divss $dst, $src" %} | 10084 format %{ "divss $dst, $src" %} |
10683 ins_cost(150); // XXX | 10085 ins_cost(150); // XXX |
10684 opcode(0xF3, 0x0F, 0x5E); | 10086 ins_encode %{ |
10685 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 10087 __ divss($dst$$XMMRegister, $src$$XMMRegister); |
10088 %} | |
10686 ins_pipe(pipe_slow); | 10089 ins_pipe(pipe_slow); |
10687 %} | 10090 %} |
10688 | 10091 |
10689 instruct divF_mem(regF dst, memory src) | 10092 instruct divF_mem(regF dst, memory src) |
10690 %{ | 10093 %{ |
10691 match(Set dst (DivF dst (LoadF src))); | 10094 match(Set dst (DivF dst (LoadF src))); |
10692 | 10095 |
10693 format %{ "divss $dst, $src" %} | 10096 format %{ "divss $dst, $src" %} |
10694 ins_cost(150); // XXX | 10097 ins_cost(150); // XXX |
10695 opcode(0xF3, 0x0F, 0x5E); | 10098 ins_encode %{ |
10696 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 10099 __ divss($dst$$XMMRegister, $src$$Address); |
10100 %} | |
10697 ins_pipe(pipe_slow); | 10101 ins_pipe(pipe_slow); |
10698 %} | 10102 %} |
10699 | 10103 |
10700 instruct divF_imm(regF dst, immF con) %{ | 10104 instruct divF_imm(regF dst, immF con) %{ |
10701 match(Set dst (DivF dst con)); | 10105 match(Set dst (DivF dst con)); |
10711 %{ | 10115 %{ |
10712 match(Set dst (DivD dst src)); | 10116 match(Set dst (DivD dst src)); |
10713 | 10117 |
10714 format %{ "divsd $dst, $src" %} | 10118 format %{ "divsd $dst, $src" %} |
10715 ins_cost(150); // XXX | 10119 ins_cost(150); // XXX |
10716 opcode(0xF2, 0x0F, 0x5E); | 10120 ins_encode %{ |
10717 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 10121 __ divsd($dst$$XMMRegister, $src$$XMMRegister); |
10122 %} | |
10718 ins_pipe(pipe_slow); | 10123 ins_pipe(pipe_slow); |
10719 %} | 10124 %} |
10720 | 10125 |
10721 instruct divD_mem(regD dst, memory src) | 10126 instruct divD_mem(regD dst, memory src) |
10722 %{ | 10127 %{ |
10723 match(Set dst (DivD dst (LoadD src))); | 10128 match(Set dst (DivD dst (LoadD src))); |
10724 | 10129 |
10725 format %{ "divsd $dst, $src" %} | 10130 format %{ "divsd $dst, $src" %} |
10726 ins_cost(150); // XXX | 10131 ins_cost(150); // XXX |
10727 opcode(0xF2, 0x0F, 0x5E); | 10132 ins_encode %{ |
10728 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 10133 __ divsd($dst$$XMMRegister, $src$$Address); |
10134 %} | |
10729 ins_pipe(pipe_slow); | 10135 ins_pipe(pipe_slow); |
10730 %} | 10136 %} |
10731 | 10137 |
10732 instruct divD_imm(regD dst, immD con) %{ | 10138 instruct divD_imm(regD dst, immD con) %{ |
10733 match(Set dst (DivD dst con)); | 10139 match(Set dst (DivD dst con)); |
10743 %{ | 10149 %{ |
10744 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | 10150 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); |
10745 | 10151 |
10746 format %{ "sqrtss $dst, $src" %} | 10152 format %{ "sqrtss $dst, $src" %} |
10747 ins_cost(150); // XXX | 10153 ins_cost(150); // XXX |
10748 opcode(0xF3, 0x0F, 0x51); | 10154 ins_encode %{ |
10749 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 10155 __ sqrtss($dst$$XMMRegister, $src$$XMMRegister); |
10156 %} | |
10750 ins_pipe(pipe_slow); | 10157 ins_pipe(pipe_slow); |
10751 %} | 10158 %} |
10752 | 10159 |
10753 instruct sqrtF_mem(regF dst, memory src) | 10160 instruct sqrtF_mem(regF dst, memory src) |
10754 %{ | 10161 %{ |
10755 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src))))); | 10162 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src))))); |
10756 | 10163 |
10757 format %{ "sqrtss $dst, $src" %} | 10164 format %{ "sqrtss $dst, $src" %} |
10758 ins_cost(150); // XXX | 10165 ins_cost(150); // XXX |
10759 opcode(0xF3, 0x0F, 0x51); | 10166 ins_encode %{ |
10760 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 10167 __ sqrtss($dst$$XMMRegister, $src$$Address); |
10168 %} | |
10761 ins_pipe(pipe_slow); | 10169 ins_pipe(pipe_slow); |
10762 %} | 10170 %} |
10763 | 10171 |
10764 instruct sqrtF_imm(regF dst, immF con) %{ | 10172 instruct sqrtF_imm(regF dst, immF con) %{ |
10765 match(Set dst (ConvD2F (SqrtD (ConvF2D con)))); | 10173 match(Set dst (ConvD2F (SqrtD (ConvF2D con)))); |
10775 %{ | 10183 %{ |
10776 match(Set dst (SqrtD src)); | 10184 match(Set dst (SqrtD src)); |
10777 | 10185 |
10778 format %{ "sqrtsd $dst, $src" %} | 10186 format %{ "sqrtsd $dst, $src" %} |
10779 ins_cost(150); // XXX | 10187 ins_cost(150); // XXX |
10780 opcode(0xF2, 0x0F, 0x51); | 10188 ins_encode %{ |
10781 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 10189 __ sqrtsd($dst$$XMMRegister, $src$$XMMRegister); |
10190 %} | |
10782 ins_pipe(pipe_slow); | 10191 ins_pipe(pipe_slow); |
10783 %} | 10192 %} |
10784 | 10193 |
10785 instruct sqrtD_mem(regD dst, memory src) | 10194 instruct sqrtD_mem(regD dst, memory src) |
10786 %{ | 10195 %{ |
10787 match(Set dst (SqrtD (LoadD src))); | 10196 match(Set dst (SqrtD (LoadD src))); |
10788 | 10197 |
10789 format %{ "sqrtsd $dst, $src" %} | 10198 format %{ "sqrtsd $dst, $src" %} |
10790 ins_cost(150); // XXX | 10199 ins_cost(150); // XXX |
10791 opcode(0xF2, 0x0F, 0x51); | 10200 ins_encode %{ |
10792 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 10201 __ sqrtsd($dst$$XMMRegister, $src$$Address); |
10202 %} | |
10793 ins_pipe(pipe_slow); | 10203 ins_pipe(pipe_slow); |
10794 %} | 10204 %} |
10795 | 10205 |
10796 instruct sqrtD_imm(regD dst, immD con) %{ | 10206 instruct sqrtD_imm(regD dst, immD con) %{ |
10797 match(Set dst (SqrtD con)); | 10207 match(Set dst (SqrtD con)); |
10804 %} | 10214 %} |
10805 | 10215 |
10806 instruct absF_reg(regF dst) | 10216 instruct absF_reg(regF dst) |
10807 %{ | 10217 %{ |
10808 match(Set dst (AbsF dst)); | 10218 match(Set dst (AbsF dst)); |
10809 | 10219 ins_cost(150); // XXX |
10810 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %} | 10220 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %} |
10811 ins_encode(absF_encoding(dst)); | 10221 ins_encode %{ |
10222 __ andps($dst$$XMMRegister, | |
10223 ExternalAddress((address) StubRoutines::x86::float_sign_mask())); | |
10224 %} | |
10812 ins_pipe(pipe_slow); | 10225 ins_pipe(pipe_slow); |
10813 %} | 10226 %} |
10814 | 10227 |
10815 instruct absD_reg(regD dst) | 10228 instruct absD_reg(regD dst) |
10816 %{ | 10229 %{ |
10817 match(Set dst (AbsD dst)); | 10230 match(Set dst (AbsD dst)); |
10818 | 10231 ins_cost(150); // XXX |
10819 format %{ "andpd $dst, [0x7fffffffffffffff]\t" | 10232 format %{ "andpd $dst, [0x7fffffffffffffff]\t" |
10820 "# abs double by sign masking" %} | 10233 "# abs double by sign masking" %} |
10821 ins_encode(absD_encoding(dst)); | 10234 ins_encode %{ |
10235 __ andpd($dst$$XMMRegister, | |
10236 ExternalAddress((address) StubRoutines::x86::double_sign_mask())); | |
10237 %} | |
10822 ins_pipe(pipe_slow); | 10238 ins_pipe(pipe_slow); |
10823 %} | 10239 %} |
10824 | 10240 |
10825 instruct negF_reg(regF dst) | 10241 instruct negF_reg(regF dst) |
10826 %{ | 10242 %{ |
10827 match(Set dst (NegF dst)); | 10243 match(Set dst (NegF dst)); |
10828 | 10244 ins_cost(150); // XXX |
10829 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %} | 10245 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %} |
10830 ins_encode(negF_encoding(dst)); | 10246 ins_encode %{ |
10247 __ xorps($dst$$XMMRegister, | |
10248 ExternalAddress((address) StubRoutines::x86::float_sign_flip())); | |
10249 %} | |
10831 ins_pipe(pipe_slow); | 10250 ins_pipe(pipe_slow); |
10832 %} | 10251 %} |
10833 | 10252 |
10834 instruct negD_reg(regD dst) | 10253 instruct negD_reg(regD dst) |
10835 %{ | 10254 %{ |
10836 match(Set dst (NegD dst)); | 10255 match(Set dst (NegD dst)); |
10837 | 10256 ins_cost(150); // XXX |
10838 format %{ "xorpd $dst, [0x8000000000000000]\t" | 10257 format %{ "xorpd $dst, [0x8000000000000000]\t" |
10839 "# neg double by sign flipping" %} | 10258 "# neg double by sign flipping" %} |
10840 ins_encode(negD_encoding(dst)); | 10259 ins_encode %{ |
10260 __ xorpd($dst$$XMMRegister, | |
10261 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
10262 %} | |
10841 ins_pipe(pipe_slow); | 10263 ins_pipe(pipe_slow); |
10842 %} | 10264 %} |
10843 | 10265 |
10844 // -----------Trig and Trancendental Instructions------------------------------ | 10266 // -----------Trig and Trancendental Instructions------------------------------ |
10845 instruct cosD_reg(regD dst) %{ | 10267 instruct cosD_reg(regD dst) %{ |
10927 instruct convF2D_reg_reg(regD dst, regF src) | 10349 instruct convF2D_reg_reg(regD dst, regF src) |
10928 %{ | 10350 %{ |
10929 match(Set dst (ConvF2D src)); | 10351 match(Set dst (ConvF2D src)); |
10930 | 10352 |
10931 format %{ "cvtss2sd $dst, $src" %} | 10353 format %{ "cvtss2sd $dst, $src" %} |
10932 opcode(0xF3, 0x0F, 0x5A); | 10354 ins_encode %{ |
10933 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 10355 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); |
10356 %} | |
10934 ins_pipe(pipe_slow); // XXX | 10357 ins_pipe(pipe_slow); // XXX |
10935 %} | 10358 %} |
10936 | 10359 |
10937 instruct convF2D_reg_mem(regD dst, memory src) | 10360 instruct convF2D_reg_mem(regD dst, memory src) |
10938 %{ | 10361 %{ |
10939 match(Set dst (ConvF2D (LoadF src))); | 10362 match(Set dst (ConvF2D (LoadF src))); |
10940 | 10363 |
10941 format %{ "cvtss2sd $dst, $src" %} | 10364 format %{ "cvtss2sd $dst, $src" %} |
10942 opcode(0xF3, 0x0F, 0x5A); | 10365 ins_encode %{ |
10943 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 10366 __ cvtss2sd ($dst$$XMMRegister, $src$$Address); |
10367 %} | |
10944 ins_pipe(pipe_slow); // XXX | 10368 ins_pipe(pipe_slow); // XXX |
10945 %} | 10369 %} |
10946 | 10370 |
10947 instruct convD2F_reg_reg(regF dst, regD src) | 10371 instruct convD2F_reg_reg(regF dst, regD src) |
10948 %{ | 10372 %{ |
10949 match(Set dst (ConvD2F src)); | 10373 match(Set dst (ConvD2F src)); |
10950 | 10374 |
10951 format %{ "cvtsd2ss $dst, $src" %} | 10375 format %{ "cvtsd2ss $dst, $src" %} |
10952 opcode(0xF2, 0x0F, 0x5A); | 10376 ins_encode %{ |
10953 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 10377 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); |
10378 %} | |
10954 ins_pipe(pipe_slow); // XXX | 10379 ins_pipe(pipe_slow); // XXX |
10955 %} | 10380 %} |
10956 | 10381 |
10957 instruct convD2F_reg_mem(regF dst, memory src) | 10382 instruct convD2F_reg_mem(regF dst, memory src) |
10958 %{ | 10383 %{ |
10959 match(Set dst (ConvD2F (LoadD src))); | 10384 match(Set dst (ConvD2F (LoadD src))); |
10960 | 10385 |
10961 format %{ "cvtsd2ss $dst, $src" %} | 10386 format %{ "cvtsd2ss $dst, $src" %} |
10962 opcode(0xF2, 0x0F, 0x5A); | 10387 ins_encode %{ |
10963 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 10388 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address); |
10389 %} | |
10964 ins_pipe(pipe_slow); // XXX | 10390 ins_pipe(pipe_slow); // XXX |
10965 %} | 10391 %} |
10966 | 10392 |
10967 // XXX do mem variants | 10393 // XXX do mem variants |
10968 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) | 10394 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) |
10976 "subq rsp, #8\n\t" | 10402 "subq rsp, #8\n\t" |
10977 "movss [rsp], $src\n\t" | 10403 "movss [rsp], $src\n\t" |
10978 "call f2i_fixup\n\t" | 10404 "call f2i_fixup\n\t" |
10979 "popq $dst\n" | 10405 "popq $dst\n" |
10980 "done: "%} | 10406 "done: "%} |
10981 opcode(0xF3, 0x0F, 0x2C); | 10407 ins_encode %{ |
10982 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src), | 10408 Label done; |
10983 f2i_fixup(dst, src)); | 10409 __ cvttss2sil($dst$$Register, $src$$XMMRegister); |
10410 __ cmpl($dst$$Register, 0x80000000); | |
10411 __ jccb(Assembler::notEqual, done); | |
10412 __ subptr(rsp, 8); | |
10413 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
10414 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup()))); | |
10415 __ pop($dst$$Register); | |
10416 __ bind(done); | |
10417 %} | |
10984 ins_pipe(pipe_slow); | 10418 ins_pipe(pipe_slow); |
10985 %} | 10419 %} |
10986 | 10420 |
10987 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) | 10421 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) |
10988 %{ | 10422 %{ |
10995 "subq rsp, #8\n\t" | 10429 "subq rsp, #8\n\t" |
10996 "movss [rsp], $src\n\t" | 10430 "movss [rsp], $src\n\t" |
10997 "call f2l_fixup\n\t" | 10431 "call f2l_fixup\n\t" |
10998 "popq $dst\n" | 10432 "popq $dst\n" |
10999 "done: "%} | 10433 "done: "%} |
11000 opcode(0xF3, 0x0F, 0x2C); | 10434 ins_encode %{ |
11001 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src), | 10435 Label done; |
11002 f2l_fixup(dst, src)); | 10436 __ cvttss2siq($dst$$Register, $src$$XMMRegister); |
10437 __ cmp64($dst$$Register, | |
10438 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
10439 __ jccb(Assembler::notEqual, done); | |
10440 __ subptr(rsp, 8); | |
10441 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
10442 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup()))); | |
10443 __ pop($dst$$Register); | |
10444 __ bind(done); | |
10445 %} | |
11003 ins_pipe(pipe_slow); | 10446 ins_pipe(pipe_slow); |
11004 %} | 10447 %} |
11005 | 10448 |
11006 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) | 10449 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) |
11007 %{ | 10450 %{ |
11014 "subq rsp, #8\n\t" | 10457 "subq rsp, #8\n\t" |
11015 "movsd [rsp], $src\n\t" | 10458 "movsd [rsp], $src\n\t" |
11016 "call d2i_fixup\n\t" | 10459 "call d2i_fixup\n\t" |
11017 "popq $dst\n" | 10460 "popq $dst\n" |
11018 "done: "%} | 10461 "done: "%} |
11019 opcode(0xF2, 0x0F, 0x2C); | 10462 ins_encode %{ |
11020 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src), | 10463 Label done; |
11021 d2i_fixup(dst, src)); | 10464 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); |
10465 __ cmpl($dst$$Register, 0x80000000); | |
10466 __ jccb(Assembler::notEqual, done); | |
10467 __ subptr(rsp, 8); | |
10468 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
10469 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup()))); | |
10470 __ pop($dst$$Register); | |
10471 __ bind(done); | |
10472 %} | |
11022 ins_pipe(pipe_slow); | 10473 ins_pipe(pipe_slow); |
11023 %} | 10474 %} |
11024 | 10475 |
11025 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) | 10476 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) |
11026 %{ | 10477 %{ |
11033 "subq rsp, #8\n\t" | 10484 "subq rsp, #8\n\t" |
11034 "movsd [rsp], $src\n\t" | 10485 "movsd [rsp], $src\n\t" |
11035 "call d2l_fixup\n\t" | 10486 "call d2l_fixup\n\t" |
11036 "popq $dst\n" | 10487 "popq $dst\n" |
11037 "done: "%} | 10488 "done: "%} |
11038 opcode(0xF2, 0x0F, 0x2C); | 10489 ins_encode %{ |
11039 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src), | 10490 Label done; |
11040 d2l_fixup(dst, src)); | 10491 __ cvttsd2siq($dst$$Register, $src$$XMMRegister); |
10492 __ cmp64($dst$$Register, | |
10493 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
10494 __ jccb(Assembler::notEqual, done); | |
10495 __ subptr(rsp, 8); | |
10496 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
10497 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup()))); | |
10498 __ pop($dst$$Register); | |
10499 __ bind(done); | |
10500 %} | |
11041 ins_pipe(pipe_slow); | 10501 ins_pipe(pipe_slow); |
11042 %} | 10502 %} |
11043 | 10503 |
11044 instruct convI2F_reg_reg(regF dst, rRegI src) | 10504 instruct convI2F_reg_reg(regF dst, rRegI src) |
11045 %{ | 10505 %{ |
11046 predicate(!UseXmmI2F); | 10506 predicate(!UseXmmI2F); |
11047 match(Set dst (ConvI2F src)); | 10507 match(Set dst (ConvI2F src)); |
11048 | 10508 |
11049 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | 10509 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} |
11050 opcode(0xF3, 0x0F, 0x2A); | 10510 ins_encode %{ |
11051 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 10511 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); |
10512 %} | |
11052 ins_pipe(pipe_slow); // XXX | 10513 ins_pipe(pipe_slow); // XXX |
11053 %} | 10514 %} |
11054 | 10515 |
11055 instruct convI2F_reg_mem(regF dst, memory src) | 10516 instruct convI2F_reg_mem(regF dst, memory src) |
11056 %{ | 10517 %{ |
11057 match(Set dst (ConvI2F (LoadI src))); | 10518 match(Set dst (ConvI2F (LoadI src))); |
11058 | 10519 |
11059 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | 10520 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} |
11060 opcode(0xF3, 0x0F, 0x2A); | 10521 ins_encode %{ |
11061 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 10522 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address); |
10523 %} | |
11062 ins_pipe(pipe_slow); // XXX | 10524 ins_pipe(pipe_slow); // XXX |
11063 %} | 10525 %} |
11064 | 10526 |
11065 instruct convI2D_reg_reg(regD dst, rRegI src) | 10527 instruct convI2D_reg_reg(regD dst, rRegI src) |
11066 %{ | 10528 %{ |
11067 predicate(!UseXmmI2D); | 10529 predicate(!UseXmmI2D); |
11068 match(Set dst (ConvI2D src)); | 10530 match(Set dst (ConvI2D src)); |
11069 | 10531 |
11070 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | 10532 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} |
11071 opcode(0xF2, 0x0F, 0x2A); | 10533 ins_encode %{ |
11072 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 10534 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); |
10535 %} | |
11073 ins_pipe(pipe_slow); // XXX | 10536 ins_pipe(pipe_slow); // XXX |
11074 %} | 10537 %} |
11075 | 10538 |
11076 instruct convI2D_reg_mem(regD dst, memory src) | 10539 instruct convI2D_reg_mem(regD dst, memory src) |
11077 %{ | 10540 %{ |
11078 match(Set dst (ConvI2D (LoadI src))); | 10541 match(Set dst (ConvI2D (LoadI src))); |
11079 | 10542 |
11080 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | 10543 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} |
11081 opcode(0xF2, 0x0F, 0x2A); | 10544 ins_encode %{ |
11082 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 10545 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address); |
10546 %} | |
11083 ins_pipe(pipe_slow); // XXX | 10547 ins_pipe(pipe_slow); // XXX |
11084 %} | 10548 %} |
11085 | 10549 |
11086 instruct convXI2F_reg(regF dst, rRegI src) | 10550 instruct convXI2F_reg(regF dst, rRegI src) |
11087 %{ | 10551 %{ |
11114 instruct convL2F_reg_reg(regF dst, rRegL src) | 10578 instruct convL2F_reg_reg(regF dst, rRegL src) |
11115 %{ | 10579 %{ |
11116 match(Set dst (ConvL2F src)); | 10580 match(Set dst (ConvL2F src)); |
11117 | 10581 |
11118 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | 10582 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} |
11119 opcode(0xF3, 0x0F, 0x2A); | 10583 ins_encode %{ |
11120 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 10584 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register); |
10585 %} | |
11121 ins_pipe(pipe_slow); // XXX | 10586 ins_pipe(pipe_slow); // XXX |
11122 %} | 10587 %} |
11123 | 10588 |
11124 instruct convL2F_reg_mem(regF dst, memory src) | 10589 instruct convL2F_reg_mem(regF dst, memory src) |
11125 %{ | 10590 %{ |
11126 match(Set dst (ConvL2F (LoadL src))); | 10591 match(Set dst (ConvL2F (LoadL src))); |
11127 | 10592 |
11128 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | 10593 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} |
11129 opcode(0xF3, 0x0F, 0x2A); | 10594 ins_encode %{ |
11130 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 10595 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address); |
10596 %} | |
11131 ins_pipe(pipe_slow); // XXX | 10597 ins_pipe(pipe_slow); // XXX |
11132 %} | 10598 %} |
11133 | 10599 |
11134 instruct convL2D_reg_reg(regD dst, rRegL src) | 10600 instruct convL2D_reg_reg(regD dst, rRegL src) |
11135 %{ | 10601 %{ |
11136 match(Set dst (ConvL2D src)); | 10602 match(Set dst (ConvL2D src)); |
11137 | 10603 |
11138 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | 10604 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} |
11139 opcode(0xF2, 0x0F, 0x2A); | 10605 ins_encode %{ |
11140 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src)); | 10606 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register); |
10607 %} | |
11141 ins_pipe(pipe_slow); // XXX | 10608 ins_pipe(pipe_slow); // XXX |
11142 %} | 10609 %} |
11143 | 10610 |
11144 instruct convL2D_reg_mem(regD dst, memory src) | 10611 instruct convL2D_reg_mem(regD dst, memory src) |
11145 %{ | 10612 %{ |
11146 match(Set dst (ConvL2D (LoadL src))); | 10613 match(Set dst (ConvL2D (LoadL src))); |
11147 | 10614 |
11148 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | 10615 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} |
11149 opcode(0xF2, 0x0F, 0x2A); | 10616 ins_encode %{ |
11150 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 10617 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address); |
10618 %} | |
11151 ins_pipe(pipe_slow); // XXX | 10619 ins_pipe(pipe_slow); // XXX |
11152 %} | 10620 %} |
11153 | 10621 |
11154 instruct convI2L_reg_reg(rRegL dst, rRegI src) | 10622 instruct convI2L_reg_reg(rRegL dst, rRegI src) |
11155 %{ | 10623 %{ |
11184 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) | 10652 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) |
11185 %{ | 10653 %{ |
11186 match(Set dst (AndL (ConvI2L src) mask)); | 10654 match(Set dst (AndL (ConvI2L src) mask)); |
11187 | 10655 |
11188 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | 10656 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} |
11189 ins_encode(enc_copy(dst, src)); | 10657 ins_encode %{ |
10658 if ($dst$$reg != $src$$reg) { | |
10659 __ movl($dst$$Register, $src$$Register); | |
10660 } | |
10661 %} | |
11190 ins_pipe(ialu_reg_reg); | 10662 ins_pipe(ialu_reg_reg); |
11191 %} | 10663 %} |
11192 | 10664 |
11193 // Zero-extend convert int to long | 10665 // Zero-extend convert int to long |
11194 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) | 10666 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) |
11195 %{ | 10667 %{ |
11196 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); | 10668 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); |
11197 | 10669 |
11198 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | 10670 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} |
11199 opcode(0x8B); | 10671 ins_encode %{ |
11200 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | 10672 __ movl($dst$$Register, $src$$Address); |
10673 %} | |
11201 ins_pipe(ialu_reg_mem); | 10674 ins_pipe(ialu_reg_mem); |
11202 %} | 10675 %} |
11203 | 10676 |
11204 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) | 10677 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) |
11205 %{ | 10678 %{ |
11206 match(Set dst (AndL src mask)); | 10679 match(Set dst (AndL src mask)); |
11207 | 10680 |
11208 format %{ "movl $dst, $src\t# zero-extend long" %} | 10681 format %{ "movl $dst, $src\t# zero-extend long" %} |
11209 ins_encode(enc_copy_always(dst, src)); | 10682 ins_encode %{ |
10683 __ movl($dst$$Register, $src$$Register); | |
10684 %} | |
11210 ins_pipe(ialu_reg_reg); | 10685 ins_pipe(ialu_reg_reg); |
11211 %} | 10686 %} |
11212 | 10687 |
11213 instruct convL2I_reg_reg(rRegI dst, rRegL src) | 10688 instruct convL2I_reg_reg(rRegI dst, rRegL src) |
11214 %{ | 10689 %{ |
11215 match(Set dst (ConvL2I src)); | 10690 match(Set dst (ConvL2I src)); |
11216 | 10691 |
11217 format %{ "movl $dst, $src\t# l2i" %} | 10692 format %{ "movl $dst, $src\t# l2i" %} |
11218 ins_encode(enc_copy_always(dst, src)); | 10693 ins_encode %{ |
10694 __ movl($dst$$Register, $src$$Register); | |
10695 %} | |
11219 ins_pipe(ialu_reg_reg); | 10696 ins_pipe(ialu_reg_reg); |
11220 %} | 10697 %} |
11221 | 10698 |
11222 | 10699 |
11223 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ | 10700 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ |
11224 match(Set dst (MoveF2I src)); | 10701 match(Set dst (MoveF2I src)); |
11225 effect(DEF dst, USE src); | 10702 effect(DEF dst, USE src); |
11226 | 10703 |
11227 ins_cost(125); | 10704 ins_cost(125); |
11228 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} | 10705 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} |
11229 opcode(0x8B); | 10706 ins_encode %{ |
11230 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | 10707 __ movl($dst$$Register, Address(rsp, $src$$disp)); |
10708 %} | |
11231 ins_pipe(ialu_reg_mem); | 10709 ins_pipe(ialu_reg_mem); |
11232 %} | 10710 %} |
11233 | 10711 |
11234 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | 10712 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ |
11235 match(Set dst (MoveI2F src)); | 10713 match(Set dst (MoveI2F src)); |
11236 effect(DEF dst, USE src); | 10714 effect(DEF dst, USE src); |
11237 | 10715 |
11238 ins_cost(125); | 10716 ins_cost(125); |
11239 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} | 10717 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} |
11240 opcode(0xF3, 0x0F, 0x10); | 10718 ins_encode %{ |
11241 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 10719 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); |
10720 %} | |
11242 ins_pipe(pipe_slow); | 10721 ins_pipe(pipe_slow); |
11243 %} | 10722 %} |
11244 | 10723 |
11245 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ | 10724 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ |
11246 match(Set dst (MoveD2L src)); | 10725 match(Set dst (MoveD2L src)); |
11247 effect(DEF dst, USE src); | 10726 effect(DEF dst, USE src); |
11248 | 10727 |
11249 ins_cost(125); | 10728 ins_cost(125); |
11250 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} | 10729 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} |
11251 opcode(0x8B); | 10730 ins_encode %{ |
11252 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | 10731 __ movq($dst$$Register, Address(rsp, $src$$disp)); |
10732 %} | |
11253 ins_pipe(ialu_reg_mem); | 10733 ins_pipe(ialu_reg_mem); |
11254 %} | 10734 %} |
11255 | 10735 |
11256 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ | 10736 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ |
11257 predicate(!UseXmmLoadAndClearUpper); | 10737 predicate(!UseXmmLoadAndClearUpper); |
11258 match(Set dst (MoveL2D src)); | 10738 match(Set dst (MoveL2D src)); |
11259 effect(DEF dst, USE src); | 10739 effect(DEF dst, USE src); |
11260 | 10740 |
11261 ins_cost(125); | 10741 ins_cost(125); |
11262 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} | 10742 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} |
11263 opcode(0x66, 0x0F, 0x12); | 10743 ins_encode %{ |
11264 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 10744 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); |
10745 %} | |
11265 ins_pipe(pipe_slow); | 10746 ins_pipe(pipe_slow); |
11266 %} | 10747 %} |
11267 | 10748 |
11268 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | 10749 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ |
11269 predicate(UseXmmLoadAndClearUpper); | 10750 predicate(UseXmmLoadAndClearUpper); |
11270 match(Set dst (MoveL2D src)); | 10751 match(Set dst (MoveL2D src)); |
11271 effect(DEF dst, USE src); | 10752 effect(DEF dst, USE src); |
11272 | 10753 |
11273 ins_cost(125); | 10754 ins_cost(125); |
11274 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} | 10755 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} |
11275 opcode(0xF2, 0x0F, 0x10); | 10756 ins_encode %{ |
11276 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | 10757 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); |
10758 %} | |
11277 ins_pipe(pipe_slow); | 10759 ins_pipe(pipe_slow); |
11278 %} | 10760 %} |
11279 | 10761 |
11280 | 10762 |
11281 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | 10763 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ |
11282 match(Set dst (MoveF2I src)); | 10764 match(Set dst (MoveF2I src)); |
11283 effect(DEF dst, USE src); | 10765 effect(DEF dst, USE src); |
11284 | 10766 |
11285 ins_cost(95); // XXX | 10767 ins_cost(95); // XXX |
11286 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} | 10768 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} |
11287 opcode(0xF3, 0x0F, 0x11); | 10769 ins_encode %{ |
11288 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | 10770 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); |
10771 %} | |
11289 ins_pipe(pipe_slow); | 10772 ins_pipe(pipe_slow); |
11290 %} | 10773 %} |
11291 | 10774 |
11292 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ | 10775 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ |
11293 match(Set dst (MoveI2F src)); | 10776 match(Set dst (MoveI2F src)); |
11294 effect(DEF dst, USE src); | 10777 effect(DEF dst, USE src); |
11295 | 10778 |
11296 ins_cost(100); | 10779 ins_cost(100); |
11297 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} | 10780 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} |
11298 opcode(0x89); | 10781 ins_encode %{ |
11299 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | 10782 __ movl(Address(rsp, $dst$$disp), $src$$Register); |
10783 %} | |
11300 ins_pipe( ialu_mem_reg ); | 10784 ins_pipe( ialu_mem_reg ); |
11301 %} | 10785 %} |
11302 | 10786 |
11303 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | 10787 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ |
11304 match(Set dst (MoveD2L src)); | 10788 match(Set dst (MoveD2L src)); |
11305 effect(DEF dst, USE src); | 10789 effect(DEF dst, USE src); |
11306 | 10790 |
11307 ins_cost(95); // XXX | 10791 ins_cost(95); // XXX |
11308 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} | 10792 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} |
11309 opcode(0xF2, 0x0F, 0x11); | 10793 ins_encode %{ |
11310 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | 10794 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); |
10795 %} | |
11311 ins_pipe(pipe_slow); | 10796 ins_pipe(pipe_slow); |
11312 %} | 10797 %} |
11313 | 10798 |
11314 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ | 10799 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ |
11315 match(Set dst (MoveL2D src)); | 10800 match(Set dst (MoveL2D src)); |
11316 effect(DEF dst, USE src); | 10801 effect(DEF dst, USE src); |
11317 | 10802 |
11318 ins_cost(100); | 10803 ins_cost(100); |
11319 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} | 10804 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} |
11320 opcode(0x89); | 10805 ins_encode %{ |
11321 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | 10806 __ movq(Address(rsp, $dst$$disp), $src$$Register); |
10807 %} | |
11322 ins_pipe(ialu_mem_reg); | 10808 ins_pipe(ialu_mem_reg); |
11323 %} | 10809 %} |
11324 | 10810 |
11325 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ | 10811 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ |
11326 match(Set dst (MoveF2I src)); | 10812 match(Set dst (MoveF2I src)); |
11327 effect(DEF dst, USE src); | 10813 effect(DEF dst, USE src); |
11328 ins_cost(85); | 10814 ins_cost(85); |
11329 format %{ "movd $dst,$src\t# MoveF2I" %} | 10815 format %{ "movd $dst,$src\t# MoveF2I" %} |
11330 ins_encode %{ __ movdl($dst$$Register, $src$$XMMRegister); %} | 10816 ins_encode %{ |
10817 __ movdl($dst$$Register, $src$$XMMRegister); | |
10818 %} | |
11331 ins_pipe( pipe_slow ); | 10819 ins_pipe( pipe_slow ); |
11332 %} | 10820 %} |
11333 | 10821 |
11334 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ | 10822 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ |
11335 match(Set dst (MoveD2L src)); | 10823 match(Set dst (MoveD2L src)); |
11336 effect(DEF dst, USE src); | 10824 effect(DEF dst, USE src); |
11337 ins_cost(85); | 10825 ins_cost(85); |
11338 format %{ "movd $dst,$src\t# MoveD2L" %} | 10826 format %{ "movd $dst,$src\t# MoveD2L" %} |
11339 ins_encode %{ __ movdq($dst$$Register, $src$$XMMRegister); %} | 10827 ins_encode %{ |
10828 __ movdq($dst$$Register, $src$$XMMRegister); | |
10829 %} | |
11340 ins_pipe( pipe_slow ); | 10830 ins_pipe( pipe_slow ); |
11341 %} | 10831 %} |
11342 | 10832 |
11343 // The next instructions have long latency and use Int unit. Set high cost. | 10833 // The next instructions have long latency and use Int unit. Set high cost. |
11344 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ | 10834 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ |
11345 match(Set dst (MoveI2F src)); | 10835 match(Set dst (MoveI2F src)); |
11346 effect(DEF dst, USE src); | 10836 effect(DEF dst, USE src); |
11347 ins_cost(300); | 10837 ins_cost(300); |
11348 format %{ "movd $dst,$src\t# MoveI2F" %} | 10838 format %{ "movd $dst,$src\t# MoveI2F" %} |
11349 ins_encode %{ __ movdl($dst$$XMMRegister, $src$$Register); %} | 10839 ins_encode %{ |
10840 __ movdl($dst$$XMMRegister, $src$$Register); | |
10841 %} | |
11350 ins_pipe( pipe_slow ); | 10842 ins_pipe( pipe_slow ); |
11351 %} | 10843 %} |
11352 | 10844 |
11353 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ | 10845 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ |
11354 match(Set dst (MoveL2D src)); | 10846 match(Set dst (MoveL2D src)); |
11355 effect(DEF dst, USE src); | 10847 effect(DEF dst, USE src); |
11356 ins_cost(300); | 10848 ins_cost(300); |
11357 format %{ "movd $dst,$src\t# MoveL2D" %} | 10849 format %{ "movd $dst,$src\t# MoveL2D" %} |
11358 ins_encode %{ __ movdq($dst$$XMMRegister, $src$$Register); %} | 10850 ins_encode %{ |
10851 __ movdq($dst$$XMMRegister, $src$$Register); | |
10852 %} | |
11359 ins_pipe( pipe_slow ); | 10853 ins_pipe( pipe_slow ); |
11360 %} | 10854 %} |
11361 | 10855 |
11362 // Replicate scalar to packed byte (1 byte) values in xmm | 10856 // Replicate scalar to packed byte (1 byte) values in xmm |
11363 instruct Repl8B_reg(regD dst, regD src) %{ | 10857 instruct Repl8B_reg(regD dst, regD src) %{ |
11364 match(Set dst (Replicate8B src)); | 10858 match(Set dst (Replicate8B src)); |
11365 format %{ "MOVDQA $dst,$src\n\t" | 10859 format %{ "MOVDQA $dst,$src\n\t" |
11366 "PUNPCKLBW $dst,$dst\n\t" | 10860 "PUNPCKLBW $dst,$dst\n\t" |
11367 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | 10861 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} |
11368 ins_encode( pshufd_8x8(dst, src)); | 10862 ins_encode %{ |
10863 if ($dst$$reg != $src$$reg) { | |
10864 __ movdqa($dst$$XMMRegister, $src$$XMMRegister); | |
10865 } | |
10866 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); | |
10867 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
10868 %} | |
11369 ins_pipe( pipe_slow ); | 10869 ins_pipe( pipe_slow ); |
11370 %} | 10870 %} |
11371 | 10871 |
11372 // Replicate scalar to packed byte (1 byte) values in xmm | 10872 // Replicate scalar to packed byte (1 byte) values in xmm |
11373 instruct Repl8B_rRegI(regD dst, rRegI src) %{ | 10873 instruct Repl8B_rRegI(regD dst, rRegI src) %{ |
11374 match(Set dst (Replicate8B src)); | 10874 match(Set dst (Replicate8B src)); |
11375 format %{ "MOVD $dst,$src\n\t" | 10875 format %{ "MOVD $dst,$src\n\t" |
11376 "PUNPCKLBW $dst,$dst\n\t" | 10876 "PUNPCKLBW $dst,$dst\n\t" |
11377 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | 10877 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} |
11378 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst)); | 10878 ins_encode %{ |
10879 __ movdl($dst$$XMMRegister, $src$$Register); | |
10880 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); | |
10881 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
10882 %} | |
11379 ins_pipe( pipe_slow ); | 10883 ins_pipe( pipe_slow ); |
11380 %} | 10884 %} |
11381 | 10885 |
11382 // Replicate scalar zero to packed byte (1 byte) values in xmm | 10886 // Replicate scalar zero to packed byte (1 byte) values in xmm |
11383 instruct Repl8B_immI0(regD dst, immI0 zero) %{ | 10887 instruct Repl8B_immI0(regD dst, immI0 zero) %{ |
11384 match(Set dst (Replicate8B zero)); | 10888 match(Set dst (Replicate8B zero)); |
11385 format %{ "PXOR $dst,$dst\t! replicate8B" %} | 10889 format %{ "PXOR $dst,$dst\t! replicate8B" %} |
11386 ins_encode( pxor(dst, dst)); | 10890 ins_encode %{ |
10891 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
10892 %} | |
11387 ins_pipe( fpu_reg_reg ); | 10893 ins_pipe( fpu_reg_reg ); |
11388 %} | 10894 %} |
11389 | 10895 |
11390 // Replicate scalar to packed shore (2 byte) values in xmm | 10896 // Replicate scalar to packed shore (2 byte) values in xmm |
11391 instruct Repl4S_reg(regD dst, regD src) %{ | 10897 instruct Repl4S_reg(regD dst, regD src) %{ |
11392 match(Set dst (Replicate4S src)); | 10898 match(Set dst (Replicate4S src)); |
11393 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} | 10899 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} |
11394 ins_encode( pshufd_4x16(dst, src)); | 10900 ins_encode %{ |
10901 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00); | |
10902 %} | |
11395 ins_pipe( fpu_reg_reg ); | 10903 ins_pipe( fpu_reg_reg ); |
11396 %} | 10904 %} |
11397 | 10905 |
11398 // Replicate scalar to packed shore (2 byte) values in xmm | 10906 // Replicate scalar to packed shore (2 byte) values in xmm |
11399 instruct Repl4S_rRegI(regD dst, rRegI src) %{ | 10907 instruct Repl4S_rRegI(regD dst, rRegI src) %{ |
11400 match(Set dst (Replicate4S src)); | 10908 match(Set dst (Replicate4S src)); |
11401 format %{ "MOVD $dst,$src\n\t" | 10909 format %{ "MOVD $dst,$src\n\t" |
11402 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} | 10910 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} |
11403 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | 10911 ins_encode %{ |
10912 __ movdl($dst$$XMMRegister, $src$$Register); | |
10913 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
10914 %} | |
11404 ins_pipe( fpu_reg_reg ); | 10915 ins_pipe( fpu_reg_reg ); |
11405 %} | 10916 %} |
11406 | 10917 |
11407 // Replicate scalar zero to packed short (2 byte) values in xmm | 10918 // Replicate scalar zero to packed short (2 byte) values in xmm |
11408 instruct Repl4S_immI0(regD dst, immI0 zero) %{ | 10919 instruct Repl4S_immI0(regD dst, immI0 zero) %{ |
11409 match(Set dst (Replicate4S zero)); | 10920 match(Set dst (Replicate4S zero)); |
11410 format %{ "PXOR $dst,$dst\t! replicate4S" %} | 10921 format %{ "PXOR $dst,$dst\t! replicate4S" %} |
11411 ins_encode( pxor(dst, dst)); | 10922 ins_encode %{ |
10923 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
10924 %} | |
11412 ins_pipe( fpu_reg_reg ); | 10925 ins_pipe( fpu_reg_reg ); |
11413 %} | 10926 %} |
11414 | 10927 |
11415 // Replicate scalar to packed char (2 byte) values in xmm | 10928 // Replicate scalar to packed char (2 byte) values in xmm |
11416 instruct Repl4C_reg(regD dst, regD src) %{ | 10929 instruct Repl4C_reg(regD dst, regD src) %{ |
11417 match(Set dst (Replicate4C src)); | 10930 match(Set dst (Replicate4C src)); |
11418 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} | 10931 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} |
11419 ins_encode( pshufd_4x16(dst, src)); | 10932 ins_encode %{ |
10933 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00); | |
10934 %} | |
11420 ins_pipe( fpu_reg_reg ); | 10935 ins_pipe( fpu_reg_reg ); |
11421 %} | 10936 %} |
11422 | 10937 |
11423 // Replicate scalar to packed char (2 byte) values in xmm | 10938 // Replicate scalar to packed char (2 byte) values in xmm |
11424 instruct Repl4C_rRegI(regD dst, rRegI src) %{ | 10939 instruct Repl4C_rRegI(regD dst, rRegI src) %{ |
11425 match(Set dst (Replicate4C src)); | 10940 match(Set dst (Replicate4C src)); |
11426 format %{ "MOVD $dst,$src\n\t" | 10941 format %{ "MOVD $dst,$src\n\t" |
11427 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} | 10942 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} |
11428 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | 10943 ins_encode %{ |
10944 __ movdl($dst$$XMMRegister, $src$$Register); | |
10945 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
10946 %} | |
11429 ins_pipe( fpu_reg_reg ); | 10947 ins_pipe( fpu_reg_reg ); |
11430 %} | 10948 %} |
11431 | 10949 |
11432 // Replicate scalar zero to packed char (2 byte) values in xmm | 10950 // Replicate scalar zero to packed char (2 byte) values in xmm |
11433 instruct Repl4C_immI0(regD dst, immI0 zero) %{ | 10951 instruct Repl4C_immI0(regD dst, immI0 zero) %{ |
11434 match(Set dst (Replicate4C zero)); | 10952 match(Set dst (Replicate4C zero)); |
11435 format %{ "PXOR $dst,$dst\t! replicate4C" %} | 10953 format %{ "PXOR $dst,$dst\t! replicate4C" %} |
11436 ins_encode( pxor(dst, dst)); | 10954 ins_encode %{ |
10955 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
10956 %} | |
11437 ins_pipe( fpu_reg_reg ); | 10957 ins_pipe( fpu_reg_reg ); |
11438 %} | 10958 %} |
11439 | 10959 |
11440 // Replicate scalar to packed integer (4 byte) values in xmm | 10960 // Replicate scalar to packed integer (4 byte) values in xmm |
11441 instruct Repl2I_reg(regD dst, regD src) %{ | 10961 instruct Repl2I_reg(regD dst, regD src) %{ |
11442 match(Set dst (Replicate2I src)); | 10962 match(Set dst (Replicate2I src)); |
11443 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} | 10963 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} |
11444 ins_encode( pshufd(dst, src, 0x00)); | 10964 ins_encode %{ |
10965 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); | |
10966 %} | |
11445 ins_pipe( fpu_reg_reg ); | 10967 ins_pipe( fpu_reg_reg ); |
11446 %} | 10968 %} |
11447 | 10969 |
11448 // Replicate scalar to packed integer (4 byte) values in xmm | 10970 // Replicate scalar to packed integer (4 byte) values in xmm |
11449 instruct Repl2I_rRegI(regD dst, rRegI src) %{ | 10971 instruct Repl2I_rRegI(regD dst, rRegI src) %{ |
11450 match(Set dst (Replicate2I src)); | 10972 match(Set dst (Replicate2I src)); |
11451 format %{ "MOVD $dst,$src\n\t" | 10973 format %{ "MOVD $dst,$src\n\t" |
11452 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} | 10974 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} |
11453 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00)); | 10975 ins_encode %{ |
10976 __ movdl($dst$$XMMRegister, $src$$Register); | |
10977 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
10978 %} | |
11454 ins_pipe( fpu_reg_reg ); | 10979 ins_pipe( fpu_reg_reg ); |
11455 %} | 10980 %} |
11456 | 10981 |
11457 // Replicate scalar zero to packed integer (2 byte) values in xmm | 10982 // Replicate scalar zero to packed integer (2 byte) values in xmm |
11458 instruct Repl2I_immI0(regD dst, immI0 zero) %{ | 10983 instruct Repl2I_immI0(regD dst, immI0 zero) %{ |
11459 match(Set dst (Replicate2I zero)); | 10984 match(Set dst (Replicate2I zero)); |
11460 format %{ "PXOR $dst,$dst\t! replicate2I" %} | 10985 format %{ "PXOR $dst,$dst\t! replicate2I" %} |
11461 ins_encode( pxor(dst, dst)); | 10986 ins_encode %{ |
10987 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
10988 %} | |
11462 ins_pipe( fpu_reg_reg ); | 10989 ins_pipe( fpu_reg_reg ); |
11463 %} | 10990 %} |
11464 | 10991 |
11465 // Replicate scalar to packed single precision floating point values in xmm | 10992 // Replicate scalar to packed single precision floating point values in xmm |
11466 instruct Repl2F_reg(regD dst, regD src) %{ | 10993 instruct Repl2F_reg(regD dst, regD src) %{ |
11467 match(Set dst (Replicate2F src)); | 10994 match(Set dst (Replicate2F src)); |
11468 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | 10995 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} |
11469 ins_encode( pshufd(dst, src, 0xe0)); | 10996 ins_encode %{ |
10997 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0); | |
10998 %} | |
11470 ins_pipe( fpu_reg_reg ); | 10999 ins_pipe( fpu_reg_reg ); |
11471 %} | 11000 %} |
11472 | 11001 |
11473 // Replicate scalar to packed single precision floating point values in xmm | 11002 // Replicate scalar to packed single precision floating point values in xmm |
11474 instruct Repl2F_regF(regD dst, regF src) %{ | 11003 instruct Repl2F_regF(regD dst, regF src) %{ |
11475 match(Set dst (Replicate2F src)); | 11004 match(Set dst (Replicate2F src)); |
11476 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | 11005 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} |
11477 ins_encode( pshufd(dst, src, 0xe0)); | 11006 ins_encode %{ |
11007 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0); | |
11008 %} | |
11478 ins_pipe( fpu_reg_reg ); | 11009 ins_pipe( fpu_reg_reg ); |
11479 %} | 11010 %} |
11480 | 11011 |
11481 // Replicate scalar to packed single precision floating point values in xmm | 11012 // Replicate scalar to packed single precision floating point values in xmm |
11482 instruct Repl2F_immF0(regD dst, immF0 zero) %{ | 11013 instruct Repl2F_immF0(regD dst, immF0 zero) %{ |
11483 match(Set dst (Replicate2F zero)); | 11014 match(Set dst (Replicate2F zero)); |
11484 format %{ "PXOR $dst,$dst\t! replicate2F" %} | 11015 format %{ "PXOR $dst,$dst\t! replicate2F" %} |
11485 ins_encode( pxor(dst, dst)); | 11016 ins_encode %{ |
11017 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
11018 %} | |
11486 ins_pipe( fpu_reg_reg ); | 11019 ins_pipe( fpu_reg_reg ); |
11487 %} | 11020 %} |
11488 | 11021 |
11489 | 11022 |
11490 // ======================================================================= | 11023 // ======================================================================= |