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comparison src/cpu/x86/vm/vm_version_x86.hpp @ 2479:15c9a0e16269

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7035713: 3DNow Prefetch Instruction Support Summary: The upcoming processors from AMD are the first that support 3dnow prefetch without supporting the 3dnow instruction set. Reviewed-by: kvn Contributed-by: tom.deneau@amd.com
author kvn
date Mon, 11 Apr 2011 15:30:31 -0700
parents f95d63e2154a
children fe189d4a44e9 6ae7a1561b53
comparison
equal deleted inserted replaced
2478:328926869b15 2479:15c9a0e16269
186 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) 186 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
187 CPU_CMOV = (1 << 1), 187 CPU_CMOV = (1 << 1),
188 CPU_FXSR = (1 << 2), 188 CPU_FXSR = (1 << 2),
189 CPU_HT = (1 << 3), 189 CPU_HT = (1 << 3),
190 CPU_MMX = (1 << 4), 190 CPU_MMX = (1 << 4),
191 CPU_3DNOW = (1 << 5), // 3DNow comes from cpuid 0x80000001 (EDX) 191 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
192 // may not necessarily support other 3dnow instructions
192 CPU_SSE = (1 << 6), 193 CPU_SSE = (1 << 6),
193 CPU_SSE2 = (1 << 7), 194 CPU_SSE2 = (1 << 7),
194 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) 195 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
195 CPU_SSSE3 = (1 << 9), 196 CPU_SSSE3 = (1 << 9),
196 CPU_SSE4A = (1 << 10), 197 CPU_SSE4A = (1 << 10),
326 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) 327 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
327 result |= CPU_POPCNT; 328 result |= CPU_POPCNT;
328 329
329 // AMD features. 330 // AMD features.
330 if (is_amd()) { 331 if (is_amd()) {
331 if (_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) 332 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
332 result |= CPU_3DNOW; 333 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
334 result |= CPU_3DNOW_PREFETCH;
333 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) 335 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
334 result |= CPU_LZCNT; 336 result |= CPU_LZCNT;
335 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) 337 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
336 result |= CPU_SSE4A; 338 result |= CPU_SSE4A;
337 } 339 }
444 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } 446 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; }
445 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } 447 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; }
446 // 448 //
447 // AMD features 449 // AMD features
448 // 450 //
449 static bool supports_3dnow() { return (_cpuFeatures & CPU_3DNOW) != 0; } 451 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; }
450 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } 452 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
451 static bool supports_3dnow2() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.tdnow2 != 0; }
452 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } 453 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; }
453 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } 454 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
454 455
455 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). 456 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
456 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && 457 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&