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7035713: 3DNow Prefetch Instruction Support Summary: The upcoming processors from AMD are the first that support 3dnow prefetch without supporting the 3dnow instruction set. Reviewed-by: kvn Contributed-by: tom.deneau@amd.com
author kvn
date Mon, 11 Apr 2011 15:30:31 -0700
parents 7e88bdae86ec
children bad7ecd0b6ed
comparison
equal deleted inserted replaced
2478:328926869b15 2479:15c9a0e16269
3421 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 3421 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3422 masm.movptr(scrReg, boxReg) ; 3422 masm.movptr(scrReg, boxReg) ;
3423 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 3423 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3424 3424
3425 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 3425 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3426 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) { 3426 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3427 // prefetchw [eax + Offset(_owner)-2] 3427 // prefetchw [eax + Offset(_owner)-2]
3428 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); 3428 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3429 } 3429 }
3430 3430
3431 if ((EmitSync & 64) == 0) { 3431 if ((EmitSync & 64) == 0) {
3465 } else { 3465 } else {
3466 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty 3466 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3467 masm.movptr(boxReg, tmpReg) ; 3467 masm.movptr(boxReg, tmpReg) ;
3468 3468
3469 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 3469 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3470 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) { 3470 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3471 // prefetchw [eax + Offset(_owner)-2] 3471 // prefetchw [eax + Offset(_owner)-2]
3472 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); 3472 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3473 } 3473 }
3474 3474
3475 if ((EmitSync & 64) == 0) { 3475 if ((EmitSync & 64) == 0) {
3612 // IA32's memory-model is SPO, so STs are ordered with respect to 3612 // IA32's memory-model is SPO, so STs are ordered with respect to
3613 // each other and there's no need for an explicit barrier (fence). 3613 // each other and there's no need for an explicit barrier (fence).
3614 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 3614 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3615 3615
3616 masm.get_thread (boxReg) ; 3616 masm.get_thread (boxReg) ;
3617 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) { 3617 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3618 // prefetchw [ebx + Offset(_owner)-2] 3618 // prefetchw [ebx + Offset(_owner)-2]
3619 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2)); 3619 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3620 } 3620 }
3621 3621
3622 // Note that we could employ various encoding schemes to reduce 3622 // Note that we could employ various encoding schemes to reduce
7331 7331
7332 // Prefetch instructions. 7332 // Prefetch instructions.
7333 // Must be safe to execute with invalid address (cannot fault). 7333 // Must be safe to execute with invalid address (cannot fault).
7334 7334
7335 instruct prefetchr0( memory mem ) %{ 7335 instruct prefetchr0( memory mem ) %{
7336 predicate(UseSSE==0 && !VM_Version::supports_3dnow()); 7336 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
7337 match(PrefetchRead mem); 7337 match(PrefetchRead mem);
7338 ins_cost(0); 7338 ins_cost(0);
7339 size(0); 7339 size(0);
7340 format %{ "PREFETCHR (non-SSE is empty encoding)" %} 7340 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7341 ins_encode(); 7341 ins_encode();
7342 ins_pipe(empty); 7342 ins_pipe(empty);
7343 %} 7343 %}
7344 7344
7345 instruct prefetchr( memory mem ) %{ 7345 instruct prefetchr( memory mem ) %{
7346 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3); 7346 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
7347 match(PrefetchRead mem); 7347 match(PrefetchRead mem);
7348 ins_cost(100); 7348 ins_cost(100);
7349 7349
7350 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} 7350 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7351 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */ 7351 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
7385 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); 7385 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7386 ins_pipe(ialu_mem); 7386 ins_pipe(ialu_mem);
7387 %} 7387 %}
7388 7388
7389 instruct prefetchw0( memory mem ) %{ 7389 instruct prefetchw0( memory mem ) %{
7390 predicate(UseSSE==0 && !VM_Version::supports_3dnow()); 7390 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
7391 match(PrefetchWrite mem); 7391 match(PrefetchWrite mem);
7392 ins_cost(0); 7392 ins_cost(0);
7393 size(0); 7393 size(0);
7394 format %{ "Prefetch (non-SSE is empty encoding)" %} 7394 format %{ "Prefetch (non-SSE is empty encoding)" %}
7395 ins_encode(); 7395 ins_encode();
7396 ins_pipe(empty); 7396 ins_pipe(empty);
7397 %} 7397 %}
7398 7398
7399 instruct prefetchw( memory mem ) %{ 7399 instruct prefetchw( memory mem ) %{
7400 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3); 7400 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || AllocatePrefetchInstr==3);
7401 match( PrefetchWrite mem ); 7401 match( PrefetchWrite mem );
7402 ins_cost(100); 7402 ins_cost(100);
7403 7403
7404 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} 7404 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7405 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ 7405 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */