Mercurial > hg > truffle
comparison src/cpu/x86/vm/assembler_x86.cpp @ 20438:166d744df0de
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
Summary: Add new C2 intrinsic for BigInteger::multiplyToLen() on x86 in 64-bit VM.
Reviewed-by: roland
author | kvn |
---|---|
date | Tue, 02 Sep 2014 12:48:45 -0700 |
parents | b1bc1af04c6e |
children | 7848fc12602b |
comparison
equal
deleted
inserted
replaced
20437:bddcb33dadf4 | 20438:166d744df0de |
---|---|
4935 void Assembler::addq(Register dst, Register src) { | 4935 void Assembler::addq(Register dst, Register src) { |
4936 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | 4936 (void) prefixq_and_encode(dst->encoding(), src->encoding()); |
4937 emit_arith(0x03, 0xC0, dst, src); | 4937 emit_arith(0x03, 0xC0, dst, src); |
4938 } | 4938 } |
4939 | 4939 |
4940 void Assembler::adcxq(Register dst, Register src) { | |
4941 //assert(VM_Version::supports_adx(), "adx instructions not supported"); | |
4942 emit_int8((unsigned char)0x66); | |
4943 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4944 emit_int8(0x0F); | |
4945 emit_int8(0x38); | |
4946 emit_int8((unsigned char)0xF6); | |
4947 emit_int8((unsigned char)(0xC0 | encode)); | |
4948 } | |
4949 | |
4950 void Assembler::adoxq(Register dst, Register src) { | |
4951 //assert(VM_Version::supports_adx(), "adx instructions not supported"); | |
4952 emit_int8((unsigned char)0xF3); | |
4953 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4954 emit_int8(0x0F); | |
4955 emit_int8(0x38); | |
4956 emit_int8((unsigned char)0xF6); | |
4957 emit_int8((unsigned char)(0xC0 | encode)); | |
4958 } | |
4959 | |
4940 void Assembler::andq(Address dst, int32_t imm32) { | 4960 void Assembler::andq(Address dst, int32_t imm32) { |
4941 InstructionMark im(this); | 4961 InstructionMark im(this); |
4942 prefixq(dst); | 4962 prefixq(dst); |
4943 emit_int8((unsigned char)0x81); | 4963 emit_int8((unsigned char)0x81); |
4944 emit_operand(rsp, dst, 4); | 4964 emit_operand(rsp, dst, 4); |
5439 | 5459 |
5440 void Assembler::movzwq(Register dst, Register src) { | 5460 void Assembler::movzwq(Register dst, Register src) { |
5441 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 5461 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
5442 emit_int8((unsigned char)0x0F); | 5462 emit_int8((unsigned char)0x0F); |
5443 emit_int8((unsigned char)0xB7); | 5463 emit_int8((unsigned char)0xB7); |
5464 emit_int8((unsigned char)(0xC0 | encode)); | |
5465 } | |
5466 | |
5467 void Assembler::mulq(Address src) { | |
5468 InstructionMark im(this); | |
5469 prefixq(src); | |
5470 emit_int8((unsigned char)0xF7); | |
5471 emit_operand(rsp, src); | |
5472 } | |
5473 | |
5474 void Assembler::mulq(Register src) { | |
5475 int encode = prefixq_and_encode(src->encoding()); | |
5476 emit_int8((unsigned char)0xF7); | |
5477 emit_int8((unsigned char)(0xE0 | encode)); | |
5478 } | |
5479 | |
5480 void Assembler::mulxq(Register dst1, Register dst2, Register src) { | |
5481 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); | |
5482 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, true, false); | |
5483 emit_int8((unsigned char)0xF6); | |
5444 emit_int8((unsigned char)(0xC0 | encode)); | 5484 emit_int8((unsigned char)(0xC0 | encode)); |
5445 } | 5485 } |
5446 | 5486 |
5447 void Assembler::negq(Register dst) { | 5487 void Assembler::negq(Register dst) { |
5448 int encode = prefixq_and_encode(dst->encoding()); | 5488 int encode = prefixq_and_encode(dst->encoding()); |
5570 emit_int8((unsigned char)0xC1); | 5610 emit_int8((unsigned char)0xC1); |
5571 emit_int8((unsigned char)(0xD0 | encode)); | 5611 emit_int8((unsigned char)(0xD0 | encode)); |
5572 emit_int8(imm8); | 5612 emit_int8(imm8); |
5573 } | 5613 } |
5574 } | 5614 } |
5615 | |
5616 void Assembler::rorq(Register dst, int imm8) { | |
5617 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5618 int encode = prefixq_and_encode(dst->encoding()); | |
5619 if (imm8 == 1) { | |
5620 emit_int8((unsigned char)0xD1); | |
5621 emit_int8((unsigned char)(0xC8 | encode)); | |
5622 } else { | |
5623 emit_int8((unsigned char)0xC1); | |
5624 emit_int8((unsigned char)(0xc8 | encode)); | |
5625 emit_int8(imm8); | |
5626 } | |
5627 } | |
5628 | |
5629 void Assembler::rorxq(Register dst, Register src, int imm8) { | |
5630 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); | |
5631 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, true, false); | |
5632 emit_int8((unsigned char)0xF0); | |
5633 emit_int8((unsigned char)(0xC0 | encode)); | |
5634 emit_int8(imm8); | |
5635 } | |
5636 | |
5575 void Assembler::sarq(Register dst, int imm8) { | 5637 void Assembler::sarq(Register dst, int imm8) { |
5576 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | 5638 assert(isShiftCount(imm8 >> 1), "illegal shift count"); |
5577 int encode = prefixq_and_encode(dst->encoding()); | 5639 int encode = prefixq_and_encode(dst->encoding()); |
5578 if (imm8 == 1) { | 5640 if (imm8 == 1) { |
5579 emit_int8((unsigned char)0xD1); | 5641 emit_int8((unsigned char)0xD1); |