Mercurial > hg > truffle

comparison src/cpu/x86/vm/x86_32.ad @ 824:18a08a7e16b5

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
5057225: Remove useless I2L conversions Summary: The optimizer should be told to normalize (AndL (ConvI2L x) 0xFF) to (ConvI2L (AndI x 0xFF)), and then the existing matcher rule will work for free. Reviewed-by: kvn
author twisti
date Fri, 26 Jun 2009 07:26:10 -0700
parents 2056494941db
children 62001a362ce9
comparison
equal deleted inserted replaced
823:14367225a853 824:18a08a7e16b5
6883 6883
6884 ins_pipe(ialu_reg_mem); 6884 ins_pipe(ialu_reg_mem);
6885 %} 6885 %}
6886 6886
6887 // Load Byte (8bit signed) into Long Register 6887 // Load Byte (8bit signed) into Long Register
6888 instruct loadB2L(eRegL dst, memory mem) %{ 6888 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6889 match(Set dst (ConvI2L (LoadB mem))); 6889 match(Set dst (ConvI2L (LoadB mem)));
6890 effect(KILL cr);
6890 6891
6891 ins_cost(375); 6892 ins_cost(375);
6892 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" 6893 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
6893 "MOV $dst.hi,$dst.lo\n\t" 6894 "MOV $dst.hi,$dst.lo\n\t"
6894 "SAR $dst.hi,7" %} 6895 "SAR $dst.hi,7" %}
6915 6916
6916 ins_pipe(ialu_reg_mem); 6917 ins_pipe(ialu_reg_mem);
6917 %} 6918 %}
6918 6919
6919 // Load Unsigned Byte (8 bit UNsigned) into Long Register 6920 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6920 instruct loadUB2L(eRegL dst, memory mem) 6921 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6921 %{
6922 match(Set dst (ConvI2L (LoadUB mem))); 6922 match(Set dst (ConvI2L (LoadUB mem)));
6923 effect(KILL cr);
6923 6924
6924 ins_cost(250); 6925 ins_cost(250);
6925 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" 6926 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
6926 "XOR $dst.hi,$dst.hi" %} 6927 "XOR $dst.hi,$dst.hi" %}
6927 6928
6928 ins_encode %{ 6929 ins_encode %{
6929 __ movzbl($dst$$Register, $mem$$Address); 6930 Register Rdst = $dst$$Register;
6930 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); 6931 __ movzbl(Rdst, $mem$$Address);
6931 %} 6932 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6932 6933 %}
6934
6935 ins_pipe(ialu_reg_mem);
6936 %}
6937
6938 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
6939 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
6940 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
6941 effect(KILL cr);
6942
6943 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
6944 "XOR $dst.hi,$dst.hi\n\t"
6945 "AND $dst.lo,$mask" %}
6946 ins_encode %{
6947 Register Rdst = $dst$$Register;
6948 __ movzbl(Rdst, $mem$$Address);
6949 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6950 __ andl(Rdst, $mask$$constant);
6951 %}
6933 ins_pipe(ialu_reg_mem); 6952 ins_pipe(ialu_reg_mem);
6934 %} 6953 %}
6935 6954
6936 // Load Short (16bit signed) 6955 // Load Short (16bit signed)
6937 instruct loadS(eRegI dst, memory mem) %{ 6956 instruct loadS(eRegI dst, memory mem) %{
6958 %} 6977 %}
6959 ins_pipe(ialu_reg_mem); 6978 ins_pipe(ialu_reg_mem);
6960 %} 6979 %}
6961 6980
6962 // Load Short (16bit signed) into Long Register 6981 // Load Short (16bit signed) into Long Register
6963 instruct loadS2L(eRegL dst, memory mem) %{ 6982 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6964 match(Set dst (ConvI2L (LoadS mem))); 6983 match(Set dst (ConvI2L (LoadS mem)));
6984 effect(KILL cr);
6965 6985
6966 ins_cost(375); 6986 ins_cost(375);
6967 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" 6987 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6968 "MOV $dst.hi,$dst.lo\n\t" 6988 "MOV $dst.hi,$dst.lo\n\t"
6969 "SAR $dst.hi,15" %} 6989 "SAR $dst.hi,15" %}
7002 %} 7022 %}
7003 ins_pipe(ialu_reg_mem); 7023 ins_pipe(ialu_reg_mem);
7004 %} 7024 %}
7005 7025
7006 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register 7026 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
7007 instruct loadUS2L(eRegL dst, memory mem) %{ 7027 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
7008 match(Set dst (ConvI2L (LoadUS mem))); 7028 match(Set dst (ConvI2L (LoadUS mem)));
7029 effect(KILL cr);
7009 7030
7010 ins_cost(250); 7031 ins_cost(250);
7011 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" 7032 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
7012 "XOR $dst.hi,$dst.hi" %} 7033 "XOR $dst.hi,$dst.hi" %}
7013 7034
7014 ins_encode %{ 7035 ins_encode %{
7015 __ movzwl($dst$$Register, $mem$$Address); 7036 __ movzwl($dst$$Register, $mem$$Address);
7016 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); 7037 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
7017 %} 7038 %}
7018 7039
7040 ins_pipe(ialu_reg_mem);
7041 %}
7042
7043 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
7044 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
7045 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
7046 effect(KILL cr);
7047
7048 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
7049 "XOR $dst.hi,$dst.hi" %}
7050 ins_encode %{
7051 Register Rdst = $dst$$Register;
7052 __ movzbl(Rdst, $mem$$Address);
7053 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
7054 %}
7055 ins_pipe(ialu_reg_mem);
7056 %}
7057
7058 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
7059 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
7060 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
7061 effect(KILL cr);
7062
7063 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
7064 "XOR $dst.hi,$dst.hi\n\t"
7065 "AND $dst.lo,$mask" %}
7066 ins_encode %{
7067 Register Rdst = $dst$$Register;
7068 __ movzwl(Rdst, $mem$$Address);
7069 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
7070 __ andl(Rdst, $mask$$constant);
7071 %}
7019 ins_pipe(ialu_reg_mem); 7072 ins_pipe(ialu_reg_mem);
7020 %} 7073 %}
7021 7074
7022 // Load Integer 7075 // Load Integer
7023 instruct loadI(eRegI dst, memory mem) %{ 7076 instruct loadI(eRegI dst, memory mem) %{
7080 %} 7133 %}
7081 ins_pipe(ialu_reg_mem); 7134 ins_pipe(ialu_reg_mem);
7082 %} 7135 %}
7083 7136
7084 // Load Integer into Long Register 7137 // Load Integer into Long Register
7085 instruct loadI2L(eRegL dst, memory mem) %{ 7138 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
7086 match(Set dst (ConvI2L (LoadI mem))); 7139 match(Set dst (ConvI2L (LoadI mem)));
7140 effect(KILL cr);
7087 7141
7088 ins_cost(375); 7142 ins_cost(375);
7089 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" 7143 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
7090 "MOV $dst.hi,$dst.lo\n\t" 7144 "MOV $dst.hi,$dst.lo\n\t"
7091 "SAR $dst.hi,31" %} 7145 "SAR $dst.hi,31" %}
7097 %} 7151 %}
7098 7152
7099 ins_pipe(ialu_reg_mem); 7153 ins_pipe(ialu_reg_mem);
7100 %} 7154 %}
7101 7155
7156 // Load Integer with mask 0xFF into Long Register
7157 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
7158 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
7159 effect(KILL cr);
7160
7161 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
7162 "XOR $dst.hi,$dst.hi" %}
7163 ins_encode %{
7164 Register Rdst = $dst$$Register;
7165 __ movzbl(Rdst, $mem$$Address);
7166 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
7167 %}
7168 ins_pipe(ialu_reg_mem);
7169 %}
7170
7171 // Load Integer with mask 0xFFFF into Long Register
7172 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
7173 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
7174 effect(KILL cr);
7175
7176 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
7177 "XOR $dst.hi,$dst.hi" %}
7178 ins_encode %{
7179 Register Rdst = $dst$$Register;
7180 __ movzwl(Rdst, $mem$$Address);
7181 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
7182 %}
7183 ins_pipe(ialu_reg_mem);
7184 %}
7185
7186 // Load Integer with 32-bit mask into Long Register
7187 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
7188 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
7189 effect(KILL cr);
7190
7191 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
7192 "XOR $dst.hi,$dst.hi\n\t"
7193 "AND $dst.lo,$mask" %}
7194 ins_encode %{
7195 Register Rdst = $dst$$Register;
7196 __ movl(Rdst, $mem$$Address);
7197 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
7198 __ andl(Rdst, $mask$$constant);
7199 %}
7200 ins_pipe(ialu_reg_mem);
7201 %}
7202
7102 // Load Unsigned Integer into Long Register 7203 // Load Unsigned Integer into Long Register
7103 instruct loadUI2L(eRegL dst, memory mem) %{ 7204 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
7104 match(Set dst (LoadUI2L mem)); 7205 match(Set dst (LoadUI2L mem));
7206 effect(KILL cr);
7105 7207
7106 ins_cost(250); 7208 ins_cost(250);
7107 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" 7209 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
7108 "XOR $dst.hi,$dst.hi" %} 7210 "XOR $dst.hi,$dst.hi" %}
7109 7211
7691 format %{ "MOV $mem,$src.lo\n\t" 7793 format %{ "MOV $mem,$src.lo\n\t"
7692 "MOV $mem+4,$src.hi" %} 7794 "MOV $mem+4,$src.hi" %}
7693 opcode(0x89, 0x89); 7795 opcode(0x89, 0x89);
7694 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); 7796 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
7695 ins_pipe( ialu_mem_long_reg ); 7797 ins_pipe( ialu_mem_long_reg );
7798 %}
7799
7800 // Store Long to Integer
7801 instruct storeL2I(memory mem, eRegL src) %{
7802 match(Set mem (StoreI mem (ConvL2I src)));
7803
7804 format %{ "MOV $mem,$src.lo\t# long -> int" %}
7805 ins_encode %{
7806 __ movl($mem$$Address, $src$$Register);
7807 %}
7808 ins_pipe(ialu_mem_reg);
7696 %} 7809 %}
7697 7810
7698 // Volatile Store Long. Must be atomic, so move it into 7811 // Volatile Store Long. Must be atomic, so move it into
7699 // the FP TOS and then do a 64-bit FIST. Has to probe the 7812 // the FP TOS and then do a 64-bit FIST. Has to probe the
7700 // target address before the store (for null-ptr checks) 7813 // target address before the store (for null-ptr checks)