Mercurial > hg > truffle
comparison src/share/vm/runtime/vm_version.hpp @ 3854:1af104d6cf99
7079329: Adjust allocation prefetching for T4
Summary: on T4 2 BIS instructions should be issued to prefetch 64 bytes
Reviewed-by: iveresov, phh, twisti
author | kvn |
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date | Tue, 16 Aug 2011 16:59:46 -0700 |
parents | 1d1603768966 |
children | c77d473e71f7 |
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3853:11211f7cb5a0 | 3854:1af104d6cf99 |
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42 static int _vm_minor_version; | 42 static int _vm_minor_version; |
43 static int _vm_build_number; | 43 static int _vm_build_number; |
44 static bool _initialized; | 44 static bool _initialized; |
45 static int _parallel_worker_threads; | 45 static int _parallel_worker_threads; |
46 static bool _parallel_worker_threads_initialized; | 46 static bool _parallel_worker_threads_initialized; |
47 static int _reserve_for_allocation_prefetch; | |
47 | 48 |
48 static unsigned int nof_parallel_worker_threads(unsigned int num, | 49 static unsigned int nof_parallel_worker_threads(unsigned int num, |
49 unsigned int dem, | 50 unsigned int dem, |
50 unsigned int switch_pt); | 51 unsigned int switch_pt); |
51 public: | 52 public: |
75 static bool supports_cx8() {return _supports_cx8;} | 76 static bool supports_cx8() {return _supports_cx8;} |
76 static unsigned int logical_processors_per_package() { | 77 static unsigned int logical_processors_per_package() { |
77 return _logical_processors_per_package; | 78 return _logical_processors_per_package; |
78 } | 79 } |
79 | 80 |
81 // Need a space at the end of TLAB for prefetch instructions | |
82 // which may fault when accessing memory outside of heap. | |
83 static int reserve_for_allocation_prefetch() { | |
84 return _reserve_for_allocation_prefetch; | |
85 } | |
86 | |
80 // ARCH specific policy for the BiasedLocking | 87 // ARCH specific policy for the BiasedLocking |
81 static bool use_biased_locking() { return true; } | 88 static bool use_biased_locking() { return true; } |
82 | 89 |
83 // Number of page sizes efficiently supported by the hardware. Most chips now | 90 // Number of page sizes efficiently supported by the hardware. Most chips now |
84 // support two sizes, thus this default implementation. Processor-specific | 91 // support two sizes, thus this default implementation. Processor-specific |