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comparison graal/com.oracle.graal.hsail/src/com/oracle/graal/hsail/HSAIL.java @ 12664:1fdecc36c8ac

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HSAIL updates to integrate recent changes to the providers infrastructure. Contributed-by: Tom Deneau <tom.deneau@amd.com>
author Doug Simon <doug.simon@oracle.com>
date Mon, 04 Nov 2013 17:17:08 +0100
parents ea308a63760b
children 343541fb3b49
comparison
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12663:7f507f082daa 12664:1fdecc36c8ac
20 * or visit www.oracle.com if you need additional information or have any 20 * or visit www.oracle.com if you need additional information or have any
21 * questions. 21 * questions.
22 */ 22 */
23 package com.oracle.graal.hsail; 23 package com.oracle.graal.hsail;
24 24
25 import static com.oracle.graal.api.code.MemoryBarriers.*;
26 import static com.oracle.graal.api.code.ValueUtil.*; 25 import static com.oracle.graal.api.code.ValueUtil.*;
27 26
28 import java.nio.*; 27 import java.nio.*;
29 28
30 import com.oracle.graal.api.code.*; 29 import com.oracle.graal.api.code.*;
35 /** 34 /**
36 * Represents the HSAIL architecture. 35 * Represents the HSAIL architecture.
37 */ 36 */
38 public class HSAIL extends Architecture { 37 public class HSAIL extends Architecture {
39 38
40 // @formatter:off
41 public static final RegisterCategory CPU = new RegisterCategory("CPU"); 39 public static final RegisterCategory CPU = new RegisterCategory("CPU");
42 public static final RegisterCategory FPU = new RegisterCategory("FPU"); 40 public static final RegisterCategory FPU = new RegisterCategory("FPU");
43 41
44 // Control registers. 42 // Control registers.
45 public static final Register c0 = new Register(0, 0, "c0", CPU); 43 public static final Register c0 = new Register(0, 0, "c0", CPU);
49 public static final Register c4 = new Register(4, 4, "c4", CPU); 47 public static final Register c4 = new Register(4, 4, "c4", CPU);
50 public static final Register c5 = new Register(5, 5, "c5", CPU); 48 public static final Register c5 = new Register(5, 5, "c5", CPU);
51 public static final Register c6 = new Register(6, 6, "c6", CPU); 49 public static final Register c6 = new Register(6, 6, "c6", CPU);
52 public static final Register c7 = new Register(7, 7, "c7", CPU); 50 public static final Register c7 = new Register(7, 7, "c7", CPU);
53 51
54 //32 bit registers. 52 // 32 bit registers.
55 public static final Register s0 = new Register(8, 0, "s0", CPU); 53 public static final Register s0 = new Register(8, 0, "s0", CPU);
56 public static final Register s1 = new Register(9, 1, "s1", CPU); 54 public static final Register s1 = new Register(9, 1, "s1", CPU);
57 public static final Register s2 = new Register(10, 2, "s2", CPU); 55 public static final Register s2 = new Register(10, 2, "s2", CPU);
58 public static final Register s3 = new Register(11, 3, "s3", CPU); 56 public static final Register s3 = new Register(11, 3, "s3", CPU);
59 public static final Register s4 = new Register(12, 4, "s4", CPU); 57 public static final Register s4 = new Register(12, 4, "s4", CPU);
60 public static final Register s5 = new Register(13, 5, "s5", CPU); 58 public static final Register s5 = new Register(13, 5, "s5", CPU);
61 public static final Register s6 = new Register(14, 6, "s6", CPU); 59 public static final Register s6 = new Register(14, 6, "s6", CPU);
62 public static final Register s7 = new Register(15, 7, "s7", CPU); 60 public static final Register s7 = new Register(15, 7, "s7", CPU);
63 public static final Register s8 = new Register(16, 8, "s8", CPU); 61 public static final Register s8 = new Register(16, 8, "s8", CPU);
64 public static final Register s9 = new Register(17, 9, "s9", CPU); 62 public static final Register s9 = new Register(17, 9, "s9", CPU);
65 public static final Register s10 = new Register(18, 10, "s10", CPU); 63 public static final Register s10 = new Register(18, 10, "s10", CPU);
66 public static final Register s11 = new Register(19, 11, "s11", CPU); 64 public static final Register s11 = new Register(19, 11, "s11", CPU);
67 public static final Register s12 = new Register(20, 12, "s12", CPU); 65 public static final Register s12 = new Register(20, 12, "s12", CPU);
68 public static final Register s13 = new Register(21, 13, "s13", CPU); 66 public static final Register s13 = new Register(21, 13, "s13", CPU);
69 public static final Register s14 = new Register(22, 14, "s14", CPU); 67 public static final Register s14 = new Register(22, 14, "s14", CPU);
70 public static final Register s15 = new Register(23, 15, "s15", CPU); 68 public static final Register s15 = new Register(23, 15, "s15", CPU);
71 public static final Register s16 = new Register(24, 16, "s16", CPU); 69 public static final Register s16 = new Register(24, 16, "s16", CPU);
72 public static final Register s17 = new Register(25, 17, "s17", CPU); 70 public static final Register s17 = new Register(25, 17, "s17", CPU);
73 public static final Register s18 = new Register(26, 18, "s18", CPU); 71 public static final Register s18 = new Register(26, 18, "s18", CPU);
74 public static final Register s19 = new Register(27, 19, "s19", CPU); 72 public static final Register s19 = new Register(27, 19, "s19", CPU);
75 public static final Register s20 = new Register(28, 20, "s20", CPU); 73 public static final Register s20 = new Register(28, 20, "s20", CPU);
76 public static final Register s21 = new Register(29, 21, "s21", CPU); 74 public static final Register s21 = new Register(29, 21, "s21", CPU);
77 public static final Register s22 = new Register(30, 22, "s22", CPU); 75 public static final Register s22 = new Register(30, 22, "s22", CPU);
78 public static final Register s23 = new Register(31, 23, "s23", CPU); 76 public static final Register s23 = new Register(31, 23, "s23", CPU);
79 public static final Register s24 = new Register(32, 24, "s24", CPU); 77 public static final Register s24 = new Register(32, 24, "s24", CPU);
80 public static final Register s25 = new Register(33, 25, "s25", CPU); 78 public static final Register s25 = new Register(33, 25, "s25", CPU);
81 public static final Register s26 = new Register(34, 26, "s26", CPU); 79 public static final Register s26 = new Register(34, 26, "s26", CPU);
82 public static final Register s27 = new Register(35, 27, "s27", CPU); 80 public static final Register s27 = new Register(35, 27, "s27", CPU);
83 public static final Register s28 = new Register(36, 28, "s28", CPU); 81 public static final Register s28 = new Register(36, 28, "s28", CPU);
84 public static final Register s29 = new Register(37, 29, "s29", CPU); 82 public static final Register s29 = new Register(37, 29, "s29", CPU);
85 public static final Register s30 = new Register(38, 30, "s30", CPU); 83 public static final Register s30 = new Register(38, 30, "s30", CPU);
86 public static final Register s31 = new Register(39, 31, "s31", CPU); 84 public static final Register s31 = new Register(39, 31, "s31", CPU);
87 public static final Register s32 = new Register(40, 32, "s32", CPU); 85
88 public static final Register s33 = new Register(41, 33, "s33", CPU); 86 // 64 bit registers.
89 public static final Register s34 = new Register(42, 34, "s34", CPU); 87 public static final Register d0 = new Register(40, 0, "d0", CPU);
90 public static final Register s35 = new Register(43, 35, "s35", CPU); 88 public static final Register d1 = new Register(41, 1, "d1", CPU);
91 public static final Register s36 = new Register(44, 36, "s36", CPU); 89 public static final Register d2 = new Register(42, 2, "d2", CPU);
92 public static final Register s37 = new Register(45, 37, "s37", CPU); 90 public static final Register d3 = new Register(43, 3, "d3", CPU);
93 public static final Register s38 = new Register(45, 38, "s38", CPU); 91 public static final Register d4 = new Register(44, 4, "d4", CPU);
94 public static final Register s39 = new Register(46, 39, "s39", CPU); 92 public static final Register d5 = new Register(45, 5, "d5", CPU);
95 public static final Register s40 = new Register(47, 40, "s40", CPU); 93 public static final Register d6 = new Register(46, 6, "d6", CPU);
96 public static final Register s41 = new Register(48, 41, "s41", CPU); 94 public static final Register d7 = new Register(47, 7, "d7", CPU);
97 public static final Register s42 = new Register(49, 42, "s42", CPU); 95 public static final Register d8 = new Register(48, 8, "d8", CPU);
98 public static final Register s43 = new Register(50, 43, "s43", CPU); 96 public static final Register d9 = new Register(49, 9, "d9", CPU);
99 public static final Register s44 = new Register(51, 44, "s44", CPU); 97 public static final Register d10 = new Register(50, 10, "d10", CPU);
100 public static final Register s45 = new Register(52, 45, "s45", CPU); 98 public static final Register d11 = new Register(51, 11, "d11", CPU);
101 public static final Register s46 = new Register(53, 46, "s46", CPU); 99 public static final Register d12 = new Register(52, 12, "d12", CPU);
102 public static final Register s47 = new Register(54, 47, "s47", CPU); 100 public static final Register d13 = new Register(53, 13, "d13", CPU);
103 public static final Register s48 = new Register(55, 48, "s48", CPU); 101 public static final Register d14 = new Register(54, 14, "d14", CPU);
104 public static final Register s49 = new Register(56, 49, "s49", CPU); 102 public static final Register d15 = new Register(55, 15, "d15", CPU);
105 public static final Register s50 = new Register(57, 50, "s50", CPU); 103
106 public static final Register s51 = new Register(58, 51, "s51", CPU); 104 // 128 bit registers.
107 public static final Register s52 = new Register(59, 52, "s52", CPU); 105 public static final Register q0 = new Register(56, 0, "q0", CPU);
108 public static final Register s53 = new Register(60, 53, "s53", CPU); 106 public static final Register q1 = new Register(57, 1, "q1", CPU);
109 public static final Register s54 = new Register(61, 54, "s54", CPU); 107 public static final Register q2 = new Register(58, 2, "q2", CPU);
110 public static final Register s55 = new Register(62, 55, "s55", CPU); 108 public static final Register q3 = new Register(59, 3, "q3", CPU);
111 public static final Register s56 = new Register(64, 56, "s56", CPU); 109 public static final Register q4 = new Register(60, 4, "q4", CPU);
112 public static final Register s57 = new Register(64, 57, "s57", CPU); 110 public static final Register q5 = new Register(61, 5, "q5", CPU);
113 public static final Register s58 = new Register(65, 58, "s58", CPU); 111 public static final Register q6 = new Register(62, 6, "q6", CPU);
114 public static final Register s59 = new Register(66, 59, "s59", CPU); 112 public static final Register q7 = new Register(63, 7, "q7", CPU);
115 public static final Register s60 = new Register(67, 60, "s60", CPU); 113 public static final Register q8 = new Register(64, 8, "q8", CPU);
116 public static final Register s61 = new Register(68, 61, "s61", CPU); 114 public static final Register q9 = new Register(65, 9, "q9", CPU);
117 public static final Register s62 = new Register(69, 62, "s62", CPU); 115 public static final Register q10 = new Register(66, 10, "q10", CPU);
118 public static final Register s63 = new Register(70, 63, "s63", CPU); 116 public static final Register q11 = new Register(67, 11, "q11", CPU);
119 public static final Register s64 = new Register(71, 64, "s64", CPU); 117 public static final Register q12 = new Register(68, 12, "q12", CPU);
120 public static final Register s65 = new Register(72, 65, "s65", CPU); 118 public static final Register q13 = new Register(69, 13, "q13", CPU);
121 public static final Register s66 = new Register(73, 66, "s66", CPU); 119 public static final Register q14 = new Register(70, 14, "q14", CPU);
122 public static final Register s67 = new Register(74, 67, "s67", CPU); 120 public static final Register q15 = new Register(71, 15, "q15", CPU);
123 public static final Register s68 = new Register(75, 68, "s68", CPU); 121
124 public static final Register s69 = new Register(76, 69, "s69", CPU); 122 // @formatter:off
125 public static final Register s70 = new Register(77, 70, "s70", CPU);
126 public static final Register s71 = new Register(78, 71, "s71", CPU);
127 public static final Register s72 = new Register(79, 72, "s72", CPU);
128 public static final Register s73 = new Register(80, 73, "s73", CPU);
129 public static final Register s74 = new Register(81, 74, "s74", CPU);
130 public static final Register s75 = new Register(82, 75, "s75", CPU);
131 public static final Register s76 = new Register(83, 76, "s76", CPU);
132 public static final Register s77 = new Register(84, 77, "s77", CPU);
133 public static final Register s78 = new Register(85, 78, "s78", CPU);
134 public static final Register s79 = new Register(86, 79, "s79", CPU);
135 public static final Register s80 = new Register(87, 80, "s80", CPU);
136 public static final Register s81 = new Register(88, 81, "s81", CPU);
137 public static final Register s82 = new Register(89, 82, "s82", CPU);
138 public static final Register s83 = new Register(90, 83, "s83", CPU);
139 public static final Register s84 = new Register(91, 84, "s84", CPU);
140 public static final Register s85 = new Register(92, 85, "s85", CPU);
141 public static final Register s86 = new Register(93, 86, "s86", CPU);
142 public static final Register s87 = new Register(94, 87, "s87", CPU);
143 public static final Register s88 = new Register(95, 88, "s88", CPU);
144 public static final Register s89 = new Register(96, 89, "s89", CPU);
145 public static final Register s90 = new Register(97, 90, "s90", CPU);
146 public static final Register s91 = new Register(98, 91, "s91", CPU);
147 public static final Register s92 = new Register(99, 92, "s92", CPU);
148 public static final Register s93 = new Register(100, 93, "s93", CPU);
149 public static final Register s94 = new Register(101, 94, "s94", CPU);
150 public static final Register s95 = new Register(102, 95, "s95", CPU);
151 public static final Register s96 = new Register(103, 96, "s96", CPU);
152 public static final Register s97 = new Register(104, 97, "s97", CPU);
153 public static final Register s98 = new Register(105, 98, "s98", CPU);
154 public static final Register s99 = new Register(106, 99, "s99", CPU);
155 public static final Register s100 = new Register(107, 100, "s100", CPU);
156 public static final Register s101 = new Register(108, 101, "s101", CPU);
157 public static final Register s102 = new Register(109, 102, "s102", CPU);
158 public static final Register s103 = new Register(110, 103, "s103", CPU);
159 public static final Register s104 = new Register(111, 104, "s104", CPU);
160 public static final Register s105 = new Register(112, 105, "s105", CPU);
161 public static final Register s106 = new Register(113, 106, "s106", CPU);
162 public static final Register s107 = new Register(114, 107, "s107", CPU);
163 public static final Register s108 = new Register(115, 108, "s108", CPU);
164 public static final Register s109 = new Register(116, 109, "s109", CPU);
165 public static final Register s110 = new Register(117, 110, "s110", CPU);
166 public static final Register s111 = new Register(118, 111, "s111", CPU);
167 public static final Register s112 = new Register(119, 112, "s112", CPU);
168 public static final Register s113 = new Register(120, 113, "s113", CPU);
169 public static final Register s114 = new Register(121, 114, "s114", CPU);
170 public static final Register s115 = new Register(122, 115, "s115", CPU);
171 public static final Register s116 = new Register(123, 116, "s116", CPU);
172 public static final Register s117 = new Register(124, 117, "s117", CPU);
173 public static final Register s118 = new Register(125, 118, "s118", CPU);
174 public static final Register s119 = new Register(126, 119, "s119", CPU);
175 public static final Register s120 = new Register(127, 120, "s120", CPU);
176 public static final Register s121 = new Register(128, 121, "s121", CPU);
177 public static final Register s122 = new Register(129, 122, "s122", CPU);
178 public static final Register s123 = new Register(130, 123, "s123", CPU);
179 public static final Register s124 = new Register(131, 124, "s124", CPU);
180 public static final Register s125 = new Register(132, 125, "s125", CPU);
181 public static final Register s126 = new Register(133, 126, "s126", CPU);
182 public static final Register s127 = new Register(134, 127, "s127", CPU);
183
184 //64 bit registers.
185 public static final Register d0 = new Register(135, 0, "d0", CPU);
186 public static final Register d1 = new Register(136, 1, "d1", CPU);
187 public static final Register d2 = new Register(137, 2, "d2", CPU);
188 public static final Register d3 = new Register(138, 3, "d3", CPU);
189 public static final Register d4 = new Register(139, 4, "d4", CPU);
190 public static final Register d5 = new Register(140, 5, "d5", CPU);
191 public static final Register d6 = new Register(141, 6, "d6", CPU);
192 public static final Register d7 = new Register(142, 7, "d7", CPU);
193 public static final Register d8 = new Register(143, 8, "d8", CPU);
194 public static final Register d9 = new Register(144, 9, "d9", CPU);
195 public static final Register d10 = new Register(145, 10, "d10", CPU);
196 public static final Register d11 = new Register(146, 11, "d11", CPU);
197 public static final Register d12 = new Register(147, 12, "d12", CPU);
198 public static final Register d13 = new Register(148, 13, "d13", CPU);
199 public static final Register d14 = new Register(149, 14, "d14", CPU);
200 public static final Register d15 = new Register(150, 15, "d15", CPU);
201 public static final Register d16 = new Register(151, 16, "d16", CPU);
202 public static final Register d17 = new Register(152, 17, "d17", CPU);
203 public static final Register d18 = new Register(153, 18, "d18", CPU);
204 public static final Register d19 = new Register(154, 19, "d19", CPU);
205 public static final Register d20 = new Register(155, 20, "d20", CPU);
206 public static final Register d21 = new Register(156, 21, "d21", CPU);
207 public static final Register d22 = new Register(157, 22, "d22", CPU);
208 public static final Register d23 = new Register(158, 23, "d23", CPU);
209 public static final Register d24 = new Register(159, 24, "d24", CPU);
210 public static final Register d25 = new Register(160, 25, "d25", CPU);
211 public static final Register d26 = new Register(161, 26, "d26", CPU);
212 public static final Register d27 = new Register(162, 27, "d27", CPU);
213 public static final Register d28 = new Register(163, 28, "d28", CPU);
214 public static final Register d29 = new Register(164, 29, "d29", CPU);
215 public static final Register d30 = new Register(165, 30, "d30", CPU);
216 public static final Register d31 = new Register(166, 31, "d31", CPU);
217 public static final Register d32 = new Register(167, 32, "d32", CPU);
218 public static final Register d33 = new Register(168, 33, "d33", CPU);
219 public static final Register d34 = new Register(169, 34, "d34", CPU);
220 public static final Register d35 = new Register(170, 35, "d35", CPU);
221 public static final Register d36 = new Register(171, 36, "d36", CPU);
222 public static final Register d37 = new Register(172, 37, "d37", CPU);
223 public static final Register d38 = new Register(173, 38, "d38", CPU);
224 public static final Register d39 = new Register(174, 39, "d39", CPU);
225 public static final Register d40 = new Register(175, 40, "d40", CPU);
226 public static final Register d41 = new Register(176, 41, "d41", CPU);
227 public static final Register d42 = new Register(177, 42, "d42", CPU);
228 public static final Register d43 = new Register(178, 43, "d43", CPU);
229 public static final Register d44 = new Register(179, 44, "d44", CPU);
230 public static final Register d45 = new Register(180, 45, "d45", CPU);
231 public static final Register d46 = new Register(181, 46, "d46", CPU);
232 public static final Register d47 = new Register(182, 47, "d47", CPU);
233 public static final Register d48 = new Register(183, 48, "d48", CPU);
234 public static final Register d49 = new Register(184, 49, "d49", CPU);
235 public static final Register d50 = new Register(185, 50, "d50", CPU);
236 public static final Register d51 = new Register(186, 51, "d51", CPU);
237 public static final Register d52 = new Register(187, 52, "d52", CPU);
238 public static final Register d53 = new Register(188, 53, "d53", CPU);
239 public static final Register d54 = new Register(189, 54, "d54", CPU);
240 public static final Register d55 = new Register(190, 55, "d55", CPU);
241 public static final Register d56 = new Register(191, 56, "d56", CPU);
242 public static final Register d57 = new Register(192, 57, "d57", CPU);
243 public static final Register d58 = new Register(193, 58, "d58", CPU);
244 public static final Register d59 = new Register(194, 59, "d59", CPU);
245 public static final Register d60 = new Register(195, 60, "d60", CPU);
246 public static final Register d61 = new Register(196, 61, "d61", CPU);
247 public static final Register d62 = new Register(197, 62, "d62", CPU);
248 public static final Register d63 = new Register(198, 63, "d63", CPU);
249
250 //128 bit registers.
251 public static final Register q0 = new Register(199, 0, "q0", CPU);
252 public static final Register q1 = new Register(200, 1, "q1", CPU);
253 public static final Register q2 = new Register(201, 2, "q2", CPU);
254 public static final Register q3 = new Register(202, 3, "q3", CPU);
255 public static final Register q4 = new Register(203, 4, "q4", CPU);
256 public static final Register q5 = new Register(204, 5, "q5", CPU);
257 public static final Register q6 = new Register(205, 6, "q6", CPU);
258 public static final Register q7 = new Register(206, 7, "q7", CPU);
259 public static final Register q8 = new Register(207, 8, "q8", CPU);
260 public static final Register q9 = new Register(208, 9, "q9", CPU);
261 public static final Register q10 = new Register(209, 10, "q10", CPU);
262 public static final Register q11 = new Register(210, 11, "q11", CPU);
263 public static final Register q12 = new Register(211, 12, "q12", CPU);
264 public static final Register q13 = new Register(212, 13, "q13", CPU);
265 public static final Register q14 = new Register(213, 14, "q14", CPU);
266 public static final Register q15 = new Register(214, 15, "q15", CPU);
267 public static final Register q16 = new Register(215, 16, "q16", CPU);
268 public static final Register q17 = new Register(216, 17, "q17", CPU);
269 public static final Register q18 = new Register(217, 18, "q18", CPU);
270 public static final Register q19 = new Register(218, 19, "q19", CPU);
271 public static final Register q20 = new Register(219, 20, "q20", CPU);
272 public static final Register q21 = new Register(220, 21, "q21", CPU);
273 public static final Register q22 = new Register(221, 22, "q22", CPU);
274 public static final Register q23 = new Register(222, 23, "q23", CPU);
275 public static final Register q24 = new Register(223, 24, "q24", CPU);
276 public static final Register q25 = new Register(224, 25, "q25", CPU);
277 public static final Register q26 = new Register(225, 26, "q26", CPU);
278 public static final Register q27 = new Register(226, 27, "q27", CPU);
279 public static final Register q28 = new Register(227, 28, "q28", CPU);
280 public static final Register q29 = new Register(228, 29, "q29", CPU);
281 public static final Register q30 = new Register(229, 30, "q30", CPU);
282 public static final Register q31 = new Register(230, 31, "q31", CPU);
283
284 public static final Register[] cRegisters = { 123 public static final Register[] cRegisters = {
285 c0, c1, c2, c3, c4, c5, c6, c7 124 c0, c1, c2, c3, c4, c5, c6, c7
286 }; 125 };
287 126
288 public static final Register[] sRegisters = { 127 public static final Register[] sRegisters = {
289 s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, 128 s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10,
290 s11, s12, s13, s14, s15, s16, s17, s18, s19, 129 s11, s12, s13, s14, s15, s16, s17, s18, s19,
291 s20, s21, s22, s23, s24, s25, s26, s27, s28, 130 s20, s21, s22, s23, s24, s25, s26, s27, s28,
292 s29, s30, s31, s32, s33, s34, s35, s36, s37, 131 s29, s30, s31
293 s38, s39, s40, s41, s42, s43, s44, s45, s46,
294 s47, s48, s49, s50, s51, s52, s53, s54, s55,
295 s56, s57, s58, s59, s60, s61, s62, s63, s64,
296 s65, s66, s67, s68, s69, s70, s71, s72, s73,
297 s74, s75, s76, s77, s78, s79, s80, s81, s82,
298 s83, s84, s85, s86, s87, s88, s89, s90, s91,
299 s92, s93, s94, s95, s96, s97, s98, s99, s100,
300 s101, s102, s103, s104, s105, s106, s107, s108,
301 s109, s110, s111, s112, s113, s114, s115, s116,
302 s117, s118, s119, s120, s121, s122, s123, s124,
303 s125, s126, s127
304 }; 132 };
305 133
306 public static final Register[] dRegisters = { 134 public static final Register[] dRegisters = {
307 d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, 135 d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15
308 d29, d30, d31, d32, d33, d34, d35, d36, d37, d38, d39, d40, d41, d42, d43, d44, d45, d46, d47, d48, d49, d50, d51, d52, d53, d54, d55,
309 d56, d57, d58, d59, d60, d61, d62, d63
310 }; 136 };
311 137
312 public static final Register[] qRegisters = { 138 public static final Register[] qRegisters = {
313 q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11, q12, q13, q14, q15, q16, q17, q18, q19, q20, q21, q22, q23, q24, q25, q26, q27, q28, q29, q30, q31 139 q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11, q12, q13, q14, q15
314 }; 140 };
315 141
316 public static final Register[] allRegisters = { 142 public static final Register[] allRegisters = {
317 c0, c1, c2, c3, c4, c5, c6, c7, s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, 143 c0, c1, c2, c3, c4, c5, c6, c7, s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15,
318 s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, s32, s33, s34, s35, 144 d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13,
319 s36, s37, s38, s39, s40, s41, s42, s43, s44, s45, s46, s47, s48, s49, s50, s51, s52, 145 d14, d15, q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11,
320 s53, s54, s55, s56, s57, s58, s59, s60, s61, 146 q12, q13, q14, q15
321 s62, s63, s64, s65, s66, s67, s68, s69, s70,
322 s71, s72, s73, s74, s75, s76, s77, s78, s79,
323 s80, s81, s82, s83, s84, s85, s86, s87, s88,
324 s89, s90, s91, s92, s93, s94, s95, s96, s97,
325 s98, s99, s100, s101, s102, s103, s104, s105,
326 s106, s107, s108, s109, s110, s111, s112, s113,
327 s114, s115, s116, s117, s118, s119, s120, s121,
328 s122, s123, s124, s125, s126, s127, d0, d1, d2,
329 d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13,
330 d14, d15, d16, d17, d18, d19, d20, d21, d22, d23,
331 d24, d25, d26, d27, d28, d29, d30, d31, d32, d33,
332 d34, d35, d36, d37, d38, d39, d40, d41, d42, d43,
333 d44, d45, d46, d47, d48, d49, d50, d51, d52, d53,
334 d54, d55, d56, d57, d58, d59, d60, d61, d62, d63,
335 q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11,
336 q12, q13, q14, q15, q16, q17, q18, q19, q20, q21,
337 q22, q23, q24, q25, q26, q27, q28, q29, q30, q31
338 }; 147 };
339 148
340 // @formatter:on 149 // @formatter:on
341 150
342 public HSAIL() { 151 public HSAIL() {
343 super("HSAIL", 8, ByteOrder.LITTLE_ENDIAN, false, allRegisters, LOAD_STORE | STORE_STORE, 1, q31.encoding + 1, 8); 152 super("HSAIL", 8, ByteOrder.LITTLE_ENDIAN, false, allRegisters, 0, 1, q15.encoding + 1, 8);
344 } 153 }
345 154
346 public static int getStackOffset(Value reg) { 155 public static int getStackOffset(Value reg) {
347 return -(((StackSlot) reg).getRawOffset()); 156 return -(((StackSlot) reg).getRawOffset());
348 } 157 }
366 regPrefix = "$d"; 175 regPrefix = "$d";
367 } 176 }
368 switch (argType) { 177 switch (argType) {
369 case "float": 178 case "float":
370 reg = asFloatReg(arg); 179 reg = asFloatReg(arg);
371 encoding = reg.encoding() + 16; 180 encoding = reg.encoding();
372 break; 181 break;
373 case "int": 182 case "int":
374 reg = asIntReg(arg); 183 reg = asIntReg(arg);
375 encoding = reg.encoding(); 184 encoding = reg.encoding();
376 break; 185 break;
378 reg = asLongReg(arg); 187 reg = asLongReg(arg);
379 encoding = reg.encoding(); 188 encoding = reg.encoding();
380 break; 189 break;
381 case "double": 190 case "double":
382 reg = asDoubleReg(arg); 191 reg = asDoubleReg(arg);
383 encoding = reg.encoding() + 16; 192 encoding = reg.encoding();
384 break; 193 break;
385 case "Object": 194 case "Object":
386 reg = asObjectReg(arg); 195 reg = asObjectReg(arg);
387 encoding = reg.encoding(); 196 encoding = reg.encoding();
388 break; 197 break;