Mercurial > hg > truffle
comparison src/cpu/x86/vm/vm_version_x86.hpp @ 4771:22cee0ee8927
Merge
author | kvn |
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date | Fri, 06 Jan 2012 20:09:20 -0800 |
parents | 7ab5f6318694 127b3692c168 |
children | 4a24c4f648bd |
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4755:2b3acb34791f | 4771:22cee0ee8927 |
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76 dca : 1, | 76 dca : 1, |
77 sse4_1 : 1, | 77 sse4_1 : 1, |
78 sse4_2 : 1, | 78 sse4_2 : 1, |
79 : 2, | 79 : 2, |
80 popcnt : 1, | 80 popcnt : 1, |
81 : 8; | 81 : 3, |
82 osxsave : 1, | |
83 avx : 1, | |
84 : 3; | |
82 } bits; | 85 } bits; |
83 }; | 86 }; |
84 | 87 |
85 union StdCpuid1Edx { | 88 union StdCpuid1Edx { |
86 uint32_t value; | 89 uint32_t value; |
166 L1_assoc : 8, | 169 L1_assoc : 8, |
167 L1_size : 8; | 170 L1_size : 8; |
168 } bits; | 171 } bits; |
169 }; | 172 }; |
170 | 173 |
171 union ExtCpuid8Ecx { | |
172 uint32_t value; | |
173 struct { | |
174 uint32_t cores_per_cpu : 8, | |
175 : 24; | |
176 } bits; | |
177 }; | |
178 | |
179 union ExtCpuid7Edx { | 174 union ExtCpuid7Edx { |
180 uint32_t value; | 175 uint32_t value; |
181 struct { | 176 struct { |
182 uint32_t : 8, | 177 uint32_t : 8, |
183 tsc_invariance : 1, | 178 tsc_invariance : 1, |
184 : 23; | 179 : 23; |
180 } bits; | |
181 }; | |
182 | |
183 union ExtCpuid8Ecx { | |
184 uint32_t value; | |
185 struct { | |
186 uint32_t cores_per_cpu : 8, | |
187 : 24; | |
188 } bits; | |
189 }; | |
190 | |
191 union SefCpuid7Eax { | |
192 uint32_t value; | |
193 }; | |
194 | |
195 union SefCpuid7Ebx { | |
196 uint32_t value; | |
197 struct { | |
198 uint32_t fsgsbase : 1, | |
199 : 2, | |
200 bmi1 : 1, | |
201 : 1, | |
202 avx2 : 1, | |
203 : 2, | |
204 bmi2 : 1, | |
205 : 23; | |
206 } bits; | |
207 }; | |
208 | |
209 union XemXcr0Eax { | |
210 uint32_t value; | |
211 struct { | |
212 uint32_t x87 : 1, | |
213 sse : 1, | |
214 ymm : 1, | |
215 : 29; | |
185 } bits; | 216 } bits; |
186 }; | 217 }; |
187 | 218 |
188 protected: | 219 protected: |
189 static int _cpu; | 220 static int _cpu; |
209 CPU_SSE4_1 = (1 << 11), | 240 CPU_SSE4_1 = (1 << 11), |
210 CPU_SSE4_2 = (1 << 12), | 241 CPU_SSE4_2 = (1 << 12), |
211 CPU_POPCNT = (1 << 13), | 242 CPU_POPCNT = (1 << 13), |
212 CPU_LZCNT = (1 << 14), | 243 CPU_LZCNT = (1 << 14), |
213 CPU_TSC = (1 << 15), | 244 CPU_TSC = (1 << 15), |
214 CPU_TSCINV = (1 << 16) | 245 CPU_TSCINV = (1 << 16), |
246 CPU_AVX = (1 << 17), | |
247 CPU_AVX2 = (1 << 18) | |
215 } cpuFeatureFlags; | 248 } cpuFeatureFlags; |
216 | 249 |
217 enum { | 250 enum { |
218 // AMD | 251 // AMD |
219 CPU_FAMILY_AMD_11H = 17, | 252 CPU_FAMILY_AMD_11H = 17, |
248 DcpCpuid4Eax dcp_cpuid4_eax; | 281 DcpCpuid4Eax dcp_cpuid4_eax; |
249 DcpCpuid4Ebx dcp_cpuid4_ebx; | 282 DcpCpuid4Ebx dcp_cpuid4_ebx; |
250 uint32_t dcp_cpuid4_ecx; // unused currently | 283 uint32_t dcp_cpuid4_ecx; // unused currently |
251 uint32_t dcp_cpuid4_edx; // unused currently | 284 uint32_t dcp_cpuid4_edx; // unused currently |
252 | 285 |
286 // cpuid function 7 (structured extended features) | |
287 SefCpuid7Eax sef_cpuid7_eax; | |
288 SefCpuid7Ebx sef_cpuid7_ebx; | |
289 uint32_t sef_cpuid7_ecx; // unused currently | |
290 uint32_t sef_cpuid7_edx; // unused currently | |
291 | |
253 // cpuid function 0xB (processor topology) | 292 // cpuid function 0xB (processor topology) |
254 // ecx = 0 | 293 // ecx = 0 |
255 uint32_t tpl_cpuidB0_eax; | 294 uint32_t tpl_cpuidB0_eax; |
256 TplCpuidBEbx tpl_cpuidB0_ebx; | 295 TplCpuidBEbx tpl_cpuidB0_ebx; |
257 uint32_t tpl_cpuidB0_ecx; // unused currently | 296 uint32_t tpl_cpuidB0_ecx; // unused currently |
301 // cpuid function 0x80000008 | 340 // cpuid function 0x80000008 |
302 uint32_t ext_cpuid8_eax; // unused currently | 341 uint32_t ext_cpuid8_eax; // unused currently |
303 uint32_t ext_cpuid8_ebx; // reserved | 342 uint32_t ext_cpuid8_ebx; // reserved |
304 ExtCpuid8Ecx ext_cpuid8_ecx; | 343 ExtCpuid8Ecx ext_cpuid8_ecx; |
305 uint32_t ext_cpuid8_edx; // reserved | 344 uint32_t ext_cpuid8_edx; // reserved |
345 | |
346 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) | |
347 XemXcr0Eax xem_xcr0_eax; | |
348 uint32_t xem_xcr0_edx; // reserved | |
306 }; | 349 }; |
307 | 350 |
308 // The actual cpuid info block | 351 // The actual cpuid info block |
309 static CpuidInfo _cpuid_info; | 352 static CpuidInfo _cpuid_info; |
310 | 353 |
358 result |= CPU_SSE4_1; | 401 result |= CPU_SSE4_1; |
359 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) | 402 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) |
360 result |= CPU_SSE4_2; | 403 result |= CPU_SSE4_2; |
361 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) | 404 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) |
362 result |= CPU_POPCNT; | 405 result |= CPU_POPCNT; |
406 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && | |
407 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && | |
408 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && | |
409 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { | |
410 result |= CPU_AVX; | |
411 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) | |
412 result |= CPU_AVX2; | |
413 } | |
363 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) | 414 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) |
364 result |= CPU_TSC; | 415 result |= CPU_TSC; |
365 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) | 416 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) |
366 result |= CPU_TSCINV; | 417 result |= CPU_TSCINV; |
367 | 418 |
384 public: | 435 public: |
385 // Offsets for cpuid asm stub | 436 // Offsets for cpuid asm stub |
386 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } | 437 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } |
387 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } | 438 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } |
388 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } | 439 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } |
440 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } | |
389 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } | 441 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } |
390 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } | 442 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } |
391 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } | 443 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } |
392 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } | 444 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } |
393 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } | 445 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } |
394 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } | 446 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } |
395 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } | 447 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } |
448 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } | |
396 | 449 |
397 // Initialization | 450 // Initialization |
398 static void initialize(); | 451 static void initialize(); |
399 | 452 |
400 // Asserts | 453 // Asserts |
481 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } | 534 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } |
482 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } | 535 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } |
483 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } | 536 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } |
484 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } | 537 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } |
485 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } | 538 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } |
539 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; } | |
540 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } | |
486 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } | 541 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } |
487 | 542 |
488 // Intel features | 543 // Intel features |
489 static bool is_intel_family_core() { return is_intel() && | 544 static bool is_intel_family_core() { return is_intel() && |
490 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } | 545 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } |