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comparison src/cpu/x86/vm/vm_version_x86_64.cpp @ 405:2649e5276dd7

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6532536: Optimize arraycopy stubs for Intel cpus Summary: Use SSE2 movdqu in arraycopy stubs on newest Intel's cpus Reviewed-by: rasbold
author kvn
date Tue, 14 Oct 2008 15:10:26 -0700
parents dc7f315e41f7
children
comparison
equal deleted inserted replaced
404:78c058bc5cdc 405:2649e5276dd7
184 _supports_cx8 = supports_cmpxchg8(); 184 _supports_cx8 = supports_cmpxchg8();
185 // OS should support SSE for x64 and hardware should support at least SSE2. 185 // OS should support SSE for x64 and hardware should support at least SSE2.
186 if (!VM_Version::supports_sse2()) { 186 if (!VM_Version::supports_sse2()) {
187 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); 187 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
188 } 188 }
189 if (UseSSE < 4) 189 if (UseSSE < 4) {
190 _cpuFeatures &= ~CPU_SSE4; 190 _cpuFeatures &= ~CPU_SSE4_1;
191 _cpuFeatures &= ~CPU_SSE4_2;
192 }
191 if (UseSSE < 3) { 193 if (UseSSE < 3) {
192 _cpuFeatures &= ~CPU_SSE3; 194 _cpuFeatures &= ~CPU_SSE3;
193 _cpuFeatures &= ~CPU_SSSE3; 195 _cpuFeatures &= ~CPU_SSSE3;
194 _cpuFeatures &= ~CPU_SSE4A; 196 _cpuFeatures &= ~CPU_SSE4A;
195 } 197 }
202 // HT processor could be installed on a system which doesn't support HT. 204 // HT processor could be installed on a system which doesn't support HT.
203 _cpuFeatures &= ~CPU_HT; 205 _cpuFeatures &= ~CPU_HT;
204 } 206 }
205 207
206 char buf[256]; 208 char buf[256];
207 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 209 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
208 cores_per_cpu(), threads_per_core(), 210 cores_per_cpu(), threads_per_core(),
209 cpu_family(), _model, _stepping, 211 cpu_family(), _model, _stepping,
210 (supports_cmov() ? ", cmov" : ""), 212 (supports_cmov() ? ", cmov" : ""),
211 (supports_cmpxchg8() ? ", cx8" : ""), 213 (supports_cmpxchg8() ? ", cx8" : ""),
212 (supports_fxsr() ? ", fxsr" : ""), 214 (supports_fxsr() ? ", fxsr" : ""),
213 (supports_mmx() ? ", mmx" : ""), 215 (supports_mmx() ? ", mmx" : ""),
214 (supports_sse() ? ", sse" : ""), 216 (supports_sse() ? ", sse" : ""),
215 (supports_sse2() ? ", sse2" : ""), 217 (supports_sse2() ? ", sse2" : ""),
216 (supports_sse3() ? ", sse3" : ""), 218 (supports_sse3() ? ", sse3" : ""),
217 (supports_ssse3()? ", ssse3": ""), 219 (supports_ssse3()? ", ssse3": ""),
218 (supports_sse4() ? ", sse4" : ""), 220 (supports_sse4_1() ? ", sse4.1" : ""),
221 (supports_sse4_2() ? ", sse4.2" : ""),
219 (supports_mmx_ext() ? ", mmxext" : ""), 222 (supports_mmx_ext() ? ", mmxext" : ""),
220 (supports_3dnow() ? ", 3dnow" : ""), 223 (supports_3dnow() ? ", 3dnow" : ""),
221 (supports_3dnow2() ? ", 3dnowext" : ""), 224 (supports_3dnow2() ? ", 3dnowext" : ""),
222 (supports_sse4a() ? ", sse4a": ""), 225 (supports_sse4a() ? ", sse4a": ""),
223 (supports_ht() ? ", ht": "")); 226 (supports_ht() ? ", ht": ""));
226 // UseSSE is set to the smaller of what hardware supports and what 229 // UseSSE is set to the smaller of what hardware supports and what
227 // the command line requires. I.e., you cannot set UseSSE to 2 on 230 // the command line requires. I.e., you cannot set UseSSE to 2 on
228 // older Pentiums which do not support it. 231 // older Pentiums which do not support it.
229 if( UseSSE > 4 ) UseSSE=4; 232 if( UseSSE > 4 ) UseSSE=4;
230 if( UseSSE < 0 ) UseSSE=0; 233 if( UseSSE < 0 ) UseSSE=0;
231 if( !supports_sse4() ) // Drop to 3 if no SSE4 support 234 if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support
232 UseSSE = MIN2((intx)3,UseSSE); 235 UseSSE = MIN2((intx)3,UseSSE);
233 if( !supports_sse3() ) // Drop to 2 if no SSE3 support 236 if( !supports_sse3() ) // Drop to 2 if no SSE3 support
234 UseSSE = MIN2((intx)2,UseSSE); 237 UseSSE = MIN2((intx)2,UseSSE);
235 if( !supports_sse2() ) // Drop to 1 if no SSE2 support 238 if( !supports_sse2() ) // Drop to 1 if no SSE2 support
236 UseSSE = MIN2((intx)1,UseSSE); 239 UseSSE = MIN2((intx)1,UseSSE);
312 // generated NOP instructions. 11 is the largest size of one 315 // generated NOP instructions. 11 is the largest size of one
313 // address NOP instruction '0F 1F' (see Assembler::nop(i)). 316 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
314 MaxLoopPad = 11; 317 MaxLoopPad = 11;
315 } 318 }
316 #endif // COMPILER2 319 #endif // COMPILER2
320 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
321 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
322 }
323 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
324 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
325 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
326 }
327 }
317 } 328 }
318 } 329 }
319 330
320 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); 331 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
321 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); 332 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
353 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 364 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
354 PrefetchFieldsAhead = prefetch_fields_ahead(); 365 PrefetchFieldsAhead = prefetch_fields_ahead();
355 366
356 #ifndef PRODUCT 367 #ifndef PRODUCT
357 if (PrintMiscellaneous && Verbose) { 368 if (PrintMiscellaneous && Verbose) {
358 tty->print_cr("Logical CPUs per package: %u", 369 tty->print_cr("Logical CPUs per core: %u",
359 logical_processors_per_package()); 370 logical_processors_per_package());
360 tty->print_cr("UseSSE=%d",UseSSE); 371 tty->print_cr("UseSSE=%d",UseSSE);
361 tty->print("Allocation: "); 372 tty->print("Allocation: ");
362 if (AllocatePrefetchStyle <= 0) { 373 if (AllocatePrefetchStyle <= 0) {
363 tty->print_cr("no prefetching"); 374 tty->print_cr("no prefetching");