truffle: src/cpu/x86/vm/assembler

comparison src/cpu/x86/vm/assembler_x86.hpp @ 625:2f2f54ed12ce

Merge

author	kvn
date	Tue, 10 Mar 2009 08:52:16 -0700
parents	337400e7a5dd
children	660978a2a31a

comparison

equal deleted inserted replaced

-:bcedf688d882
+:2f2f54ed12ce
 /*
-* Copyright 1997-2008 Sun Microsystems, Inc.  All Rights Reserved.
+* Copyright 1997-2009 Sun Microsystems, Inc.  All Rights Reserved.
 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 *
 * This code is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 only, as
 * published by the Free Software Foundation.
 times_2  =  1,
 times_4  =  2,
 times_8  =  3,
 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
 };
+static ScaleFactor times(int size) {
+assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
+if (size == 8)  return times_8;
+if (size == 4)  return times_4;
+if (size == 2)  return times_2;
+return times_1;
+}
+static int scale_size(ScaleFactor scale) {
+assert(scale != no_scale, "");
+assert(((1 << (int)times_1) == 1 &&
+(1 << (int)times_2) == 2 &&
+(1 << (int)times_4) == 4 &&
+(1 << (int)times_8) == 8), "");
+return (1 << (int)scale);
+}
 private:
 Register         _base;
 Register         _index;
 ScaleFactor      _scale;
 _index(index),
 _scale(scale),
 _disp (disp) {
 assert(!index->is_valid() == (scale == Address::no_scale),
 "inconsistent address");
+}
+Address(Register base, RegisterConstant index, ScaleFactor scale = times_1, int disp = 0)
+: _base (base),
+_index(index.register_or_noreg()),
+_scale(scale),
+_disp (disp + (index.constant_or_zero() * scale_size(scale))) {
+if (!index.is_register())  scale = Address::no_scale;
+assert(!_index->is_valid() == (scale == Address::no_scale),
+"inconsistent address");
+}
+Address plus_disp(int disp) const {
+Address a = (*this);
+a._disp += disp;
+return a;
 }
 // The following two overloads are used in connection with the
 // ByteSize type (see sizes.hpp).  They simplify the use of
 // ByteSize'd arguments in assembly code. Note that their equivalent
 _scale(scale),
 _disp(in_bytes(disp)) {
 assert(!index->is_valid() == (scale == Address::no_scale),
 "inconsistent address");
 }
+Address(Register base, RegisterConstant index, ScaleFactor scale, ByteSize disp)
+: _base (base),
+_index(index.register_or_noreg()),
+_scale(scale),
+_disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
+if (!index.is_register())  scale = Address::no_scale;
+assert(!_index->is_valid() == (scale == Address::no_scale),
+"inconsistent address");
+}
 #endif // ASSERT
 // accessors
 bool        uses(Register reg) const { return _base == reg || _index == reg; }
 Register    base()             const { return _base;  }
 int         disp()             const { return _disp;  }
 // Convert the raw encoding form into the form expected by the constructor for
 // Address.  An index of 4 (rsp) corresponds to having no index, so convert
 // that to noreg for the Address constructor.
-static Address make_raw(int base, int index, int scale, int disp);
+static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
 static Address make_array(ArrayAddress);
 private:
 bool base_needs_rex() const {
 return _base != noreg && _base->encoding() >= 8;
 }
 void movsbl(Register dst, Address src);
 void movsbl(Register dst, Register src);
 #ifdef _LP64
+void movsbq(Register dst, Address src);
+void movsbq(Register dst, Register src);
 // Move signed 32bit immediate to 64bit extending sign
 void movslq(Address dst, int32_t imm64);
 void movslq(Register dst, int32_t imm64);
 void movslq(Register dst, Address src);
 #endif
 void movswl(Register dst, Address src);
 void movswl(Register dst, Register src);
+#ifdef _LP64
+void movswq(Register dst, Address src);
+void movswq(Register dst, Register src);
+#endif
 void movw(Address dst, int imm16);
 void movw(Register dst, Address src);
 void movw(Address dst, Register src);
 void movzbl(Register dst, Address src);
 void movzbl(Register dst, Register src);
+#ifdef _LP64
+void movzbq(Register dst, Address src);
+void movzbq(Register dst, Register src);
+#endif
 void movzwl(Register dst, Address src);
 void movzwl(Register dst, Register src);
+#ifdef _LP64
+void movzwq(Register dst, Address src);
+void movzwq(Register dst, Register src);
+#endif
 void mull(Address src);
 void mull(Register src);
 // Multiply Scalar Double-Precision Floating-Point Values
 static void pd_print_patched_instruction(address branch);
 #endif
 // The following 4 methods return the offset of the appropriate move instruction
-// Support for fast byte/word loading with zero extension (depending on particular CPU)
+// Support for fast byte/short loading with zero extension (depending on particular CPU)
 int load_unsigned_byte(Register dst, Address src);
-int load_unsigned_word(Register dst, Address src);
+int load_unsigned_short(Register dst, Address src);
-// Support for fast byte/word loading with sign extension (depending on particular CPU)
+// Support for fast byte/short loading with sign extension (depending on particular CPU)
 int load_signed_byte(Register dst, Address src);
-int load_signed_word(Register dst, Address src);
+int load_signed_short(Register dst, Address src);
 // Support for sign-extension (hi:lo = extend_sign(lo))
 void extend_sign(Register hi, Register lo);
+// Loading values by size and signed-ness
+void load_sized_value(Register dst, Address src, int size_in_bytes, bool is_signed);
 // Support for inc/dec with optimal instruction selection depending on value
 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
 Register t2,                       // temp register
 Label&   slow_case                 // continuation point if fast allocation fails
 );
 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
+// interface method calling
+void lookup_interface_method(Register recv_klass,
+Register intf_klass,
+RegisterConstant itable_index,
+Register method_result,
+Register scan_temp,
+Label& no_such_interface);
 //----
 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
 // Debugging
 }
 // Writes to stack successive pages until offset reached to check for
 // stack overflow + shadow pages.  Also, clobbers tmp
 void bang_stack_size(Register size, Register tmp);
+virtual RegisterConstant delayed_value(intptr_t* delayed_value_addr,
+Register tmp,
+int offset);
 // Support for serializing memory accesses between threads
 void serialize_memory(Register thread, Register tmp);
 void verify_tlab();

Mercurial > hg > truffle

comparison src/cpu/x86/vm/assembler_x86.hpp @ 625:2f2f54ed12ce