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comparison src/cpu/sparc/vm/assembler_sparc.hpp @ 14263:30f8cd8b43dd

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Merge
author anoll
date Tue, 14 Jan 2014 21:33:33 -0800
parents 00f5eff62d18
children 4ca6dc0799b6 17b2fbdb6637
comparison
equal deleted inserted replaced
14262:3aaa4b9966f6 14263:30f8cd8b43dd
86 subcc_op3 = 0x14, 86 subcc_op3 = 0x14,
87 andncc_op3 = 0x15, 87 andncc_op3 = 0x15,
88 orncc_op3 = 0x16, 88 orncc_op3 = 0x16,
89 xnorcc_op3 = 0x17, 89 xnorcc_op3 = 0x17,
90 addccc_op3 = 0x18, 90 addccc_op3 = 0x18,
91 aes4_op3 = 0x19,
91 umulcc_op3 = 0x1a, 92 umulcc_op3 = 0x1a,
92 smulcc_op3 = 0x1b, 93 smulcc_op3 = 0x1b,
93 subccc_op3 = 0x1c, 94 subccc_op3 = 0x1c,
94 udivcc_op3 = 0x1e, 95 udivcc_op3 = 0x1e,
95 sdivcc_op3 = 0x1f, 96 sdivcc_op3 = 0x1f,
119 saved_op3 = 0x31, 120 saved_op3 = 0x31,
120 121
121 fpop1_op3 = 0x34, 122 fpop1_op3 = 0x34,
122 fpop2_op3 = 0x35, 123 fpop2_op3 = 0x35,
123 impdep1_op3 = 0x36, 124 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36,
126 flog3_op3 = 0x36,
124 impdep2_op3 = 0x37, 127 impdep2_op3 = 0x37,
125 jmpl_op3 = 0x38, 128 jmpl_op3 = 0x38,
126 rett_op3 = 0x39, 129 rett_op3 = 0x39,
127 trap_op3 = 0x3a, 130 trap_op3 = 0x3a,
128 flush_op3 = 0x3b, 131 flush_op3 = 0x3b,
170 cc_bit_op3 = 0x10 173 cc_bit_op3 = 0x10
171 }; 174 };
172 175
173 enum opfs { 176 enum opfs {
174 // selected opfs 177 // selected opfs
175 fmovs_opf = 0x01, 178 fmovs_opf = 0x01,
176 fmovd_opf = 0x02, 179 fmovd_opf = 0x02,
177 180
178 fnegs_opf = 0x05, 181 fnegs_opf = 0x05,
179 fnegd_opf = 0x06, 182 fnegd_opf = 0x06,
180 183
181 fadds_opf = 0x41, 184 fadds_opf = 0x41,
182 faddd_opf = 0x42, 185 faddd_opf = 0x42,
183 fsubs_opf = 0x45, 186 fsubs_opf = 0x45,
184 fsubd_opf = 0x46, 187 fsubd_opf = 0x46,
185 188
186 fmuls_opf = 0x49, 189 fmuls_opf = 0x49,
187 fmuld_opf = 0x4a, 190 fmuld_opf = 0x4a,
188 fdivs_opf = 0x4d, 191 fdivs_opf = 0x4d,
189 fdivd_opf = 0x4e, 192 fdivd_opf = 0x4e,
190 193
191 fcmps_opf = 0x51, 194 fcmps_opf = 0x51,
192 fcmpd_opf = 0x52, 195 fcmpd_opf = 0x52,
193 196
194 fstox_opf = 0x81, 197 fstox_opf = 0x81,
195 fdtox_opf = 0x82, 198 fdtox_opf = 0x82,
196 fxtos_opf = 0x84, 199 fxtos_opf = 0x84,
197 fxtod_opf = 0x88, 200 fxtod_opf = 0x88,
198 fitos_opf = 0xc4, 201 fitos_opf = 0xc4,
199 fdtos_opf = 0xc6, 202 fdtos_opf = 0xc6,
200 fitod_opf = 0xc8, 203 fitod_opf = 0xc8,
201 fstod_opf = 0xc9, 204 fstod_opf = 0xc9,
202 fstoi_opf = 0xd1, 205 fstoi_opf = 0xd1,
203 fdtoi_opf = 0xd2, 206 fdtoi_opf = 0xd2,
204 207
205 mdtox_opf = 0x110, 208 mdtox_opf = 0x110,
206 mstouw_opf = 0x111, 209 mstouw_opf = 0x111,
207 mstosw_opf = 0x113, 210 mstosw_opf = 0x113,
208 mxtod_opf = 0x118, 211 mxtod_opf = 0x118,
209 mwtos_opf = 0x119 212 mwtos_opf = 0x119,
213
214 aes_kexpand0_opf = 0x130,
215 aes_kexpand2_opf = 0x131
216 };
217
218 enum op5s {
219 aes_eround01_op5 = 0x00,
220 aes_eround23_op5 = 0x01,
221 aes_dround01_op5 = 0x02,
222 aes_dround23_op5 = 0x03,
223 aes_eround01_l_op5 = 0x04,
224 aes_eround23_l_op5 = 0x05,
225 aes_dround01_l_op5 = 0x06,
226 aes_dround23_l_op5 = 0x07,
227 aes_kexpand1_op5 = 0x08
210 }; 228 };
211 229
212 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez }; 230 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
213 231
214 enum Condition { 232 enum Condition {
425 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); } 443 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
426 static int imm_asi( int x) { return u_field(x, 12, 5); } 444 static int imm_asi( int x) { return u_field(x, 12, 5); }
427 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); } 445 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
428 static int opf_low6( int w) { return u_field(w, 10, 5); } 446 static int opf_low6( int w) { return u_field(w, 10, 5); }
429 static int opf_low5( int w) { return u_field(w, 9, 5); } 447 static int opf_low5( int w) { return u_field(w, 9, 5); }
448 static int op5( int x) { return u_field(x, 8, 5); }
430 static int trapcc( CC cc) { return u_field(cc, 12, 11); } 449 static int trapcc( CC cc) { return u_field(cc, 12, 11); }
431 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit 450 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
432 static int opf( int x) { return u_field(x, 13, 5); } 451 static int opf( int x) { return u_field(x, 13, 5); }
433 452
434 static bool is_cbcond( int x ) { 453 static bool is_cbcond( int x ) {
449 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); } 468 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
450 469
451 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); }; 470 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
452 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); }; 471 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
453 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); }; 472 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
473 static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
454 474
455 // some float instructions use this encoding on the op3 field 475 // some float instructions use this encoding on the op3 field
456 static int alt_op3(int op, FloatRegisterImpl::Width w) { 476 static int alt_op3(int op, FloatRegisterImpl::Width w) {
457 int r; 477 int r;
458 switch(w) { 478 switch(w) {
557 // create a low10 __value__ (not a field) for a given a 32-bit constant 577 // create a low10 __value__ (not a field) for a given a 32-bit constant
558 static int low10( int x ) { 578 static int low10( int x ) {
559 return x & ((1 << 10) - 1); 579 return x & ((1 << 10) - 1);
560 } 580 }
561 581
582 // AES crypto instructions supported only on certain processors
583 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
584
585 // instruction only in VIS1
586 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
587
562 // instruction only in VIS3 588 // instruction only in VIS3
563 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); } 589 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
564 590
565 // instruction only in v9 591 // instruction only in v9
566 static void v9_only() { } // do nothing 592 static void v9_only() { } // do nothing
680 void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 706 void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
681 void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 707 void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
682 void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 708 void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
683 709
684 710
711 // 4-operand AES instructions
712
713 void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
714 void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
715 void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
716 void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
717 void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
718 void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
719 void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
720 void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
721 void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D) ); }
722
723
724 // 3-operand AES instructions
725
726 void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D) ); }
727 void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D) ); }
728
685 // pp 136 729 // pp 136
686 730
687 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none); 731 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
688 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L); 732 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
689 733
781 // pp 163 825 // pp 163
782 826
783 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); } 827 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); }
784 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); } 828 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
785 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); } 829 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
830
831 // FXORs/FXORd instructions
832
833 void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); }
786 834
787 // pp 164 835 // pp 164
788 836
789 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); } 837 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
790 838