Mercurial > hg > truffle
comparison src/cpu/sparc/vm/assembler_sparc.cpp @ 794:315a5d70b295
6484957: G1: parallel concurrent refinement
6826318: G1: remove traversal-based refinement code
Summary: Removed traversal-based refinement code as it's no longer used. Made the concurrent refinement (queue-based) parallel.
Reviewed-by: tonyp
author | iveresov |
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date | Mon, 11 May 2009 16:30:56 -0700 |
parents | 6b2273dd6fa9 |
children | df6caf649ff7 |
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758:9b3a41ccc927 | 794:315a5d70b295 |
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4452 // XXX Should I predict this taken or not? Does it mattern? | 4452 // XXX Should I predict this taken or not? Does it mattern? |
4453 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered); | 4453 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered); |
4454 delayed()->nop(); | 4454 delayed()->nop(); |
4455 } | 4455 } |
4456 | 4456 |
4457 // Now we decide how to generate the card table write. If we're | 4457 // If the "store_addr" register is an "in" or "local" register, move it to |
4458 // enqueueing, we call out to a generated function. Otherwise, we do it | 4458 // a scratch reg so we can pass it as an argument. |
4459 // inline here. | 4459 bool use_scr = !(store_addr->is_global() || store_addr->is_out()); |
4460 | 4460 // Pick a scratch register different from "tmp". |
4461 if (G1RSBarrierUseQueue) { | 4461 Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch); |
4462 // If the "store_addr" register is an "in" or "local" register, move it to | 4462 // Make sure we use up the delay slot! |
4463 // a scratch reg so we can pass it as an argument. | 4463 if (use_scr) { |
4464 bool use_scr = !(store_addr->is_global() || store_addr->is_out()); | 4464 post_filter_masm->mov(store_addr, scr); |
4465 // Pick a scratch register different from "tmp". | |
4466 Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch); | |
4467 // Make sure we use up the delay slot! | |
4468 if (use_scr) { | |
4469 post_filter_masm->mov(store_addr, scr); | |
4470 } else { | |
4471 post_filter_masm->nop(); | |
4472 } | |
4473 generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base); | |
4474 save_frame(0); | |
4475 call(dirty_card_log_enqueue); | |
4476 if (use_scr) { | |
4477 delayed()->mov(scr, O0); | |
4478 } else { | |
4479 delayed()->mov(store_addr->after_save(), O0); | |
4480 } | |
4481 restore(); | |
4482 | |
4483 } else { | 4465 } else { |
4484 | 4466 post_filter_masm->nop(); |
4485 #ifdef _LP64 | 4467 } |
4486 post_filter_masm->srlx(store_addr, CardTableModRefBS::card_shift, store_addr); | 4468 generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base); |
4487 #else | 4469 save_frame(0); |
4488 post_filter_masm->srl(store_addr, CardTableModRefBS::card_shift, store_addr); | 4470 call(dirty_card_log_enqueue); |
4489 #endif | 4471 if (use_scr) { |
4490 assert(tmp != store_addr, "need separate temp reg"); | 4472 delayed()->mov(scr, O0); |
4491 set(bs->byte_map_base, tmp); | 4473 } else { |
4492 stb(G0, tmp, store_addr); | 4474 delayed()->mov(store_addr->after_save(), O0); |
4493 } | 4475 } |
4476 restore(); | |
4494 | 4477 |
4495 bind(filtered); | 4478 bind(filtered); |
4496 | 4479 |
4497 } | 4480 } |
4498 | 4481 |