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comparison src/cpu/x86/vm/assembler_x86.cpp @ 1060:323bd24c6520

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6769124: various 64-bit fixes for c1 Reviewed-by: never
author roland
date Mon, 02 Nov 2009 11:17:55 +0100
parents d40f03b57795
children 2f1ec89b9995
comparison
equal deleted inserted replaced
1059:389049f3f393 1060:323bd24c6520
2249 2249
2250 void Assembler::popf() { 2250 void Assembler::popf() {
2251 emit_byte(0x9D); 2251 emit_byte(0x9D);
2252 } 2252 }
2253 2253
2254 #ifndef _LP64 // no 32bit push/pop on amd64
2254 void Assembler::popl(Address dst) { 2255 void Assembler::popl(Address dst) {
2255 // NOTE: this will adjust stack by 8byte on 64bits 2256 // NOTE: this will adjust stack by 8byte on 64bits
2256 InstructionMark im(this); 2257 InstructionMark im(this);
2257 prefix(dst); 2258 prefix(dst);
2258 emit_byte(0x8F); 2259 emit_byte(0x8F);
2259 emit_operand(rax, dst); 2260 emit_operand(rax, dst);
2260 } 2261 }
2262 #endif
2261 2263
2262 void Assembler::prefetch_prefix(Address src) { 2264 void Assembler::prefetch_prefix(Address src) {
2263 prefix(src); 2265 prefix(src);
2264 emit_byte(0x0F); 2266 emit_byte(0x0F);
2265 } 2267 }
2426 2428
2427 void Assembler::pushf() { 2429 void Assembler::pushf() {
2428 emit_byte(0x9C); 2430 emit_byte(0x9C);
2429 } 2431 }
2430 2432
2433 #ifndef _LP64 // no 32bit push/pop on amd64
2431 void Assembler::pushl(Address src) { 2434 void Assembler::pushl(Address src) {
2432 // Note this will push 64bit on 64bit 2435 // Note this will push 64bit on 64bit
2433 InstructionMark im(this); 2436 InstructionMark im(this);
2434 prefix(src); 2437 prefix(src);
2435 emit_byte(0xFF); 2438 emit_byte(0xFF);
2436 emit_operand(rsi, src); 2439 emit_operand(rsi, src);
2437 } 2440 }
2441 #endif
2438 2442
2439 void Assembler::pxor(XMMRegister dst, Address src) { 2443 void Assembler::pxor(XMMRegister dst, Address src) {
2440 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2444 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2441 InstructionMark im(this); 2445 InstructionMark im(this);
2442 emit_byte(0x66); 2446 emit_byte(0x66);
5589 nop(modulus - (offset() % modulus)); 5593 nop(modulus - (offset() % modulus));
5590 } 5594 }
5591 } 5595 }
5592 5596
5593 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { 5597 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
5594 andpd(dst, as_Address(src)); 5598 if (reachable(src)) {
5599 andpd(dst, as_Address(src));
5600 } else {
5601 lea(rscratch1, src);
5602 andpd(dst, Address(rscratch1, 0));
5603 }
5595 } 5604 }
5596 5605
5597 void MacroAssembler::andptr(Register dst, int32_t imm32) { 5606 void MacroAssembler::andptr(Register dst, int32_t imm32) {
5598 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 5607 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
5599 } 5608 }
6076 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 6085 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
6077 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 6086 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
6078 } 6087 }
6079 6088
6080 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { 6089 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
6081 comisd(dst, as_Address(src)); 6090 if (reachable(src)) {
6091 comisd(dst, as_Address(src));
6092 } else {
6093 lea(rscratch1, src);
6094 comisd(dst, Address(rscratch1, 0));
6095 }
6082 } 6096 }
6083 6097
6084 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { 6098 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
6085 comiss(dst, as_Address(src)); 6099 if (reachable(src)) {
6100 comiss(dst, as_Address(src));
6101 } else {
6102 lea(rscratch1, src);
6103 comiss(dst, Address(rscratch1, 0));
6104 }
6086 } 6105 }
6087 6106
6088 6107
6089 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { 6108 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
6090 Condition negated_cond = negate_condition(cond); 6109 Condition negated_cond = negate_condition(cond);