Mercurial > hg > truffle
comparison src/cpu/x86/vm/assembler_x86.cpp @ 4970:33df1aeaebbf
Merge with http://hg.openjdk.java.net/hsx/hsx24/hotspot/
author | Thomas Wuerthinger <thomas.wuerthinger@oracle.com> |
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date | Mon, 27 Feb 2012 13:10:13 +0100 |
parents | 04b9a2566eec fd8114661503 |
children | 957c266d8bc5 |
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4703:2cfb7fb2dce7 | 4970:33df1aeaebbf |
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1 /* | 1 /* |
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. | 2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | 4 * |
5 * This code is free software; you can redistribute it and/or modify it | 5 * This code is free software; you can redistribute it and/or modify it |
6 * under the terms of the GNU General Public License version 2 only, as | 6 * under the terms of the GNU General Public License version 2 only, as |
7 * published by the Free Software Foundation. | 7 * published by the Free Software Foundation. |
232 } else { | 232 } else { |
233 emit_byte(op1); | 233 emit_byte(op1); |
234 emit_byte(op2 | encode(dst)); | 234 emit_byte(op2 | encode(dst)); |
235 emit_long(imm32); | 235 emit_long(imm32); |
236 } | 236 } |
237 } | |
238 | |
239 // Force generation of a 4 byte immediate value even if it fits into 8bit | |
240 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { | |
241 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
242 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
243 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
244 emit_byte(op1); | |
245 emit_byte(op2 | encode(dst)); | |
246 emit_long(imm32); | |
237 } | 247 } |
238 | 248 |
239 // immediate-to-memory forms | 249 // immediate-to-memory forms |
240 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { | 250 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
241 assert((op1 & 0x01) == 1, "should be 32bit operation"); | 251 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
531 debug_only(has_disp32 = true); // has both kinds of operands! | 541 debug_only(has_disp32 = true); // has both kinds of operands! |
532 break; | 542 break; |
533 | 543 |
534 case 0x0F: // movx..., etc. | 544 case 0x0F: // movx..., etc. |
535 switch (0xFF & *ip++) { | 545 switch (0xFF & *ip++) { |
546 case 0x3A: // pcmpestri | |
547 tail_size = 1; | |
548 case 0x38: // ptest, pmovzxbw | |
549 ip++; // skip opcode | |
550 debug_only(has_disp32 = true); // has both kinds of operands! | |
551 break; | |
552 | |
553 case 0x70: // pshufd r, r/a, #8 | |
554 debug_only(has_disp32 = true); // has both kinds of operands! | |
555 case 0x73: // psrldq r, #8 | |
556 tail_size = 1; | |
557 break; | |
558 | |
536 case 0x12: // movlps | 559 case 0x12: // movlps |
537 case 0x28: // movaps | 560 case 0x28: // movaps |
538 case 0x2E: // ucomiss | 561 case 0x2E: // ucomiss |
539 case 0x2F: // comiss | 562 case 0x2F: // comiss |
540 case 0x54: // andps | 563 case 0x54: // andps |
541 case 0x55: // andnps | 564 case 0x55: // andnps |
542 case 0x56: // orps | 565 case 0x56: // orps |
543 case 0x57: // xorps | 566 case 0x57: // xorps |
544 case 0x6E: // movd | 567 case 0x6E: // movd |
545 case 0x7E: // movd | 568 case 0x7E: // movd |
546 case 0xAE: // ldmxcsr a | 569 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush |
547 // 64bit side says it these have both operands but that doesn't | |
548 // appear to be true | |
549 debug_only(has_disp32 = true); | 570 debug_only(has_disp32 = true); |
550 break; | 571 break; |
551 | 572 |
552 case 0xAD: // shrd r, a, %cl | 573 case 0xAD: // shrd r, a, %cl |
553 case 0xAF: // imul r, a | 574 case 0xAF: // imul r, a |
563 case REP16(0x90): // setcc a | 584 case REP16(0x90): // setcc a |
564 debug_only(has_disp32 = true); | 585 debug_only(has_disp32 = true); |
565 // fall out of the switch to decode the address | 586 // fall out of the switch to decode the address |
566 break; | 587 break; |
567 | 588 |
589 case 0xC4: // pinsrw r, a, #8 | |
590 debug_only(has_disp32 = true); | |
591 case 0xC5: // pextrw r, r, #8 | |
592 tail_size = 1; // the imm8 | |
593 break; | |
594 | |
568 case 0xAC: // shrd r, a, #8 | 595 case 0xAC: // shrd r, a, #8 |
569 debug_only(has_disp32 = true); | 596 debug_only(has_disp32 = true); |
570 tail_size = 1; // the imm8 | 597 tail_size = 1; // the imm8 |
571 break; | 598 break; |
572 | 599 |
623 case 0x6B: // imul r, a, #8 | 650 case 0x6B: // imul r, a, #8 |
624 debug_only(has_disp32 = true); // has both kinds of operands! | 651 debug_only(has_disp32 = true); // has both kinds of operands! |
625 tail_size = 1; // the imm8 | 652 tail_size = 1; // the imm8 |
626 break; | 653 break; |
627 | 654 |
628 case 0xE8: // call rdisp32 | 655 case 0xC4: // VEX_3bytes |
629 case 0xE9: // jmp rdisp32 | 656 case 0xC5: // VEX_2bytes |
630 if (which == end_pc_operand) return ip + 4; | 657 assert((UseAVX > 0), "shouldn't have VEX prefix"); |
631 assert(which == call32_operand, "call has no disp32 or imm"); | 658 assert(ip == inst+1, "no prefixes allowed"); |
632 return ip; | 659 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions |
660 // but they have prefix 0x0F and processed when 0x0F processed above. | |
661 // | |
662 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES | |
663 // instructions (these instructions are not supported in 64-bit mode). | |
664 // To distinguish them bits [7:6] are set in the VEX second byte since | |
665 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set | |
666 // those VEX bits REX and vvvv bits are inverted. | |
667 // | |
668 // Fortunately C2 doesn't generate these instructions so we don't need | |
669 // to check for them in product version. | |
670 | |
671 // Check second byte | |
672 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); | |
673 | |
674 // First byte | |
675 if ((0xFF & *inst) == VEX_3bytes) { | |
676 ip++; // third byte | |
677 is_64bit = ((VEX_W & *ip) == VEX_W); | |
678 } | |
679 ip++; // opcode | |
680 // To find the end of instruction (which == end_pc_operand). | |
681 switch (0xFF & *ip) { | |
682 case 0x61: // pcmpestri r, r/a, #8 | |
683 case 0x70: // pshufd r, r/a, #8 | |
684 case 0x73: // psrldq r, #8 | |
685 tail_size = 1; // the imm8 | |
686 break; | |
687 default: | |
688 break; | |
689 } | |
690 ip++; // skip opcode | |
691 debug_only(has_disp32 = true); // has both kinds of operands! | |
692 break; | |
633 | 693 |
634 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | 694 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 |
635 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | 695 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl |
636 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | 696 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a |
637 case 0xDD: // fld_d a; fst_d a; fstp_d a | 697 case 0xDD: // fld_d a; fst_d a; fstp_d a |
640 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | 700 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a |
641 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | 701 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a |
642 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | 702 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a |
643 debug_only(has_disp32 = true); | 703 debug_only(has_disp32 = true); |
644 break; | 704 break; |
705 | |
706 case 0xE8: // call rdisp32 | |
707 case 0xE9: // jmp rdisp32 | |
708 if (which == end_pc_operand) return ip + 4; | |
709 assert(which == call32_operand, "call has no disp32 or imm"); | |
710 return ip; | |
645 | 711 |
646 case 0xF0: // Lock | 712 case 0xF0: // Lock |
647 assert(os::is_MP(), "only on MP"); | 713 assert(os::is_MP(), "only on MP"); |
648 goto again_after_prefix; | 714 goto again_after_prefix; |
649 | 715 |
881 (void) prefix_and_encode(dst->encoding(), src->encoding()); | 947 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
882 emit_arith(0x03, 0xC0, dst, src); | 948 emit_arith(0x03, 0xC0, dst, src); |
883 } | 949 } |
884 | 950 |
885 void Assembler::addr_nop_4() { | 951 void Assembler::addr_nop_4() { |
952 assert(UseAddressNop, "no CPU support"); | |
886 // 4 bytes: NOP DWORD PTR [EAX+0] | 953 // 4 bytes: NOP DWORD PTR [EAX+0] |
887 emit_byte(0x0F); | 954 emit_byte(0x0F); |
888 emit_byte(0x1F); | 955 emit_byte(0x1F); |
889 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); | 956 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); |
890 emit_byte(0); // 8-bits offset (1 byte) | 957 emit_byte(0); // 8-bits offset (1 byte) |
891 } | 958 } |
892 | 959 |
893 void Assembler::addr_nop_5() { | 960 void Assembler::addr_nop_5() { |
961 assert(UseAddressNop, "no CPU support"); | |
894 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset | 962 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset |
895 emit_byte(0x0F); | 963 emit_byte(0x0F); |
896 emit_byte(0x1F); | 964 emit_byte(0x1F); |
897 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); | 965 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); |
898 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | 966 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); |
899 emit_byte(0); // 8-bits offset (1 byte) | 967 emit_byte(0); // 8-bits offset (1 byte) |
900 } | 968 } |
901 | 969 |
902 void Assembler::addr_nop_7() { | 970 void Assembler::addr_nop_7() { |
971 assert(UseAddressNop, "no CPU support"); | |
903 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset | 972 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset |
904 emit_byte(0x0F); | 973 emit_byte(0x0F); |
905 emit_byte(0x1F); | 974 emit_byte(0x1F); |
906 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); | 975 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); |
907 emit_long(0); // 32-bits offset (4 bytes) | 976 emit_long(0); // 32-bits offset (4 bytes) |
908 } | 977 } |
909 | 978 |
910 void Assembler::addr_nop_8() { | 979 void Assembler::addr_nop_8() { |
980 assert(UseAddressNop, "no CPU support"); | |
911 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset | 981 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset |
912 emit_byte(0x0F); | 982 emit_byte(0x0F); |
913 emit_byte(0x1F); | 983 emit_byte(0x1F); |
914 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); | 984 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); |
915 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | 985 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); |
916 emit_long(0); // 32-bits offset (4 bytes) | 986 emit_long(0); // 32-bits offset (4 bytes) |
917 } | 987 } |
918 | 988 |
919 void Assembler::addsd(XMMRegister dst, XMMRegister src) { | 989 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
920 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 990 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
921 emit_byte(0xF2); | 991 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
922 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
923 emit_byte(0x0F); | |
924 emit_byte(0x58); | 992 emit_byte(0x58); |
925 emit_byte(0xC0 | encode); | 993 emit_byte(0xC0 | encode); |
926 } | 994 } |
927 | 995 |
928 void Assembler::addsd(XMMRegister dst, Address src) { | 996 void Assembler::addsd(XMMRegister dst, Address src) { |
929 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 997 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
930 InstructionMark im(this); | 998 InstructionMark im(this); |
931 emit_byte(0xF2); | 999 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
932 prefix(src, dst); | |
933 emit_byte(0x0F); | |
934 emit_byte(0x58); | 1000 emit_byte(0x58); |
935 emit_operand(dst, src); | 1001 emit_operand(dst, src); |
936 } | 1002 } |
937 | 1003 |
938 void Assembler::addss(XMMRegister dst, XMMRegister src) { | 1004 void Assembler::addss(XMMRegister dst, XMMRegister src) { |
939 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1005 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
940 emit_byte(0xF3); | 1006 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
941 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
942 emit_byte(0x0F); | |
943 emit_byte(0x58); | 1007 emit_byte(0x58); |
944 emit_byte(0xC0 | encode); | 1008 emit_byte(0xC0 | encode); |
945 } | 1009 } |
946 | 1010 |
947 void Assembler::addss(XMMRegister dst, Address src) { | 1011 void Assembler::addss(XMMRegister dst, Address src) { |
948 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1012 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
949 InstructionMark im(this); | 1013 InstructionMark im(this); |
950 emit_byte(0xF3); | 1014 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
951 prefix(src, dst); | |
952 emit_byte(0x0F); | |
953 emit_byte(0x58); | 1015 emit_byte(0x58); |
954 emit_operand(dst, src); | 1016 emit_operand(dst, src); |
1017 } | |
1018 | |
1019 void Assembler::andl(Address dst, int32_t imm32) { | |
1020 InstructionMark im(this); | |
1021 prefix(dst); | |
1022 emit_byte(0x81); | |
1023 emit_operand(rsp, dst, 4); | |
1024 emit_long(imm32); | |
955 } | 1025 } |
956 | 1026 |
957 void Assembler::andl(Register dst, int32_t imm32) { | 1027 void Assembler::andl(Register dst, int32_t imm32) { |
958 prefix(dst); | 1028 prefix(dst); |
959 emit_arith(0x81, 0xE0, dst, imm32); | 1029 emit_arith(0x81, 0xE0, dst, imm32); |
972 } | 1042 } |
973 | 1043 |
974 void Assembler::andpd(XMMRegister dst, Address src) { | 1044 void Assembler::andpd(XMMRegister dst, Address src) { |
975 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1045 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
976 InstructionMark im(this); | 1046 InstructionMark im(this); |
977 emit_byte(0x66); | 1047 simd_prefix(dst, dst, src, VEX_SIMD_66); |
978 prefix(src, dst); | |
979 emit_byte(0x0F); | |
980 emit_byte(0x54); | 1048 emit_byte(0x54); |
981 emit_operand(dst, src); | 1049 emit_operand(dst, src); |
1050 } | |
1051 | |
1052 void Assembler::andpd(XMMRegister dst, XMMRegister src) { | |
1053 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1054 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | |
1055 emit_byte(0x54); | |
1056 emit_byte(0xC0 | encode); | |
1057 } | |
1058 | |
1059 void Assembler::andps(XMMRegister dst, Address src) { | |
1060 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1061 InstructionMark im(this); | |
1062 simd_prefix(dst, dst, src, VEX_SIMD_NONE); | |
1063 emit_byte(0x54); | |
1064 emit_operand(dst, src); | |
1065 } | |
1066 | |
1067 void Assembler::andps(XMMRegister dst, XMMRegister src) { | |
1068 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1069 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE); | |
1070 emit_byte(0x54); | |
1071 emit_byte(0xC0 | encode); | |
982 } | 1072 } |
983 | 1073 |
984 void Assembler::bsfl(Register dst, Register src) { | 1074 void Assembler::bsfl(Register dst, Register src) { |
985 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 1075 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
986 emit_byte(0x0F); | 1076 emit_byte(0x0F); |
1023 emit_data(int(0), rtype, operand); | 1113 emit_data(int(0), rtype, operand); |
1024 } | 1114 } |
1025 } | 1115 } |
1026 | 1116 |
1027 void Assembler::call(Register dst) { | 1117 void Assembler::call(Register dst) { |
1028 // This was originally using a 32bit register encoding | 1118 int encode = prefix_and_encode(dst->encoding()); |
1029 // and surely we want 64bit! | |
1030 // this is a 32bit encoding but in 64bit mode the default | |
1031 // operand size is 64bit so there is no need for the | |
1032 // wide prefix. So prefix only happens if we use the | |
1033 // new registers. Much like push/pop. | |
1034 int x = offset(); | |
1035 // this may be true but dbx disassembles it as if it | |
1036 // were 32bits... | |
1037 // int encode = prefix_and_encode(dst->encoding()); | |
1038 // if (offset() != x) assert(dst->encoding() >= 8, "what?"); | |
1039 int encode = prefixq_and_encode(dst->encoding()); | |
1040 | |
1041 emit_byte(0xFF); | 1119 emit_byte(0xFF); |
1042 emit_byte(0xD0 | encode); | 1120 emit_byte(0xD0 | encode); |
1043 } | 1121 } |
1044 | 1122 |
1045 | 1123 |
1155 | 1233 |
1156 void Assembler::comisd(XMMRegister dst, Address src) { | 1234 void Assembler::comisd(XMMRegister dst, Address src) { |
1157 // NOTE: dbx seems to decode this as comiss even though the | 1235 // NOTE: dbx seems to decode this as comiss even though the |
1158 // 0x66 is there. Strangly ucomisd comes out correct | 1236 // 0x66 is there. Strangly ucomisd comes out correct |
1159 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1237 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1160 emit_byte(0x66); | 1238 InstructionMark im(this); |
1161 comiss(dst, src); | 1239 simd_prefix(dst, src, VEX_SIMD_66); |
1240 emit_byte(0x2F); | |
1241 emit_operand(dst, src); | |
1242 } | |
1243 | |
1244 void Assembler::comisd(XMMRegister dst, XMMRegister src) { | |
1245 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1246 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); | |
1247 emit_byte(0x2F); | |
1248 emit_byte(0xC0 | encode); | |
1162 } | 1249 } |
1163 | 1250 |
1164 void Assembler::comiss(XMMRegister dst, Address src) { | 1251 void Assembler::comiss(XMMRegister dst, Address src) { |
1165 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1252 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1166 | 1253 InstructionMark im(this); |
1167 InstructionMark im(this); | 1254 simd_prefix(dst, src, VEX_SIMD_NONE); |
1168 prefix(src, dst); | |
1169 emit_byte(0x0F); | |
1170 emit_byte(0x2F); | 1255 emit_byte(0x2F); |
1171 emit_operand(dst, src); | 1256 emit_operand(dst, src); |
1172 } | 1257 } |
1173 | 1258 |
1259 void Assembler::comiss(XMMRegister dst, XMMRegister src) { | |
1260 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1261 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); | |
1262 emit_byte(0x2F); | |
1263 emit_byte(0xC0 | encode); | |
1264 } | |
1265 | |
1174 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { | 1266 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { |
1175 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1267 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1176 emit_byte(0xF3); | 1268 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
1177 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1178 emit_byte(0x0F); | |
1179 emit_byte(0xE6); | 1269 emit_byte(0xE6); |
1180 emit_byte(0xC0 | encode); | 1270 emit_byte(0xC0 | encode); |
1181 } | 1271 } |
1182 | 1272 |
1183 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | 1273 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { |
1184 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1274 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1185 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 1275 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
1186 emit_byte(0x0F); | |
1187 emit_byte(0x5B); | 1276 emit_byte(0x5B); |
1188 emit_byte(0xC0 | encode); | 1277 emit_byte(0xC0 | encode); |
1189 } | 1278 } |
1190 | 1279 |
1191 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | 1280 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { |
1192 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1281 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1193 emit_byte(0xF2); | 1282 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1194 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1195 emit_byte(0x0F); | |
1196 emit_byte(0x5A); | 1283 emit_byte(0x5A); |
1197 emit_byte(0xC0 | encode); | 1284 emit_byte(0xC0 | encode); |
1198 } | 1285 } |
1199 | 1286 |
1287 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { | |
1288 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1289 InstructionMark im(this); | |
1290 simd_prefix(dst, dst, src, VEX_SIMD_F2); | |
1291 emit_byte(0x5A); | |
1292 emit_operand(dst, src); | |
1293 } | |
1294 | |
1200 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { | 1295 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { |
1201 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1296 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1202 emit_byte(0xF2); | 1297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1203 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1204 emit_byte(0x0F); | |
1205 emit_byte(0x2A); | 1298 emit_byte(0x2A); |
1206 emit_byte(0xC0 | encode); | 1299 emit_byte(0xC0 | encode); |
1207 } | 1300 } |
1208 | 1301 |
1302 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { | |
1303 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1304 InstructionMark im(this); | |
1305 simd_prefix(dst, dst, src, VEX_SIMD_F2); | |
1306 emit_byte(0x2A); | |
1307 emit_operand(dst, src); | |
1308 } | |
1309 | |
1209 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { | 1310 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { |
1210 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1311 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1211 emit_byte(0xF3); | 1312 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1212 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1213 emit_byte(0x0F); | |
1214 emit_byte(0x2A); | 1313 emit_byte(0x2A); |
1215 emit_byte(0xC0 | encode); | 1314 emit_byte(0xC0 | encode); |
1216 } | 1315 } |
1217 | 1316 |
1317 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { | |
1318 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1319 InstructionMark im(this); | |
1320 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
1321 emit_byte(0x2A); | |
1322 emit_operand(dst, src); | |
1323 } | |
1324 | |
1218 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { | 1325 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { |
1219 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1326 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1220 emit_byte(0xF3); | 1327 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1221 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1222 emit_byte(0x0F); | |
1223 emit_byte(0x5A); | 1328 emit_byte(0x5A); |
1224 emit_byte(0xC0 | encode); | 1329 emit_byte(0xC0 | encode); |
1225 } | 1330 } |
1226 | 1331 |
1332 void Assembler::cvtss2sd(XMMRegister dst, Address src) { | |
1333 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1334 InstructionMark im(this); | |
1335 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
1336 emit_byte(0x5A); | |
1337 emit_operand(dst, src); | |
1338 } | |
1339 | |
1340 | |
1227 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { | 1341 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { |
1228 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1342 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1229 emit_byte(0xF2); | 1343 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
1230 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1231 emit_byte(0x0F); | |
1232 emit_byte(0x2C); | 1344 emit_byte(0x2C); |
1233 emit_byte(0xC0 | encode); | 1345 emit_byte(0xC0 | encode); |
1234 } | 1346 } |
1235 | 1347 |
1236 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | 1348 void Assembler::cvttss2sil(Register dst, XMMRegister src) { |
1237 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1349 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1238 emit_byte(0xF3); | 1350 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
1239 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1240 emit_byte(0x0F); | |
1241 emit_byte(0x2C); | 1351 emit_byte(0x2C); |
1242 emit_byte(0xC0 | encode); | 1352 emit_byte(0xC0 | encode); |
1243 } | 1353 } |
1244 | 1354 |
1245 void Assembler::decl(Address dst) { | 1355 void Assembler::decl(Address dst) { |
1251 } | 1361 } |
1252 | 1362 |
1253 void Assembler::divsd(XMMRegister dst, Address src) { | 1363 void Assembler::divsd(XMMRegister dst, Address src) { |
1254 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1364 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1255 InstructionMark im(this); | 1365 InstructionMark im(this); |
1256 emit_byte(0xF2); | 1366 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
1257 prefix(src, dst); | |
1258 emit_byte(0x0F); | |
1259 emit_byte(0x5E); | 1367 emit_byte(0x5E); |
1260 emit_operand(dst, src); | 1368 emit_operand(dst, src); |
1261 } | 1369 } |
1262 | 1370 |
1263 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | 1371 void Assembler::divsd(XMMRegister dst, XMMRegister src) { |
1264 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1372 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1265 emit_byte(0xF2); | 1373 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1266 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1267 emit_byte(0x0F); | |
1268 emit_byte(0x5E); | 1374 emit_byte(0x5E); |
1269 emit_byte(0xC0 | encode); | 1375 emit_byte(0xC0 | encode); |
1270 } | 1376 } |
1271 | 1377 |
1272 void Assembler::divss(XMMRegister dst, Address src) { | 1378 void Assembler::divss(XMMRegister dst, Address src) { |
1273 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1379 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1274 InstructionMark im(this); | 1380 InstructionMark im(this); |
1275 emit_byte(0xF3); | 1381 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
1276 prefix(src, dst); | |
1277 emit_byte(0x0F); | |
1278 emit_byte(0x5E); | 1382 emit_byte(0x5E); |
1279 emit_operand(dst, src); | 1383 emit_operand(dst, src); |
1280 } | 1384 } |
1281 | 1385 |
1282 void Assembler::divss(XMMRegister dst, XMMRegister src) { | 1386 void Assembler::divss(XMMRegister dst, XMMRegister src) { |
1283 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1387 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1284 emit_byte(0xF3); | 1388 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1285 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1286 emit_byte(0x0F); | |
1287 emit_byte(0x5E); | 1389 emit_byte(0x5E); |
1288 emit_byte(0xC0 | encode); | 1390 emit_byte(0xC0 | encode); |
1289 } | 1391 } |
1290 | 1392 |
1291 void Assembler::emms() { | 1393 void Assembler::emms() { |
1375 | 1477 |
1376 void Assembler::jccb(Condition cc, Label& L) { | 1478 void Assembler::jccb(Condition cc, Label& L) { |
1377 if (L.is_bound()) { | 1479 if (L.is_bound()) { |
1378 const int short_size = 2; | 1480 const int short_size = 2; |
1379 address entry = target(L); | 1481 address entry = target(L); |
1380 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)), | 1482 #ifdef ASSERT |
1381 "Dispacement too large for a short jmp"); | 1483 intptr_t dist = (intptr_t)entry - ((intptr_t)_code_pos + short_size); |
1484 intptr_t delta = short_branch_delta(); | |
1485 if (delta != 0) { | |
1486 dist += (dist < 0 ? (-delta) :delta); | |
1487 } | |
1488 assert(is8bit(dist), "Dispacement too large for a short jmp"); | |
1489 #endif | |
1382 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; | 1490 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; |
1383 // 0111 tttn #8-bit disp | 1491 // 0111 tttn #8-bit disp |
1384 emit_byte(0x70 | cc); | 1492 emit_byte(0x70 | cc); |
1385 emit_byte((offs - short_size) & 0xFF); | 1493 emit_byte((offs - short_size) & 0xFF); |
1386 } else { | 1494 } else { |
1442 | 1550 |
1443 void Assembler::jmpb(Label& L) { | 1551 void Assembler::jmpb(Label& L) { |
1444 if (L.is_bound()) { | 1552 if (L.is_bound()) { |
1445 const int short_size = 2; | 1553 const int short_size = 2; |
1446 address entry = target(L); | 1554 address entry = target(L); |
1447 assert(is8bit((entry - _code_pos) + short_size), | |
1448 "Dispacement too large for a short jmp"); | |
1449 assert(entry != NULL, "jmp most probably wrong"); | 1555 assert(entry != NULL, "jmp most probably wrong"); |
1556 #ifdef ASSERT | |
1557 intptr_t dist = (intptr_t)entry - ((intptr_t)_code_pos + short_size); | |
1558 intptr_t delta = short_branch_delta(); | |
1559 if (delta != 0) { | |
1560 dist += (dist < 0 ? (-delta) :delta); | |
1561 } | |
1562 assert(is8bit(dist), "Dispacement too large for a short jmp"); | |
1563 #endif | |
1450 intptr_t offs = entry - _code_pos; | 1564 intptr_t offs = entry - _code_pos; |
1451 emit_byte(0xEB); | 1565 emit_byte(0xEB); |
1452 emit_byte((offs - short_size) & 0xFF); | 1566 emit_byte((offs - short_size) & 0xFF); |
1453 } else { | 1567 } else { |
1454 InstructionMark im(this); | 1568 InstructionMark im(this); |
1507 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | 1621 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); |
1508 } | 1622 } |
1509 | 1623 |
1510 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | 1624 void Assembler::movapd(XMMRegister dst, XMMRegister src) { |
1511 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1625 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1512 int dstenc = dst->encoding(); | 1626 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
1513 int srcenc = src->encoding(); | |
1514 emit_byte(0x66); | |
1515 if (dstenc < 8) { | |
1516 if (srcenc >= 8) { | |
1517 prefix(REX_B); | |
1518 srcenc -= 8; | |
1519 } | |
1520 } else { | |
1521 if (srcenc < 8) { | |
1522 prefix(REX_R); | |
1523 } else { | |
1524 prefix(REX_RB); | |
1525 srcenc -= 8; | |
1526 } | |
1527 dstenc -= 8; | |
1528 } | |
1529 emit_byte(0x0F); | |
1530 emit_byte(0x28); | 1627 emit_byte(0x28); |
1531 emit_byte(0xC0 | dstenc << 3 | srcenc); | 1628 emit_byte(0xC0 | encode); |
1532 } | 1629 } |
1533 | 1630 |
1534 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | 1631 void Assembler::movaps(XMMRegister dst, XMMRegister src) { |
1535 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1632 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1536 int dstenc = dst->encoding(); | 1633 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
1537 int srcenc = src->encoding(); | |
1538 if (dstenc < 8) { | |
1539 if (srcenc >= 8) { | |
1540 prefix(REX_B); | |
1541 srcenc -= 8; | |
1542 } | |
1543 } else { | |
1544 if (srcenc < 8) { | |
1545 prefix(REX_R); | |
1546 } else { | |
1547 prefix(REX_RB); | |
1548 srcenc -= 8; | |
1549 } | |
1550 dstenc -= 8; | |
1551 } | |
1552 emit_byte(0x0F); | |
1553 emit_byte(0x28); | 1634 emit_byte(0x28); |
1554 emit_byte(0xC0 | dstenc << 3 | srcenc); | 1635 emit_byte(0xC0 | encode); |
1555 } | 1636 } |
1556 | 1637 |
1557 void Assembler::movb(Register dst, Address src) { | 1638 void Assembler::movb(Register dst, Address src) { |
1558 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | 1639 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); |
1559 InstructionMark im(this); | 1640 InstructionMark im(this); |
1580 emit_operand(src, dst); | 1661 emit_operand(src, dst); |
1581 } | 1662 } |
1582 | 1663 |
1583 void Assembler::movdl(XMMRegister dst, Register src) { | 1664 void Assembler::movdl(XMMRegister dst, Register src) { |
1584 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1665 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1585 emit_byte(0x66); | 1666 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
1586 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1587 emit_byte(0x0F); | |
1588 emit_byte(0x6E); | 1667 emit_byte(0x6E); |
1589 emit_byte(0xC0 | encode); | 1668 emit_byte(0xC0 | encode); |
1590 } | 1669 } |
1591 | 1670 |
1592 void Assembler::movdl(Register dst, XMMRegister src) { | 1671 void Assembler::movdl(Register dst, XMMRegister src) { |
1593 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1672 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1594 emit_byte(0x66); | |
1595 // swap src/dst to get correct prefix | 1673 // swap src/dst to get correct prefix |
1596 int encode = prefix_and_encode(src->encoding(), dst->encoding()); | 1674 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66); |
1597 emit_byte(0x0F); | |
1598 emit_byte(0x7E); | 1675 emit_byte(0x7E); |
1599 emit_byte(0xC0 | encode); | 1676 emit_byte(0xC0 | encode); |
1600 } | 1677 } |
1601 | 1678 |
1602 void Assembler::movdl(XMMRegister dst, Address src) { | 1679 void Assembler::movdl(XMMRegister dst, Address src) { |
1603 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1680 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1604 InstructionMark im(this); | 1681 InstructionMark im(this); |
1605 emit_byte(0x66); | 1682 simd_prefix(dst, src, VEX_SIMD_66); |
1606 prefix(src, dst); | |
1607 emit_byte(0x0F); | |
1608 emit_byte(0x6E); | 1683 emit_byte(0x6E); |
1609 emit_operand(dst, src); | 1684 emit_operand(dst, src); |
1610 } | 1685 } |
1611 | 1686 |
1612 | 1687 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { |
1613 void Assembler::movdqa(XMMRegister dst, Address src) { | |
1614 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1688 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1615 InstructionMark im(this); | 1689 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
1616 emit_byte(0x66); | 1690 emit_byte(0x6F); |
1617 prefix(src, dst); | 1691 emit_byte(0xC0 | encode); |
1618 emit_byte(0x0F); | 1692 } |
1693 | |
1694 void Assembler::movdqu(XMMRegister dst, Address src) { | |
1695 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1696 InstructionMark im(this); | |
1697 simd_prefix(dst, src, VEX_SIMD_F3); | |
1619 emit_byte(0x6F); | 1698 emit_byte(0x6F); |
1620 emit_operand(dst, src); | 1699 emit_operand(dst, src); |
1621 } | 1700 } |
1622 | 1701 |
1623 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { | 1702 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { |
1624 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1703 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1625 emit_byte(0x66); | 1704 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
1626 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
1627 emit_byte(0x0F); | |
1628 emit_byte(0x6F); | 1705 emit_byte(0x6F); |
1629 emit_byte(0xC0 | encode); | 1706 emit_byte(0xC0 | encode); |
1630 } | 1707 } |
1631 | 1708 |
1632 void Assembler::movdqa(Address dst, XMMRegister src) { | |
1633 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1634 InstructionMark im(this); | |
1635 emit_byte(0x66); | |
1636 prefix(dst, src); | |
1637 emit_byte(0x0F); | |
1638 emit_byte(0x7F); | |
1639 emit_operand(src, dst); | |
1640 } | |
1641 | |
1642 void Assembler::movdqu(XMMRegister dst, Address src) { | |
1643 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1644 InstructionMark im(this); | |
1645 emit_byte(0xF3); | |
1646 prefix(src, dst); | |
1647 emit_byte(0x0F); | |
1648 emit_byte(0x6F); | |
1649 emit_operand(dst, src); | |
1650 } | |
1651 | |
1652 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
1653 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1654 emit_byte(0xF3); | |
1655 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
1656 emit_byte(0x0F); | |
1657 emit_byte(0x6F); | |
1658 emit_byte(0xC0 | encode); | |
1659 } | |
1660 | |
1661 void Assembler::movdqu(Address dst, XMMRegister src) { | 1709 void Assembler::movdqu(Address dst, XMMRegister src) { |
1662 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1710 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1663 InstructionMark im(this); | 1711 InstructionMark im(this); |
1664 emit_byte(0xF3); | 1712 simd_prefix(dst, src, VEX_SIMD_F3); |
1665 prefix(dst, src); | |
1666 emit_byte(0x0F); | |
1667 emit_byte(0x7F); | 1713 emit_byte(0x7F); |
1668 emit_operand(src, dst); | 1714 emit_operand(src, dst); |
1669 } | 1715 } |
1670 | 1716 |
1671 // Uses zero extension on 64bit | 1717 // Uses zero extension on 64bit |
1708 // when loading from memory. But for old Opteron use movlpd instead of movsd. | 1754 // when loading from memory. But for old Opteron use movlpd instead of movsd. |
1709 // The selection is done in MacroAssembler::movdbl() and movflt(). | 1755 // The selection is done in MacroAssembler::movdbl() and movflt(). |
1710 void Assembler::movlpd(XMMRegister dst, Address src) { | 1756 void Assembler::movlpd(XMMRegister dst, Address src) { |
1711 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1757 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1712 InstructionMark im(this); | 1758 InstructionMark im(this); |
1713 emit_byte(0x66); | 1759 simd_prefix(dst, dst, src, VEX_SIMD_66); |
1714 prefix(src, dst); | |
1715 emit_byte(0x0F); | |
1716 emit_byte(0x12); | 1760 emit_byte(0x12); |
1717 emit_operand(dst, src); | 1761 emit_operand(dst, src); |
1718 } | 1762 } |
1719 | 1763 |
1720 void Assembler::movq( MMXRegister dst, Address src ) { | 1764 void Assembler::movq( MMXRegister dst, Address src ) { |
1738 } | 1782 } |
1739 | 1783 |
1740 void Assembler::movq(XMMRegister dst, Address src) { | 1784 void Assembler::movq(XMMRegister dst, Address src) { |
1741 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1785 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1742 InstructionMark im(this); | 1786 InstructionMark im(this); |
1743 emit_byte(0xF3); | 1787 simd_prefix(dst, src, VEX_SIMD_F3); |
1744 prefix(src, dst); | |
1745 emit_byte(0x0F); | |
1746 emit_byte(0x7E); | 1788 emit_byte(0x7E); |
1747 emit_operand(dst, src); | 1789 emit_operand(dst, src); |
1748 } | 1790 } |
1749 | 1791 |
1750 void Assembler::movq(Address dst, XMMRegister src) { | 1792 void Assembler::movq(Address dst, XMMRegister src) { |
1751 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1793 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1752 InstructionMark im(this); | 1794 InstructionMark im(this); |
1753 emit_byte(0x66); | 1795 simd_prefix(dst, src, VEX_SIMD_66); |
1754 prefix(dst, src); | |
1755 emit_byte(0x0F); | |
1756 emit_byte(0xD6); | 1796 emit_byte(0xD6); |
1757 emit_operand(src, dst); | 1797 emit_operand(src, dst); |
1758 } | 1798 } |
1759 | 1799 |
1760 void Assembler::movsbl(Register dst, Address src) { // movsxb | 1800 void Assembler::movsbl(Register dst, Address src) { // movsxb |
1773 emit_byte(0xC0 | encode); | 1813 emit_byte(0xC0 | encode); |
1774 } | 1814 } |
1775 | 1815 |
1776 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | 1816 void Assembler::movsd(XMMRegister dst, XMMRegister src) { |
1777 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1817 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1778 emit_byte(0xF2); | 1818 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1779 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1780 emit_byte(0x0F); | |
1781 emit_byte(0x10); | 1819 emit_byte(0x10); |
1782 emit_byte(0xC0 | encode); | 1820 emit_byte(0xC0 | encode); |
1783 } | 1821 } |
1784 | 1822 |
1785 void Assembler::movsd(XMMRegister dst, Address src) { | 1823 void Assembler::movsd(XMMRegister dst, Address src) { |
1786 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1824 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1787 InstructionMark im(this); | 1825 InstructionMark im(this); |
1788 emit_byte(0xF2); | 1826 simd_prefix(dst, src, VEX_SIMD_F2); |
1789 prefix(src, dst); | |
1790 emit_byte(0x0F); | |
1791 emit_byte(0x10); | 1827 emit_byte(0x10); |
1792 emit_operand(dst, src); | 1828 emit_operand(dst, src); |
1793 } | 1829 } |
1794 | 1830 |
1795 void Assembler::movsd(Address dst, XMMRegister src) { | 1831 void Assembler::movsd(Address dst, XMMRegister src) { |
1796 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1832 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1797 InstructionMark im(this); | 1833 InstructionMark im(this); |
1798 emit_byte(0xF2); | 1834 simd_prefix(dst, src, VEX_SIMD_F2); |
1799 prefix(dst, src); | |
1800 emit_byte(0x0F); | |
1801 emit_byte(0x11); | 1835 emit_byte(0x11); |
1802 emit_operand(src, dst); | 1836 emit_operand(src, dst); |
1803 } | 1837 } |
1804 | 1838 |
1805 void Assembler::movss(XMMRegister dst, XMMRegister src) { | 1839 void Assembler::movss(XMMRegister dst, XMMRegister src) { |
1806 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1840 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1807 emit_byte(0xF3); | 1841 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1808 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1809 emit_byte(0x0F); | |
1810 emit_byte(0x10); | 1842 emit_byte(0x10); |
1811 emit_byte(0xC0 | encode); | 1843 emit_byte(0xC0 | encode); |
1812 } | 1844 } |
1813 | 1845 |
1814 void Assembler::movss(XMMRegister dst, Address src) { | 1846 void Assembler::movss(XMMRegister dst, Address src) { |
1815 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1847 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1816 InstructionMark im(this); | 1848 InstructionMark im(this); |
1817 emit_byte(0xF3); | 1849 simd_prefix(dst, src, VEX_SIMD_F3); |
1818 prefix(src, dst); | |
1819 emit_byte(0x0F); | |
1820 emit_byte(0x10); | 1850 emit_byte(0x10); |
1821 emit_operand(dst, src); | 1851 emit_operand(dst, src); |
1822 } | 1852 } |
1823 | 1853 |
1824 void Assembler::movss(Address dst, XMMRegister src) { | 1854 void Assembler::movss(Address dst, XMMRegister src) { |
1825 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1855 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1826 InstructionMark im(this); | 1856 InstructionMark im(this); |
1827 emit_byte(0xF3); | 1857 simd_prefix(dst, src, VEX_SIMD_F3); |
1828 prefix(dst, src); | |
1829 emit_byte(0x0F); | |
1830 emit_byte(0x11); | 1858 emit_byte(0x11); |
1831 emit_operand(src, dst); | 1859 emit_operand(src, dst); |
1832 } | 1860 } |
1833 | 1861 |
1834 void Assembler::movswl(Register dst, Address src) { // movsxw | 1862 void Assembler::movswl(Register dst, Address src) { // movsxw |
1917 } | 1945 } |
1918 | 1946 |
1919 void Assembler::mulsd(XMMRegister dst, Address src) { | 1947 void Assembler::mulsd(XMMRegister dst, Address src) { |
1920 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1948 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1921 InstructionMark im(this); | 1949 InstructionMark im(this); |
1922 emit_byte(0xF2); | 1950 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
1923 prefix(src, dst); | |
1924 emit_byte(0x0F); | |
1925 emit_byte(0x59); | 1951 emit_byte(0x59); |
1926 emit_operand(dst, src); | 1952 emit_operand(dst, src); |
1927 } | 1953 } |
1928 | 1954 |
1929 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | 1955 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { |
1930 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1956 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1931 emit_byte(0xF2); | 1957 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1932 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1933 emit_byte(0x0F); | |
1934 emit_byte(0x59); | 1958 emit_byte(0x59); |
1935 emit_byte(0xC0 | encode); | 1959 emit_byte(0xC0 | encode); |
1936 } | 1960 } |
1937 | 1961 |
1938 void Assembler::mulss(XMMRegister dst, Address src) { | 1962 void Assembler::mulss(XMMRegister dst, Address src) { |
1939 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1963 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1940 InstructionMark im(this); | 1964 InstructionMark im(this); |
1941 emit_byte(0xF3); | 1965 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
1942 prefix(src, dst); | |
1943 emit_byte(0x0F); | |
1944 emit_byte(0x59); | 1966 emit_byte(0x59); |
1945 emit_operand(dst, src); | 1967 emit_operand(dst, src); |
1946 } | 1968 } |
1947 | 1969 |
1948 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | 1970 void Assembler::mulss(XMMRegister dst, XMMRegister src) { |
1949 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1971 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1950 emit_byte(0xF3); | 1972 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1951 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1952 emit_byte(0x0F); | |
1953 emit_byte(0x59); | 1973 emit_byte(0x59); |
1954 emit_byte(0xC0 | encode); | 1974 emit_byte(0xC0 | encode); |
1955 } | 1975 } |
1956 | 1976 |
1957 void Assembler::negl(Register dst) { | 1977 void Assembler::negl(Register dst) { |
2235 void Assembler::orl(Register dst, Register src) { | 2255 void Assembler::orl(Register dst, Register src) { |
2236 (void) prefix_and_encode(dst->encoding(), src->encoding()); | 2256 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
2237 emit_arith(0x0B, 0xC0, dst, src); | 2257 emit_arith(0x0B, 0xC0, dst, src); |
2238 } | 2258 } |
2239 | 2259 |
2260 void Assembler::packuswb(XMMRegister dst, Address src) { | |
2261 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2262 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
2263 InstructionMark im(this); | |
2264 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
2265 emit_byte(0x67); | |
2266 emit_operand(dst, src); | |
2267 } | |
2268 | |
2269 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { | |
2270 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2271 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | |
2272 emit_byte(0x67); | |
2273 emit_byte(0xC0 | encode); | |
2274 } | |
2275 | |
2240 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { | 2276 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
2241 assert(VM_Version::supports_sse4_2(), ""); | 2277 assert(VM_Version::supports_sse4_2(), ""); |
2242 | 2278 InstructionMark im(this); |
2243 InstructionMark im(this); | 2279 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
2244 emit_byte(0x66); | |
2245 prefix(src, dst); | |
2246 emit_byte(0x0F); | |
2247 emit_byte(0x3A); | |
2248 emit_byte(0x61); | 2280 emit_byte(0x61); |
2249 emit_operand(dst, src); | 2281 emit_operand(dst, src); |
2250 emit_byte(imm8); | 2282 emit_byte(imm8); |
2251 } | 2283 } |
2252 | 2284 |
2253 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | 2285 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { |
2254 assert(VM_Version::supports_sse4_2(), ""); | 2286 assert(VM_Version::supports_sse4_2(), ""); |
2255 | 2287 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
2256 emit_byte(0x66); | |
2257 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
2258 emit_byte(0x0F); | |
2259 emit_byte(0x3A); | |
2260 emit_byte(0x61); | 2288 emit_byte(0x61); |
2261 emit_byte(0xC0 | encode); | 2289 emit_byte(0xC0 | encode); |
2262 emit_byte(imm8); | 2290 emit_byte(imm8); |
2291 } | |
2292 | |
2293 void Assembler::pmovzxbw(XMMRegister dst, Address src) { | |
2294 assert(VM_Version::supports_sse4_1(), ""); | |
2295 InstructionMark im(this); | |
2296 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
2297 emit_byte(0x30); | |
2298 emit_operand(dst, src); | |
2299 } | |
2300 | |
2301 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { | |
2302 assert(VM_Version::supports_sse4_1(), ""); | |
2303 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
2304 emit_byte(0x30); | |
2305 emit_byte(0xC0 | encode); | |
2263 } | 2306 } |
2264 | 2307 |
2265 // generic | 2308 // generic |
2266 void Assembler::pop(Register dst) { | 2309 void Assembler::pop(Register dst) { |
2267 int encode = prefix_and_encode(dst->encoding()); | 2310 int encode = prefix_and_encode(dst->encoding()); |
2358 a_byte(p); | 2401 a_byte(p); |
2359 } | 2402 } |
2360 | 2403 |
2361 void Assembler::por(XMMRegister dst, XMMRegister src) { | 2404 void Assembler::por(XMMRegister dst, XMMRegister src) { |
2362 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2405 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2363 | 2406 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
2364 emit_byte(0x66); | |
2365 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2366 emit_byte(0x0F); | |
2367 | |
2368 emit_byte(0xEB); | 2407 emit_byte(0xEB); |
2369 emit_byte(0xC0 | encode); | 2408 emit_byte(0xC0 | encode); |
2409 } | |
2410 | |
2411 void Assembler::por(XMMRegister dst, Address src) { | |
2412 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2413 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
2414 InstructionMark im(this); | |
2415 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
2416 emit_byte(0xEB); | |
2417 emit_operand(dst, src); | |
2370 } | 2418 } |
2371 | 2419 |
2372 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { | 2420 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
2373 assert(isByte(mode), "invalid value"); | 2421 assert(isByte(mode), "invalid value"); |
2374 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2422 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2375 | 2423 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
2376 emit_byte(0x66); | |
2377 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2378 emit_byte(0x0F); | |
2379 emit_byte(0x70); | 2424 emit_byte(0x70); |
2380 emit_byte(0xC0 | encode); | 2425 emit_byte(0xC0 | encode); |
2381 emit_byte(mode & 0xFF); | 2426 emit_byte(mode & 0xFF); |
2382 | 2427 |
2383 } | 2428 } |
2384 | 2429 |
2385 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | 2430 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { |
2386 assert(isByte(mode), "invalid value"); | 2431 assert(isByte(mode), "invalid value"); |
2387 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2432 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2388 | 2433 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2389 InstructionMark im(this); | 2434 InstructionMark im(this); |
2390 emit_byte(0x66); | 2435 simd_prefix(dst, src, VEX_SIMD_66); |
2391 prefix(src, dst); | |
2392 emit_byte(0x0F); | |
2393 emit_byte(0x70); | 2436 emit_byte(0x70); |
2394 emit_operand(dst, src); | 2437 emit_operand(dst, src); |
2395 emit_byte(mode & 0xFF); | 2438 emit_byte(mode & 0xFF); |
2396 } | 2439 } |
2397 | 2440 |
2398 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | 2441 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { |
2399 assert(isByte(mode), "invalid value"); | 2442 assert(isByte(mode), "invalid value"); |
2400 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2443 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2401 | 2444 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
2402 emit_byte(0xF2); | |
2403 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2404 emit_byte(0x0F); | |
2405 emit_byte(0x70); | 2445 emit_byte(0x70); |
2406 emit_byte(0xC0 | encode); | 2446 emit_byte(0xC0 | encode); |
2407 emit_byte(mode & 0xFF); | 2447 emit_byte(mode & 0xFF); |
2408 } | 2448 } |
2409 | 2449 |
2410 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | 2450 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { |
2411 assert(isByte(mode), "invalid value"); | 2451 assert(isByte(mode), "invalid value"); |
2412 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2452 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2413 | 2453 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2414 InstructionMark im(this); | 2454 InstructionMark im(this); |
2415 emit_byte(0xF2); | 2455 simd_prefix(dst, src, VEX_SIMD_F2); |
2416 prefix(src, dst); // QQ new | |
2417 emit_byte(0x0F); | |
2418 emit_byte(0x70); | 2456 emit_byte(0x70); |
2419 emit_operand(dst, src); | 2457 emit_operand(dst, src); |
2420 emit_byte(mode & 0xFF); | 2458 emit_byte(mode & 0xFF); |
2421 } | 2459 } |
2422 | 2460 |
2423 void Assembler::psrlq(XMMRegister dst, int shift) { | 2461 void Assembler::psrlq(XMMRegister dst, int shift) { |
2424 // Shift 64 bit value logically right by specified number of bits. | 2462 // Shift 64 bit value logically right by specified number of bits. |
2425 // HMM Table D-1 says sse2 or mmx. | 2463 // HMM Table D-1 says sse2 or mmx. |
2426 // Do not confuse it with psrldq SSE2 instruction which | 2464 // Do not confuse it with psrldq SSE2 instruction which |
2427 // shifts 128 bit value in xmm register by number of bytes. | 2465 // shifts 128 bit value in xmm register by number of bytes. |
2428 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2466 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2429 | 2467 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
2430 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding()); | |
2431 emit_byte(0x66); | |
2432 emit_byte(0x0F); | |
2433 emit_byte(0x73); | 2468 emit_byte(0x73); |
2434 emit_byte(0xC0 | encode); | 2469 emit_byte(0xC0 | encode); |
2435 emit_byte(shift); | 2470 emit_byte(shift); |
2436 } | 2471 } |
2437 | 2472 |
2438 void Assembler::psrldq(XMMRegister dst, int shift) { | 2473 void Assembler::psrldq(XMMRegister dst, int shift) { |
2439 // Shift 128 bit value in xmm register by number of bytes. | 2474 // Shift 128 bit value in xmm register by number of bytes. |
2440 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2475 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2441 | 2476 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66); |
2442 int encode = prefixq_and_encode(xmm3->encoding(), dst->encoding()); | |
2443 emit_byte(0x66); | |
2444 emit_byte(0x0F); | |
2445 emit_byte(0x73); | 2477 emit_byte(0x73); |
2446 emit_byte(0xC0 | encode); | 2478 emit_byte(0xC0 | encode); |
2447 emit_byte(shift); | 2479 emit_byte(shift); |
2448 } | 2480 } |
2449 | 2481 |
2450 void Assembler::ptest(XMMRegister dst, Address src) { | 2482 void Assembler::ptest(XMMRegister dst, Address src) { |
2451 assert(VM_Version::supports_sse4_1(), ""); | 2483 assert(VM_Version::supports_sse4_1(), ""); |
2452 | 2484 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2453 InstructionMark im(this); | 2485 InstructionMark im(this); |
2454 emit_byte(0x66); | 2486 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
2455 prefix(src, dst); | |
2456 emit_byte(0x0F); | |
2457 emit_byte(0x38); | |
2458 emit_byte(0x17); | 2487 emit_byte(0x17); |
2459 emit_operand(dst, src); | 2488 emit_operand(dst, src); |
2460 } | 2489 } |
2461 | 2490 |
2462 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | 2491 void Assembler::ptest(XMMRegister dst, XMMRegister src) { |
2463 assert(VM_Version::supports_sse4_1(), ""); | 2492 assert(VM_Version::supports_sse4_1(), ""); |
2464 | 2493 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
2465 emit_byte(0x66); | |
2466 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
2467 emit_byte(0x0F); | |
2468 emit_byte(0x38); | |
2469 emit_byte(0x17); | 2494 emit_byte(0x17); |
2470 emit_byte(0xC0 | encode); | 2495 emit_byte(0xC0 | encode); |
2471 } | 2496 } |
2472 | 2497 |
2498 void Assembler::punpcklbw(XMMRegister dst, Address src) { | |
2499 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2500 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
2501 InstructionMark im(this); | |
2502 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
2503 emit_byte(0x60); | |
2504 emit_operand(dst, src); | |
2505 } | |
2506 | |
2473 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { | 2507 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
2474 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2508 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2475 emit_byte(0x66); | 2509 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
2476 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2477 emit_byte(0x0F); | |
2478 emit_byte(0x60); | 2510 emit_byte(0x60); |
2511 emit_byte(0xC0 | encode); | |
2512 } | |
2513 | |
2514 void Assembler::punpckldq(XMMRegister dst, Address src) { | |
2515 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2516 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
2517 InstructionMark im(this); | |
2518 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
2519 emit_byte(0x62); | |
2520 emit_operand(dst, src); | |
2521 } | |
2522 | |
2523 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { | |
2524 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2525 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | |
2526 emit_byte(0x62); | |
2479 emit_byte(0xC0 | encode); | 2527 emit_byte(0xC0 | encode); |
2480 } | 2528 } |
2481 | 2529 |
2482 void Assembler::push(int32_t imm32) { | 2530 void Assembler::push(int32_t imm32) { |
2483 // in 64bits we push 64bits onto the stack but only | 2531 // in 64bits we push 64bits onto the stack but only |
2506 } | 2554 } |
2507 #endif | 2555 #endif |
2508 | 2556 |
2509 void Assembler::pxor(XMMRegister dst, Address src) { | 2557 void Assembler::pxor(XMMRegister dst, Address src) { |
2510 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2558 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2511 InstructionMark im(this); | 2559 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2512 emit_byte(0x66); | 2560 InstructionMark im(this); |
2513 prefix(src, dst); | 2561 simd_prefix(dst, dst, src, VEX_SIMD_66); |
2514 emit_byte(0x0F); | |
2515 emit_byte(0xEF); | 2562 emit_byte(0xEF); |
2516 emit_operand(dst, src); | 2563 emit_operand(dst, src); |
2517 } | 2564 } |
2518 | 2565 |
2519 void Assembler::pxor(XMMRegister dst, XMMRegister src) { | 2566 void Assembler::pxor(XMMRegister dst, XMMRegister src) { |
2520 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2567 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2521 InstructionMark im(this); | 2568 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
2522 emit_byte(0x66); | |
2523 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2524 emit_byte(0x0F); | |
2525 emit_byte(0xEF); | 2569 emit_byte(0xEF); |
2526 emit_byte(0xC0 | encode); | 2570 emit_byte(0xC0 | encode); |
2527 } | 2571 } |
2528 | 2572 |
2529 void Assembler::rcll(Register dst, int imm8) { | 2573 void Assembler::rcll(Register dst, int imm8) { |
2681 void Assembler::smovl() { | 2725 void Assembler::smovl() { |
2682 emit_byte(0xA5); | 2726 emit_byte(0xA5); |
2683 } | 2727 } |
2684 | 2728 |
2685 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { | 2729 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
2686 // HMM Table D-1 says sse2 | |
2687 // NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2688 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2730 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2689 emit_byte(0xF2); | 2731 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
2690 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2691 emit_byte(0x0F); | |
2692 emit_byte(0x51); | 2732 emit_byte(0x51); |
2693 emit_byte(0xC0 | encode); | 2733 emit_byte(0xC0 | encode); |
2694 } | 2734 } |
2695 | 2735 |
2696 void Assembler::sqrtsd(XMMRegister dst, Address src) { | 2736 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
2697 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2737 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2698 InstructionMark im(this); | 2738 InstructionMark im(this); |
2699 emit_byte(0xF2); | 2739 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
2700 prefix(src, dst); | |
2701 emit_byte(0x0F); | |
2702 emit_byte(0x51); | 2740 emit_byte(0x51); |
2703 emit_operand(dst, src); | 2741 emit_operand(dst, src); |
2704 } | 2742 } |
2705 | 2743 |
2706 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | 2744 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { |
2707 // HMM Table D-1 says sse2 | 2745 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2708 // NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2746 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
2709 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2710 emit_byte(0xF3); | |
2711 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2712 emit_byte(0x0F); | |
2713 emit_byte(0x51); | 2747 emit_byte(0x51); |
2714 emit_byte(0xC0 | encode); | 2748 emit_byte(0xC0 | encode); |
2715 } | 2749 } |
2716 | 2750 |
2717 void Assembler::sqrtss(XMMRegister dst, Address src) { | 2751 void Assembler::sqrtss(XMMRegister dst, Address src) { |
2718 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2752 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2719 InstructionMark im(this); | 2753 InstructionMark im(this); |
2720 emit_byte(0xF3); | 2754 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
2721 prefix(src, dst); | |
2722 emit_byte(0x0F); | |
2723 emit_byte(0x51); | 2755 emit_byte(0x51); |
2724 emit_operand(dst, src); | 2756 emit_operand(dst, src); |
2725 } | 2757 } |
2726 | 2758 |
2727 void Assembler::stmxcsr( Address dst) { | 2759 void Assembler::stmxcsr( Address dst) { |
2749 void Assembler::subl(Register dst, int32_t imm32) { | 2781 void Assembler::subl(Register dst, int32_t imm32) { |
2750 prefix(dst); | 2782 prefix(dst); |
2751 emit_arith(0x81, 0xE8, dst, imm32); | 2783 emit_arith(0x81, 0xE8, dst, imm32); |
2752 } | 2784 } |
2753 | 2785 |
2786 // Force generation of a 4 byte immediate value even if it fits into 8bit | |
2787 void Assembler::subl_imm32(Register dst, int32_t imm32) { | |
2788 prefix(dst); | |
2789 emit_arith_imm32(0x81, 0xE8, dst, imm32); | |
2790 } | |
2791 | |
2754 void Assembler::subl(Register dst, Address src) { | 2792 void Assembler::subl(Register dst, Address src) { |
2755 InstructionMark im(this); | 2793 InstructionMark im(this); |
2756 prefix(src, dst); | 2794 prefix(src, dst); |
2757 emit_byte(0x2B); | 2795 emit_byte(0x2B); |
2758 emit_operand(dst, src); | 2796 emit_operand(dst, src); |
2763 emit_arith(0x2B, 0xC0, dst, src); | 2801 emit_arith(0x2B, 0xC0, dst, src); |
2764 } | 2802 } |
2765 | 2803 |
2766 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | 2804 void Assembler::subsd(XMMRegister dst, XMMRegister src) { |
2767 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2805 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2768 emit_byte(0xF2); | 2806 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
2769 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2770 emit_byte(0x0F); | |
2771 emit_byte(0x5C); | 2807 emit_byte(0x5C); |
2772 emit_byte(0xC0 | encode); | 2808 emit_byte(0xC0 | encode); |
2773 } | 2809 } |
2774 | 2810 |
2775 void Assembler::subsd(XMMRegister dst, Address src) { | 2811 void Assembler::subsd(XMMRegister dst, Address src) { |
2776 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2812 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2777 InstructionMark im(this); | 2813 InstructionMark im(this); |
2778 emit_byte(0xF2); | 2814 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
2779 prefix(src, dst); | |
2780 emit_byte(0x0F); | |
2781 emit_byte(0x5C); | 2815 emit_byte(0x5C); |
2782 emit_operand(dst, src); | 2816 emit_operand(dst, src); |
2783 } | 2817 } |
2784 | 2818 |
2785 void Assembler::subss(XMMRegister dst, XMMRegister src) { | 2819 void Assembler::subss(XMMRegister dst, XMMRegister src) { |
2786 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2820 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2787 emit_byte(0xF3); | 2821 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
2788 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2789 emit_byte(0x0F); | |
2790 emit_byte(0x5C); | 2822 emit_byte(0x5C); |
2791 emit_byte(0xC0 | encode); | 2823 emit_byte(0xC0 | encode); |
2792 } | 2824 } |
2793 | 2825 |
2794 void Assembler::subss(XMMRegister dst, Address src) { | 2826 void Assembler::subss(XMMRegister dst, Address src) { |
2795 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2827 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2796 InstructionMark im(this); | 2828 InstructionMark im(this); |
2797 emit_byte(0xF3); | 2829 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
2798 prefix(src, dst); | |
2799 emit_byte(0x0F); | |
2800 emit_byte(0x5C); | 2830 emit_byte(0x5C); |
2801 emit_operand(dst, src); | 2831 emit_operand(dst, src); |
2802 } | 2832 } |
2803 | 2833 |
2804 void Assembler::testb(Register dst, int imm8) { | 2834 void Assembler::testb(Register dst, int imm8) { |
2834 emit_operand(dst, src); | 2864 emit_operand(dst, src); |
2835 } | 2865 } |
2836 | 2866 |
2837 void Assembler::ucomisd(XMMRegister dst, Address src) { | 2867 void Assembler::ucomisd(XMMRegister dst, Address src) { |
2838 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2868 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2839 emit_byte(0x66); | 2869 InstructionMark im(this); |
2840 ucomiss(dst, src); | 2870 simd_prefix(dst, src, VEX_SIMD_66); |
2871 emit_byte(0x2E); | |
2872 emit_operand(dst, src); | |
2841 } | 2873 } |
2842 | 2874 |
2843 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | 2875 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { |
2844 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2876 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2845 emit_byte(0x66); | 2877 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
2846 ucomiss(dst, src); | 2878 emit_byte(0x2E); |
2879 emit_byte(0xC0 | encode); | |
2847 } | 2880 } |
2848 | 2881 |
2849 void Assembler::ucomiss(XMMRegister dst, Address src) { | 2882 void Assembler::ucomiss(XMMRegister dst, Address src) { |
2850 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2883 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2851 | 2884 InstructionMark im(this); |
2852 InstructionMark im(this); | 2885 simd_prefix(dst, src, VEX_SIMD_NONE); |
2853 prefix(src, dst); | |
2854 emit_byte(0x0F); | |
2855 emit_byte(0x2E); | 2886 emit_byte(0x2E); |
2856 emit_operand(dst, src); | 2887 emit_operand(dst, src); |
2857 } | 2888 } |
2858 | 2889 |
2859 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | 2890 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { |
2860 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2891 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2861 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 2892 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
2862 emit_byte(0x0F); | |
2863 emit_byte(0x2E); | 2893 emit_byte(0x2E); |
2864 emit_byte(0xC0 | encode); | 2894 emit_byte(0xC0 | encode); |
2865 } | 2895 } |
2866 | 2896 |
2867 | 2897 |
2903 emit_arith(0x33, 0xC0, dst, src); | 2933 emit_arith(0x33, 0xC0, dst, src); |
2904 } | 2934 } |
2905 | 2935 |
2906 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { | 2936 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { |
2907 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2937 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2908 emit_byte(0x66); | 2938 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
2909 xorps(dst, src); | 2939 emit_byte(0x57); |
2940 emit_byte(0xC0 | encode); | |
2910 } | 2941 } |
2911 | 2942 |
2912 void Assembler::xorpd(XMMRegister dst, Address src) { | 2943 void Assembler::xorpd(XMMRegister dst, Address src) { |
2913 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2944 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2914 InstructionMark im(this); | 2945 InstructionMark im(this); |
2915 emit_byte(0x66); | 2946 simd_prefix(dst, dst, src, VEX_SIMD_66); |
2916 prefix(src, dst); | |
2917 emit_byte(0x0F); | |
2918 emit_byte(0x57); | 2947 emit_byte(0x57); |
2919 emit_operand(dst, src); | 2948 emit_operand(dst, src); |
2920 } | 2949 } |
2921 | 2950 |
2922 | 2951 |
2923 void Assembler::xorps(XMMRegister dst, XMMRegister src) { | 2952 void Assembler::xorps(XMMRegister dst, XMMRegister src) { |
2924 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2953 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2925 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 2954 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE); |
2926 emit_byte(0x0F); | |
2927 emit_byte(0x57); | 2955 emit_byte(0x57); |
2928 emit_byte(0xC0 | encode); | 2956 emit_byte(0xC0 | encode); |
2929 } | 2957 } |
2930 | 2958 |
2931 void Assembler::xorps(XMMRegister dst, Address src) { | 2959 void Assembler::xorps(XMMRegister dst, Address src) { |
2932 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2960 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2933 InstructionMark im(this); | 2961 InstructionMark im(this); |
2934 prefix(src, dst); | 2962 simd_prefix(dst, dst, src, VEX_SIMD_NONE); |
2935 emit_byte(0x0F); | |
2936 emit_byte(0x57); | 2963 emit_byte(0x57); |
2937 emit_operand(dst, src); | 2964 emit_operand(dst, src); |
2938 } | 2965 } |
2966 | |
2967 // AVX 3-operands non destructive source instructions (encoded with VEX prefix) | |
2968 | |
2969 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { | |
2970 assert(VM_Version::supports_avx(), ""); | |
2971 InstructionMark im(this); | |
2972 vex_prefix(dst, nds, src, VEX_SIMD_F2); | |
2973 emit_byte(0x58); | |
2974 emit_operand(dst, src); | |
2975 } | |
2976 | |
2977 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
2978 assert(VM_Version::supports_avx(), ""); | |
2979 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); | |
2980 emit_byte(0x58); | |
2981 emit_byte(0xC0 | encode); | |
2982 } | |
2983 | |
2984 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { | |
2985 assert(VM_Version::supports_avx(), ""); | |
2986 InstructionMark im(this); | |
2987 vex_prefix(dst, nds, src, VEX_SIMD_F3); | |
2988 emit_byte(0x58); | |
2989 emit_operand(dst, src); | |
2990 } | |
2991 | |
2992 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
2993 assert(VM_Version::supports_avx(), ""); | |
2994 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); | |
2995 emit_byte(0x58); | |
2996 emit_byte(0xC0 | encode); | |
2997 } | |
2998 | |
2999 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src) { | |
3000 assert(VM_Version::supports_avx(), ""); | |
3001 InstructionMark im(this); | |
3002 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector | |
3003 emit_byte(0x54); | |
3004 emit_operand(dst, src); | |
3005 } | |
3006 | |
3007 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src) { | |
3008 assert(VM_Version::supports_avx(), ""); | |
3009 InstructionMark im(this); | |
3010 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector | |
3011 emit_byte(0x54); | |
3012 emit_operand(dst, src); | |
3013 } | |
3014 | |
3015 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { | |
3016 assert(VM_Version::supports_avx(), ""); | |
3017 InstructionMark im(this); | |
3018 vex_prefix(dst, nds, src, VEX_SIMD_F2); | |
3019 emit_byte(0x5E); | |
3020 emit_operand(dst, src); | |
3021 } | |
3022 | |
3023 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3024 assert(VM_Version::supports_avx(), ""); | |
3025 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); | |
3026 emit_byte(0x5E); | |
3027 emit_byte(0xC0 | encode); | |
3028 } | |
3029 | |
3030 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { | |
3031 assert(VM_Version::supports_avx(), ""); | |
3032 InstructionMark im(this); | |
3033 vex_prefix(dst, nds, src, VEX_SIMD_F3); | |
3034 emit_byte(0x5E); | |
3035 emit_operand(dst, src); | |
3036 } | |
3037 | |
3038 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3039 assert(VM_Version::supports_avx(), ""); | |
3040 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); | |
3041 emit_byte(0x5E); | |
3042 emit_byte(0xC0 | encode); | |
3043 } | |
3044 | |
3045 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { | |
3046 assert(VM_Version::supports_avx(), ""); | |
3047 InstructionMark im(this); | |
3048 vex_prefix(dst, nds, src, VEX_SIMD_F2); | |
3049 emit_byte(0x59); | |
3050 emit_operand(dst, src); | |
3051 } | |
3052 | |
3053 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3054 assert(VM_Version::supports_avx(), ""); | |
3055 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); | |
3056 emit_byte(0x59); | |
3057 emit_byte(0xC0 | encode); | |
3058 } | |
3059 | |
3060 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { | |
3061 InstructionMark im(this); | |
3062 vex_prefix(dst, nds, src, VEX_SIMD_F3); | |
3063 emit_byte(0x59); | |
3064 emit_operand(dst, src); | |
3065 } | |
3066 | |
3067 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3068 assert(VM_Version::supports_avx(), ""); | |
3069 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); | |
3070 emit_byte(0x59); | |
3071 emit_byte(0xC0 | encode); | |
3072 } | |
3073 | |
3074 | |
3075 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { | |
3076 assert(VM_Version::supports_avx(), ""); | |
3077 InstructionMark im(this); | |
3078 vex_prefix(dst, nds, src, VEX_SIMD_F2); | |
3079 emit_byte(0x5C); | |
3080 emit_operand(dst, src); | |
3081 } | |
3082 | |
3083 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3084 assert(VM_Version::supports_avx(), ""); | |
3085 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); | |
3086 emit_byte(0x5C); | |
3087 emit_byte(0xC0 | encode); | |
3088 } | |
3089 | |
3090 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { | |
3091 assert(VM_Version::supports_avx(), ""); | |
3092 InstructionMark im(this); | |
3093 vex_prefix(dst, nds, src, VEX_SIMD_F3); | |
3094 emit_byte(0x5C); | |
3095 emit_operand(dst, src); | |
3096 } | |
3097 | |
3098 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3099 assert(VM_Version::supports_avx(), ""); | |
3100 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); | |
3101 emit_byte(0x5C); | |
3102 emit_byte(0xC0 | encode); | |
3103 } | |
3104 | |
3105 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src) { | |
3106 assert(VM_Version::supports_avx(), ""); | |
3107 InstructionMark im(this); | |
3108 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector | |
3109 emit_byte(0x57); | |
3110 emit_operand(dst, src); | |
3111 } | |
3112 | |
3113 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src) { | |
3114 assert(VM_Version::supports_avx(), ""); | |
3115 InstructionMark im(this); | |
3116 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector | |
3117 emit_byte(0x57); | |
3118 emit_operand(dst, src); | |
3119 } | |
3120 | |
2939 | 3121 |
2940 #ifndef _LP64 | 3122 #ifndef _LP64 |
2941 // 32bit only pieces of the assembler | 3123 // 32bit only pieces of the assembler |
2942 | 3124 |
2943 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | 3125 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
3392 void Assembler::fyl2x() { | 3574 void Assembler::fyl2x() { |
3393 emit_byte(0xD9); | 3575 emit_byte(0xD9); |
3394 emit_byte(0xF1); | 3576 emit_byte(0xF1); |
3395 } | 3577 } |
3396 | 3578 |
3579 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. | |
3580 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; | |
3581 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. | |
3582 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; | |
3583 | |
3584 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. | |
3585 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
3586 if (pre > 0) { | |
3587 emit_byte(simd_pre[pre]); | |
3588 } | |
3589 if (rex_w) { | |
3590 prefixq(adr, xreg); | |
3591 } else { | |
3592 prefix(adr, xreg); | |
3593 } | |
3594 if (opc > 0) { | |
3595 emit_byte(0x0F); | |
3596 int opc2 = simd_opc[opc]; | |
3597 if (opc2 > 0) { | |
3598 emit_byte(opc2); | |
3599 } | |
3600 } | |
3601 } | |
3602 | |
3603 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
3604 if (pre > 0) { | |
3605 emit_byte(simd_pre[pre]); | |
3606 } | |
3607 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : | |
3608 prefix_and_encode(dst_enc, src_enc); | |
3609 if (opc > 0) { | |
3610 emit_byte(0x0F); | |
3611 int opc2 = simd_opc[opc]; | |
3612 if (opc2 > 0) { | |
3613 emit_byte(opc2); | |
3614 } | |
3615 } | |
3616 return encode; | |
3617 } | |
3618 | |
3619 | |
3620 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) { | |
3621 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { | |
3622 prefix(VEX_3bytes); | |
3623 | |
3624 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); | |
3625 byte1 = (~byte1) & 0xE0; | |
3626 byte1 |= opc; | |
3627 a_byte(byte1); | |
3628 | |
3629 int byte2 = ((~nds_enc) & 0xf) << 3; | |
3630 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre; | |
3631 emit_byte(byte2); | |
3632 } else { | |
3633 prefix(VEX_2bytes); | |
3634 | |
3635 int byte1 = vex_r ? VEX_R : 0; | |
3636 byte1 = (~byte1) & 0x80; | |
3637 byte1 |= ((~nds_enc) & 0xf) << 3; | |
3638 byte1 |= (vector256 ? 4 : 0) | pre; | |
3639 emit_byte(byte1); | |
3640 } | |
3641 } | |
3642 | |
3643 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){ | |
3644 bool vex_r = (xreg_enc >= 8); | |
3645 bool vex_b = adr.base_needs_rex(); | |
3646 bool vex_x = adr.index_needs_rex(); | |
3647 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
3648 } | |
3649 | |
3650 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) { | |
3651 bool vex_r = (dst_enc >= 8); | |
3652 bool vex_b = (src_enc >= 8); | |
3653 bool vex_x = false; | |
3654 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
3655 return (((dst_enc & 7) << 3) | (src_enc & 7)); | |
3656 } | |
3657 | |
3658 | |
3659 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
3660 if (UseAVX > 0) { | |
3661 int xreg_enc = xreg->encoding(); | |
3662 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
3663 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256); | |
3664 } else { | |
3665 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); | |
3666 rex_prefix(adr, xreg, pre, opc, rex_w); | |
3667 } | |
3668 } | |
3669 | |
3670 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
3671 int dst_enc = dst->encoding(); | |
3672 int src_enc = src->encoding(); | |
3673 if (UseAVX > 0) { | |
3674 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
3675 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256); | |
3676 } else { | |
3677 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); | |
3678 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w); | |
3679 } | |
3680 } | |
3397 | 3681 |
3398 #ifndef _LP64 | 3682 #ifndef _LP64 |
3399 | 3683 |
3400 void Assembler::incl(Register dst) { | 3684 void Assembler::incl(Register dst) { |
3401 // Don't use it directly. Use MacroAssembler::incrementl() instead. | 3685 // Don't use it directly. Use MacroAssembler::incrementl() instead. |
3402 emit_byte(0x40 | dst->encoding()); | 3686 emit_byte(0x40 | dst->encoding()); |
3403 } | 3687 } |
3404 | 3688 |
3405 void Assembler::lea(Register dst, Address src) { | 3689 void Assembler::lea(Register dst, Address src) { |
3406 leal(dst, src); | 3690 leal(dst, src); |
3407 } | 3691 } |
3754 } | 4038 } |
3755 } | 4039 } |
3756 } | 4040 } |
3757 } | 4041 } |
3758 | 4042 |
4043 void Assembler::prefixq(Address adr, XMMRegister src) { | |
4044 if (src->encoding() < 8) { | |
4045 if (adr.base_needs_rex()) { | |
4046 if (adr.index_needs_rex()) { | |
4047 prefix(REX_WXB); | |
4048 } else { | |
4049 prefix(REX_WB); | |
4050 } | |
4051 } else { | |
4052 if (adr.index_needs_rex()) { | |
4053 prefix(REX_WX); | |
4054 } else { | |
4055 prefix(REX_W); | |
4056 } | |
4057 } | |
4058 } else { | |
4059 if (adr.base_needs_rex()) { | |
4060 if (adr.index_needs_rex()) { | |
4061 prefix(REX_WRXB); | |
4062 } else { | |
4063 prefix(REX_WRB); | |
4064 } | |
4065 } else { | |
4066 if (adr.index_needs_rex()) { | |
4067 prefix(REX_WRX); | |
4068 } else { | |
4069 prefix(REX_WR); | |
4070 } | |
4071 } | |
4072 } | |
4073 } | |
4074 | |
3759 void Assembler::adcq(Register dst, int32_t imm32) { | 4075 void Assembler::adcq(Register dst, int32_t imm32) { |
3760 (void) prefixq_and_encode(dst->encoding()); | 4076 (void) prefixq_and_encode(dst->encoding()); |
3761 emit_arith(0x81, 0xD0, dst, imm32); | 4077 emit_arith(0x81, 0xD0, dst, imm32); |
3762 } | 4078 } |
3763 | 4079 |
3916 emit_operand(reg, adr); | 4232 emit_operand(reg, adr); |
3917 } | 4233 } |
3918 | 4234 |
3919 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | 4235 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { |
3920 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 4236 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3921 emit_byte(0xF2); | 4237 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2); |
3922 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3923 emit_byte(0x0F); | |
3924 emit_byte(0x2A); | 4238 emit_byte(0x2A); |
3925 emit_byte(0xC0 | encode); | 4239 emit_byte(0xC0 | encode); |
3926 } | 4240 } |
3927 | 4241 |
4242 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { | |
4243 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4244 InstructionMark im(this); | |
4245 simd_prefix_q(dst, dst, src, VEX_SIMD_F2); | |
4246 emit_byte(0x2A); | |
4247 emit_operand(dst, src); | |
4248 } | |
4249 | |
3928 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { | 4250 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { |
3929 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 4251 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
3930 emit_byte(0xF3); | 4252 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3); |
3931 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3932 emit_byte(0x0F); | |
3933 emit_byte(0x2A); | 4253 emit_byte(0x2A); |
3934 emit_byte(0xC0 | encode); | 4254 emit_byte(0xC0 | encode); |
3935 } | 4255 } |
3936 | 4256 |
4257 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { | |
4258 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4259 InstructionMark im(this); | |
4260 simd_prefix_q(dst, dst, src, VEX_SIMD_F3); | |
4261 emit_byte(0x2A); | |
4262 emit_operand(dst, src); | |
4263 } | |
4264 | |
3937 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { | 4265 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { |
3938 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 4266 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3939 emit_byte(0xF2); | 4267 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2); |
3940 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3941 emit_byte(0x0F); | |
3942 emit_byte(0x2C); | 4268 emit_byte(0x2C); |
3943 emit_byte(0xC0 | encode); | 4269 emit_byte(0xC0 | encode); |
3944 } | 4270 } |
3945 | 4271 |
3946 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | 4272 void Assembler::cvttss2siq(Register dst, XMMRegister src) { |
3947 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 4273 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
3948 emit_byte(0xF3); | 4274 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3); |
3949 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3950 emit_byte(0x0F); | |
3951 emit_byte(0x2C); | 4275 emit_byte(0x2C); |
3952 emit_byte(0xC0 | encode); | 4276 emit_byte(0xC0 | encode); |
3953 } | 4277 } |
3954 | 4278 |
3955 void Assembler::decl(Register dst) { | 4279 void Assembler::decl(Register dst) { |
4105 emit_byte(0xC0 | encode); | 4429 emit_byte(0xC0 | encode); |
4106 } | 4430 } |
4107 | 4431 |
4108 void Assembler::movdq(XMMRegister dst, Register src) { | 4432 void Assembler::movdq(XMMRegister dst, Register src) { |
4109 // table D-1 says MMX/SSE2 | 4433 // table D-1 says MMX/SSE2 |
4110 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | 4434 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4111 emit_byte(0x66); | 4435 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66); |
4112 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4113 emit_byte(0x0F); | |
4114 emit_byte(0x6E); | 4436 emit_byte(0x6E); |
4115 emit_byte(0xC0 | encode); | 4437 emit_byte(0xC0 | encode); |
4116 } | 4438 } |
4117 | 4439 |
4118 void Assembler::movdq(Register dst, XMMRegister src) { | 4440 void Assembler::movdq(Register dst, XMMRegister src) { |
4119 // table D-1 says MMX/SSE2 | 4441 // table D-1 says MMX/SSE2 |
4120 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | 4442 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4121 emit_byte(0x66); | |
4122 // swap src/dst to get correct prefix | 4443 // swap src/dst to get correct prefix |
4123 int encode = prefixq_and_encode(src->encoding(), dst->encoding()); | 4444 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66); |
4124 emit_byte(0x0F); | |
4125 emit_byte(0x7E); | 4445 emit_byte(0x7E); |
4126 emit_byte(0xC0 | encode); | 4446 emit_byte(0xC0 | encode); |
4127 } | 4447 } |
4128 | 4448 |
4129 void Assembler::movq(Register dst, Register src) { | 4449 void Assembler::movq(Register dst, Register src) { |
4458 void Assembler::subq(Register dst, int32_t imm32) { | 4778 void Assembler::subq(Register dst, int32_t imm32) { |
4459 (void) prefixq_and_encode(dst->encoding()); | 4779 (void) prefixq_and_encode(dst->encoding()); |
4460 emit_arith(0x81, 0xE8, dst, imm32); | 4780 emit_arith(0x81, 0xE8, dst, imm32); |
4461 } | 4781 } |
4462 | 4782 |
4783 // Force generation of a 4 byte immediate value even if it fits into 8bit | |
4784 void Assembler::subq_imm32(Register dst, int32_t imm32) { | |
4785 (void) prefixq_and_encode(dst->encoding()); | |
4786 emit_arith_imm32(0x81, 0xE8, dst, imm32); | |
4787 } | |
4788 | |
4463 void Assembler::subq(Register dst, Address src) { | 4789 void Assembler::subq(Register dst, Address src) { |
4464 InstructionMark im(this); | 4790 InstructionMark im(this); |
4465 prefixq(src, dst); | 4791 prefixq(src, dst); |
4466 emit_byte(0x2B); | 4792 emit_byte(0x2B); |
4467 emit_operand(dst, src); | 4793 emit_operand(dst, src); |
4630 xorl(swap_reg, tmp_reg); | 4956 xorl(swap_reg, tmp_reg); |
4631 if (swap_reg_contains_mark) { | 4957 if (swap_reg_contains_mark) { |
4632 null_check_offset = offset(); | 4958 null_check_offset = offset(); |
4633 } | 4959 } |
4634 movl(tmp_reg, klass_addr); | 4960 movl(tmp_reg, klass_addr); |
4635 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | 4961 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset())); |
4636 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); | 4962 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); |
4637 if (need_tmp_reg) { | 4963 if (need_tmp_reg) { |
4638 pop(tmp_reg); | 4964 pop(tmp_reg); |
4639 } | 4965 } |
4640 if (counters != NULL) { | 4966 if (counters != NULL) { |
4717 if (need_tmp_reg) { | 5043 if (need_tmp_reg) { |
4718 push(tmp_reg); | 5044 push(tmp_reg); |
4719 } | 5045 } |
4720 get_thread(tmp_reg); | 5046 get_thread(tmp_reg); |
4721 movl(swap_reg, klass_addr); | 5047 movl(swap_reg, klass_addr); |
4722 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | 5048 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset())); |
4723 movl(swap_reg, saved_mark_addr); | 5049 movl(swap_reg, saved_mark_addr); |
4724 if (os::is_MP()) { | 5050 if (os::is_MP()) { |
4725 lock(); | 5051 lock(); |
4726 } | 5052 } |
4727 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | 5053 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); |
4755 movl(swap_reg, saved_mark_addr); | 5081 movl(swap_reg, saved_mark_addr); |
4756 if (need_tmp_reg) { | 5082 if (need_tmp_reg) { |
4757 push(tmp_reg); | 5083 push(tmp_reg); |
4758 } | 5084 } |
4759 movl(tmp_reg, klass_addr); | 5085 movl(tmp_reg, klass_addr); |
4760 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | 5086 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset())); |
4761 if (os::is_MP()) { | 5087 if (os::is_MP()) { |
4762 lock(); | 5088 lock(); |
4763 } | 5089 } |
4764 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | 5090 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); |
4765 if (need_tmp_reg) { | 5091 if (need_tmp_reg) { |
4797 cdql(); | 5123 cdql(); |
4798 } else { | 5124 } else { |
4799 movl(hi, lo); | 5125 movl(hi, lo); |
4800 sarl(hi, 31); | 5126 sarl(hi, 31); |
4801 } | 5127 } |
4802 } | |
4803 | |
4804 void MacroAssembler::fat_nop() { | |
4805 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
4806 emit_byte(0x26); // es: | |
4807 emit_byte(0x2e); // cs: | |
4808 emit_byte(0x64); // fs: | |
4809 emit_byte(0x65); // gs: | |
4810 emit_byte(0x90); | |
4811 } | 5128 } |
4812 | 5129 |
4813 void MacroAssembler::jC2(Register tmp, Label& L) { | 5130 void MacroAssembler::jC2(Register tmp, Label& L) { |
4814 // set parity bit if FPU flag C2 is set (via rax) | 5131 // set parity bit if FPU flag C2 is set (via rax) |
4815 save_rax(tmp); | 5132 save_rax(tmp); |
5400 if (value == min_jint) { subq(dst, value); return; } | 5717 if (value == min_jint) { subq(dst, value); return; } |
5401 if (value < 0) { incrementq(dst, -value); return; } | 5718 if (value < 0) { incrementq(dst, -value); return; } |
5402 if (value == 0) { ; return; } | 5719 if (value == 0) { ; return; } |
5403 if (value == 1 && UseIncDec) { decq(dst) ; return; } | 5720 if (value == 1 && UseIncDec) { decq(dst) ; return; } |
5404 /* else */ { subq(dst, value) ; return; } | 5721 /* else */ { subq(dst, value) ; return; } |
5405 } | |
5406 | |
5407 void MacroAssembler::fat_nop() { | |
5408 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
5409 // Recommened sequence from 'Software Optimization Guide for the AMD | |
5410 // Hammer Processor' | |
5411 emit_byte(0x66); | |
5412 emit_byte(0x66); | |
5413 emit_byte(0x90); | |
5414 emit_byte(0x66); | |
5415 emit_byte(0x90); | |
5416 } | 5722 } |
5417 | 5723 |
5418 void MacroAssembler::incrementq(Register reg, int value) { | 5724 void MacroAssembler::incrementq(Register reg, int value) { |
5419 if (value == min_jint) { addq(reg, value); return; } | 5725 if (value == min_jint) { addq(reg, value); return; } |
5420 if (value < 0) { decrementq(reg, -value); return; } | 5726 if (value < 0) { decrementq(reg, -value); return; } |
5678 | 5984 |
5679 void MacroAssembler::addptr(Address dst, Register src) { | 5985 void MacroAssembler::addptr(Address dst, Register src) { |
5680 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | 5986 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); |
5681 } | 5987 } |
5682 | 5988 |
5989 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { | |
5990 if (reachable(src)) { | |
5991 Assembler::addsd(dst, as_Address(src)); | |
5992 } else { | |
5993 lea(rscratch1, src); | |
5994 Assembler::addsd(dst, Address(rscratch1, 0)); | |
5995 } | |
5996 } | |
5997 | |
5998 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { | |
5999 if (reachable(src)) { | |
6000 addss(dst, as_Address(src)); | |
6001 } else { | |
6002 lea(rscratch1, src); | |
6003 addss(dst, Address(rscratch1, 0)); | |
6004 } | |
6005 } | |
6006 | |
5683 void MacroAssembler::align(int modulus) { | 6007 void MacroAssembler::align(int modulus) { |
5684 if (offset() % modulus != 0) { | 6008 if (offset() % modulus != 0) { |
5685 nop(modulus - (offset() % modulus)); | 6009 nop(modulus - (offset() % modulus)); |
5686 } | 6010 } |
5687 } | 6011 } |
5688 | 6012 |
5689 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { | 6013 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { |
6014 // Used in sign-masking with aligned address. | |
6015 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
5690 if (reachable(src)) { | 6016 if (reachable(src)) { |
5691 andpd(dst, as_Address(src)); | 6017 Assembler::andpd(dst, as_Address(src)); |
5692 } else { | 6018 } else { |
5693 lea(rscratch1, src); | 6019 lea(rscratch1, src); |
5694 andpd(dst, Address(rscratch1, 0)); | 6020 Assembler::andpd(dst, Address(rscratch1, 0)); |
6021 } | |
6022 } | |
6023 | |
6024 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { | |
6025 // Used in sign-masking with aligned address. | |
6026 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
6027 if (reachable(src)) { | |
6028 Assembler::andps(dst, as_Address(src)); | |
6029 } else { | |
6030 lea(rscratch1, src); | |
6031 Assembler::andps(dst, Address(rscratch1, 0)); | |
5695 } | 6032 } |
5696 } | 6033 } |
5697 | 6034 |
5698 void MacroAssembler::andptr(Register dst, int32_t imm32) { | 6035 void MacroAssembler::andptr(Register dst, int32_t imm32) { |
5699 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); | 6036 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); |
5966 } | 6303 } |
5967 // debugging support | 6304 // debugging support |
5968 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | 6305 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); |
5969 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); | 6306 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); |
5970 #ifdef ASSERT | 6307 #ifdef ASSERT |
5971 LP64_ONLY(if (UseCompressedOops) verify_heapbase("call_VM_base");) | 6308 // TraceBytecodes does not use r12 but saves it over the call, so don't verify |
6309 // r12 is the heapbase. | |
6310 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base");) | |
5972 #endif // ASSERT | 6311 #endif // ASSERT |
5973 | 6312 |
5974 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); | 6313 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); |
5975 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); | 6314 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); |
5976 | 6315 |
6266 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); | 6605 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); |
6267 } | 6606 } |
6268 | 6607 |
6269 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { | 6608 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { |
6270 if (reachable(src)) { | 6609 if (reachable(src)) { |
6271 comisd(dst, as_Address(src)); | 6610 Assembler::comisd(dst, as_Address(src)); |
6272 } else { | 6611 } else { |
6273 lea(rscratch1, src); | 6612 lea(rscratch1, src); |
6274 comisd(dst, Address(rscratch1, 0)); | 6613 Assembler::comisd(dst, Address(rscratch1, 0)); |
6275 } | 6614 } |
6276 } | 6615 } |
6277 | 6616 |
6278 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { | 6617 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { |
6279 if (reachable(src)) { | 6618 if (reachable(src)) { |
6280 comiss(dst, as_Address(src)); | 6619 Assembler::comiss(dst, as_Address(src)); |
6281 } else { | 6620 } else { |
6282 lea(rscratch1, src); | 6621 lea(rscratch1, src); |
6283 comiss(dst, Address(rscratch1, 0)); | 6622 Assembler::comiss(dst, Address(rscratch1, 0)); |
6284 } | 6623 } |
6285 } | 6624 } |
6286 | 6625 |
6287 | 6626 |
6288 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { | 6627 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { |
6360 addl(reg, offset); | 6699 addl(reg, offset); |
6361 } | 6700 } |
6362 | 6701 |
6363 bind (_is_positive); | 6702 bind (_is_positive); |
6364 sarl(reg, shift_value); | 6703 sarl(reg, shift_value); |
6704 } | |
6705 | |
6706 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { | |
6707 if (reachable(src)) { | |
6708 Assembler::divsd(dst, as_Address(src)); | |
6709 } else { | |
6710 lea(rscratch1, src); | |
6711 Assembler::divsd(dst, Address(rscratch1, 0)); | |
6712 } | |
6713 } | |
6714 | |
6715 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { | |
6716 if (reachable(src)) { | |
6717 Assembler::divss(dst, as_Address(src)); | |
6718 } else { | |
6719 lea(rscratch1, src); | |
6720 Assembler::divss(dst, Address(rscratch1, 0)); | |
6721 } | |
6365 } | 6722 } |
6366 | 6723 |
6367 // !defined(COMPILER2) is because of stupid core builds | 6724 // !defined(COMPILER2) is because of stupid core builds |
6368 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) | 6725 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) |
6369 void MacroAssembler::empty_FPU_stack() { | 6726 void MacroAssembler::empty_FPU_stack() { |
6413 void MacroAssembler::enter() { | 6770 void MacroAssembler::enter() { |
6414 push(rbp); | 6771 push(rbp); |
6415 mov(rbp, rsp); | 6772 mov(rbp, rsp); |
6416 } | 6773 } |
6417 | 6774 |
6775 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
6776 void MacroAssembler::fat_nop() { | |
6777 if (UseAddressNop) { | |
6778 addr_nop_5(); | |
6779 } else { | |
6780 emit_byte(0x26); // es: | |
6781 emit_byte(0x2e); // cs: | |
6782 emit_byte(0x64); // fs: | |
6783 emit_byte(0x65); // gs: | |
6784 emit_byte(0x90); | |
6785 } | |
6786 } | |
6787 | |
6418 void MacroAssembler::fcmp(Register tmp) { | 6788 void MacroAssembler::fcmp(Register tmp) { |
6419 fcmp(tmp, 1, true, true); | 6789 fcmp(tmp, 1, true, true); |
6420 } | 6790 } |
6421 | 6791 |
6422 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { | 6792 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { |
6801 | 7171 |
6802 void MacroAssembler::movptr(Address dst, Register src) { | 7172 void MacroAssembler::movptr(Address dst, Register src) { |
6803 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | 7173 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); |
6804 } | 7174 } |
6805 | 7175 |
7176 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { | |
7177 if (reachable(src)) { | |
7178 Assembler::movsd(dst, as_Address(src)); | |
7179 } else { | |
7180 lea(rscratch1, src); | |
7181 Assembler::movsd(dst, Address(rscratch1, 0)); | |
7182 } | |
7183 } | |
7184 | |
6806 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { | 7185 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { |
6807 if (reachable(src)) { | 7186 if (reachable(src)) { |
6808 movss(dst, as_Address(src)); | 7187 Assembler::movss(dst, as_Address(src)); |
6809 } else { | 7188 } else { |
6810 lea(rscratch1, src); | 7189 lea(rscratch1, src); |
6811 movss(dst, Address(rscratch1, 0)); | 7190 Assembler::movss(dst, Address(rscratch1, 0)); |
7191 } | |
7192 } | |
7193 | |
7194 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { | |
7195 if (reachable(src)) { | |
7196 Assembler::mulsd(dst, as_Address(src)); | |
7197 } else { | |
7198 lea(rscratch1, src); | |
7199 Assembler::mulsd(dst, Address(rscratch1, 0)); | |
7200 } | |
7201 } | |
7202 | |
7203 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { | |
7204 if (reachable(src)) { | |
7205 Assembler::mulss(dst, as_Address(src)); | |
7206 } else { | |
7207 lea(rscratch1, src); | |
7208 Assembler::mulss(dst, Address(rscratch1, 0)); | |
6812 } | 7209 } |
6813 } | 7210 } |
6814 | 7211 |
6815 void MacroAssembler::null_check(Register reg, int offset) { | 7212 void MacroAssembler::null_check(Register reg, int offset) { |
6816 if (needs_explicit_null_check(offset)) { | 7213 if (needs_explicit_null_check(offset)) { |
6988 void MacroAssembler::testl(Register dst, AddressLiteral src) { | 7385 void MacroAssembler::testl(Register dst, AddressLiteral src) { |
6989 assert(reachable(src), "Address should be reachable"); | 7386 assert(reachable(src), "Address should be reachable"); |
6990 testl(dst, as_Address(src)); | 7387 testl(dst, as_Address(src)); |
6991 } | 7388 } |
6992 | 7389 |
7390 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { | |
7391 if (reachable(src)) { | |
7392 Assembler::sqrtsd(dst, as_Address(src)); | |
7393 } else { | |
7394 lea(rscratch1, src); | |
7395 Assembler::sqrtsd(dst, Address(rscratch1, 0)); | |
7396 } | |
7397 } | |
7398 | |
7399 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { | |
7400 if (reachable(src)) { | |
7401 Assembler::sqrtss(dst, as_Address(src)); | |
7402 } else { | |
7403 lea(rscratch1, src); | |
7404 Assembler::sqrtss(dst, Address(rscratch1, 0)); | |
7405 } | |
7406 } | |
7407 | |
7408 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { | |
7409 if (reachable(src)) { | |
7410 Assembler::subsd(dst, as_Address(src)); | |
7411 } else { | |
7412 lea(rscratch1, src); | |
7413 Assembler::subsd(dst, Address(rscratch1, 0)); | |
7414 } | |
7415 } | |
7416 | |
7417 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { | |
7418 if (reachable(src)) { | |
7419 Assembler::subss(dst, as_Address(src)); | |
7420 } else { | |
7421 lea(rscratch1, src); | |
7422 Assembler::subss(dst, Address(rscratch1, 0)); | |
7423 } | |
7424 } | |
7425 | |
7426 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { | |
7427 if (reachable(src)) { | |
7428 Assembler::ucomisd(dst, as_Address(src)); | |
7429 } else { | |
7430 lea(rscratch1, src); | |
7431 Assembler::ucomisd(dst, Address(rscratch1, 0)); | |
7432 } | |
7433 } | |
7434 | |
7435 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { | |
7436 if (reachable(src)) { | |
7437 Assembler::ucomiss(dst, as_Address(src)); | |
7438 } else { | |
7439 lea(rscratch1, src); | |
7440 Assembler::ucomiss(dst, Address(rscratch1, 0)); | |
7441 } | |
7442 } | |
7443 | |
7444 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { | |
7445 // Used in sign-bit flipping with aligned address. | |
7446 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
7447 if (reachable(src)) { | |
7448 Assembler::xorpd(dst, as_Address(src)); | |
7449 } else { | |
7450 lea(rscratch1, src); | |
7451 Assembler::xorpd(dst, Address(rscratch1, 0)); | |
7452 } | |
7453 } | |
7454 | |
7455 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { | |
7456 // Used in sign-bit flipping with aligned address. | |
7457 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
7458 if (reachable(src)) { | |
7459 Assembler::xorps(dst, as_Address(src)); | |
7460 } else { | |
7461 lea(rscratch1, src); | |
7462 Assembler::xorps(dst, Address(rscratch1, 0)); | |
7463 } | |
7464 } | |
7465 | |
7466 // AVX 3-operands instructions | |
7467 | |
7468 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7469 if (reachable(src)) { | |
7470 vaddsd(dst, nds, as_Address(src)); | |
7471 } else { | |
7472 lea(rscratch1, src); | |
7473 vaddsd(dst, nds, Address(rscratch1, 0)); | |
7474 } | |
7475 } | |
7476 | |
7477 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7478 if (reachable(src)) { | |
7479 vaddss(dst, nds, as_Address(src)); | |
7480 } else { | |
7481 lea(rscratch1, src); | |
7482 vaddss(dst, nds, Address(rscratch1, 0)); | |
7483 } | |
7484 } | |
7485 | |
7486 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7487 if (reachable(src)) { | |
7488 vandpd(dst, nds, as_Address(src)); | |
7489 } else { | |
7490 lea(rscratch1, src); | |
7491 vandpd(dst, nds, Address(rscratch1, 0)); | |
7492 } | |
7493 } | |
7494 | |
7495 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7496 if (reachable(src)) { | |
7497 vandps(dst, nds, as_Address(src)); | |
7498 } else { | |
7499 lea(rscratch1, src); | |
7500 vandps(dst, nds, Address(rscratch1, 0)); | |
7501 } | |
7502 } | |
7503 | |
7504 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7505 if (reachable(src)) { | |
7506 vdivsd(dst, nds, as_Address(src)); | |
7507 } else { | |
7508 lea(rscratch1, src); | |
7509 vdivsd(dst, nds, Address(rscratch1, 0)); | |
7510 } | |
7511 } | |
7512 | |
7513 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7514 if (reachable(src)) { | |
7515 vdivss(dst, nds, as_Address(src)); | |
7516 } else { | |
7517 lea(rscratch1, src); | |
7518 vdivss(dst, nds, Address(rscratch1, 0)); | |
7519 } | |
7520 } | |
7521 | |
7522 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7523 if (reachable(src)) { | |
7524 vmulsd(dst, nds, as_Address(src)); | |
7525 } else { | |
7526 lea(rscratch1, src); | |
7527 vmulsd(dst, nds, Address(rscratch1, 0)); | |
7528 } | |
7529 } | |
7530 | |
7531 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7532 if (reachable(src)) { | |
7533 vmulss(dst, nds, as_Address(src)); | |
7534 } else { | |
7535 lea(rscratch1, src); | |
7536 vmulss(dst, nds, Address(rscratch1, 0)); | |
7537 } | |
7538 } | |
7539 | |
7540 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7541 if (reachable(src)) { | |
7542 vsubsd(dst, nds, as_Address(src)); | |
7543 } else { | |
7544 lea(rscratch1, src); | |
7545 vsubsd(dst, nds, Address(rscratch1, 0)); | |
7546 } | |
7547 } | |
7548 | |
7549 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7550 if (reachable(src)) { | |
7551 vsubss(dst, nds, as_Address(src)); | |
7552 } else { | |
7553 lea(rscratch1, src); | |
7554 vsubss(dst, nds, Address(rscratch1, 0)); | |
7555 } | |
7556 } | |
7557 | |
7558 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7559 if (reachable(src)) { | |
7560 vxorpd(dst, nds, as_Address(src)); | |
7561 } else { | |
7562 lea(rscratch1, src); | |
7563 vxorpd(dst, nds, Address(rscratch1, 0)); | |
7564 } | |
7565 } | |
7566 | |
7567 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7568 if (reachable(src)) { | |
7569 vxorps(dst, nds, as_Address(src)); | |
7570 } else { | |
7571 lea(rscratch1, src); | |
7572 vxorps(dst, nds, Address(rscratch1, 0)); | |
7573 } | |
7574 } | |
7575 | |
7576 | |
6993 ////////////////////////////////////////////////////////////////////////////////// | 7577 ////////////////////////////////////////////////////////////////////////////////// |
6994 #ifndef SERIALGC | 7578 #ifndef SERIALGC |
6995 | 7579 |
6996 void MacroAssembler::g1_write_barrier_pre(Register obj, | 7580 void MacroAssembler::g1_write_barrier_pre(Register obj, |
6997 Register pre_val, | 7581 Register pre_val, |
7258 | 7842 |
7259 void MacroAssembler::subptr(Register dst, int32_t imm32) { | 7843 void MacroAssembler::subptr(Register dst, int32_t imm32) { |
7260 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); | 7844 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); |
7261 } | 7845 } |
7262 | 7846 |
7847 // Force generation of a 4 byte immediate value even if it fits into 8bit | |
7848 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { | |
7849 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); | |
7850 } | |
7851 | |
7263 void MacroAssembler::subptr(Register dst, Register src) { | 7852 void MacroAssembler::subptr(Register dst, Register src) { |
7264 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); | 7853 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); |
7265 } | 7854 } |
7266 | 7855 |
7267 // C++ bool manipulation | 7856 // C++ bool manipulation |
7426 | 8015 |
7427 void MacroAssembler::incr_allocated_bytes(Register thread, | 8016 void MacroAssembler::incr_allocated_bytes(Register thread, |
7428 Register var_size_in_bytes, | 8017 Register var_size_in_bytes, |
7429 int con_size_in_bytes, | 8018 int con_size_in_bytes, |
7430 Register t1) { | 8019 Register t1) { |
8020 if (!thread->is_valid()) { | |
8021 #ifdef _LP64 | |
8022 thread = r15_thread; | |
8023 #else | |
8024 assert(t1->is_valid(), "need temp reg"); | |
8025 thread = t1; | |
8026 get_thread(thread); | |
8027 #endif | |
8028 } | |
8029 | |
7431 #ifdef _LP64 | 8030 #ifdef _LP64 |
7432 if (var_size_in_bytes->is_valid()) { | 8031 if (var_size_in_bytes->is_valid()) { |
7433 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); | 8032 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); |
7434 } else { | 8033 } else { |
7435 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); | 8034 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); |
7436 } | 8035 } |
7437 #else | 8036 #else |
7438 if (!thread->is_valid()) { | |
7439 assert(t1->is_valid(), "need temp reg"); | |
7440 thread = t1; | |
7441 get_thread(thread); | |
7442 } | |
7443 | |
7444 if (var_size_in_bytes->is_valid()) { | 8037 if (var_size_in_bytes->is_valid()) { |
7445 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); | 8038 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); |
7446 } else { | 8039 } else { |
7447 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); | 8040 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); |
7448 } | 8041 } |
7681 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } | 8274 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
7682 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } | 8275 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
7683 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } | 8276 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } |
7684 assert(label_nulls <= 1, "at most one NULL in the batch"); | 8277 assert(label_nulls <= 1, "at most one NULL in the batch"); |
7685 | 8278 |
7686 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + | 8279 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); |
7687 Klass::secondary_super_cache_offset_in_bytes()); | 8280 int sco_offset = in_bytes(Klass::super_check_offset_offset()); |
7688 int sco_offset = (klassOopDesc::header_size() * HeapWordSize + | |
7689 Klass::super_check_offset_offset_in_bytes()); | |
7690 Address super_check_offset_addr(super_klass, sco_offset); | 8281 Address super_check_offset_addr(super_klass, sco_offset); |
7691 | 8282 |
7692 // Hacked jcc, which "knows" that L_fallthrough, at least, is in | 8283 // Hacked jcc, which "knows" that L_fallthrough, at least, is in |
7693 // range of a jccb. If this routine grows larger, reconsider at | 8284 // range of a jccb. If this routine grows larger, reconsider at |
7694 // least some of these. | 8285 // least some of these. |
7782 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } | 8373 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
7783 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } | 8374 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
7784 assert(label_nulls <= 1, "at most one NULL in the batch"); | 8375 assert(label_nulls <= 1, "at most one NULL in the batch"); |
7785 | 8376 |
7786 // a couple of useful fields in sub_klass: | 8377 // a couple of useful fields in sub_klass: |
7787 int ss_offset = (klassOopDesc::header_size() * HeapWordSize + | 8378 int ss_offset = in_bytes(Klass::secondary_supers_offset()); |
7788 Klass::secondary_supers_offset_in_bytes()); | 8379 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); |
7789 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + | |
7790 Klass::secondary_super_cache_offset_in_bytes()); | |
7791 Address secondary_supers_addr(sub_klass, ss_offset); | 8380 Address secondary_supers_addr(sub_klass, ss_offset); |
7792 Address super_cache_addr( sub_klass, sc_offset); | 8381 Address super_cache_addr( sub_klass, sc_offset); |
7793 | 8382 |
7794 // Do a linear scan of the secondary super-klass chain. | 8383 // Do a linear scan of the secondary super-klass chain. |
7795 // This code is rarely used, so simplicity is a virtue here. | 8384 // This code is rarely used, so simplicity is a virtue here. |
7871 #undef IS_A_TEMP | 8460 #undef IS_A_TEMP |
7872 | 8461 |
7873 bind(L_fallthrough); | 8462 bind(L_fallthrough); |
7874 } | 8463 } |
7875 | 8464 |
7876 | |
7877 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { | |
7878 ucomisd(dst, as_Address(src)); | |
7879 } | |
7880 | |
7881 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { | |
7882 ucomiss(dst, as_Address(src)); | |
7883 } | |
7884 | |
7885 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { | |
7886 if (reachable(src)) { | |
7887 xorpd(dst, as_Address(src)); | |
7888 } else { | |
7889 lea(rscratch1, src); | |
7890 xorpd(dst, Address(rscratch1, 0)); | |
7891 } | |
7892 } | |
7893 | |
7894 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { | |
7895 if (reachable(src)) { | |
7896 xorps(dst, as_Address(src)); | |
7897 } else { | |
7898 lea(rscratch1, src); | |
7899 xorps(dst, Address(rscratch1, 0)); | |
7900 } | |
7901 } | |
7902 | 8465 |
7903 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { | 8466 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { |
7904 if (VM_Version::supports_cmov()) { | 8467 if (VM_Version::supports_cmov()) { |
7905 cmovl(cc, dst, src); | 8468 cmovl(cc, dst, src); |
7906 } else { | 8469 } else { |
8483 assert (Universe::heap() != NULL, "java heap should be initialized"); | 9046 assert (Universe::heap() != NULL, "java heap should be initialized"); |
8484 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); | 9047 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
8485 if (Universe::narrow_oop_shift() != 0) { | 9048 if (Universe::narrow_oop_shift() != 0) { |
8486 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); | 9049 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
8487 if (LogMinObjAlignmentInBytes == Address::times_8) { | 9050 if (LogMinObjAlignmentInBytes == Address::times_8) { |
8488 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | 9051 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset())); |
8489 } else { | 9052 } else { |
8490 // OK to use shift since we don't need to preserve flags. | 9053 // OK to use shift since we don't need to preserve flags. |
8491 shlq(dst, LogMinObjAlignmentInBytes); | 9054 shlq(dst, LogMinObjAlignmentInBytes); |
8492 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | 9055 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset())); |
8493 } | 9056 } |
8494 } else { | 9057 } else { |
8495 movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | 9058 movq(dst, Address(dst, Klass::prototype_header_offset())); |
8496 } | 9059 } |
8497 } else | 9060 } else |
8498 #endif | 9061 #endif |
8499 { | 9062 { |
8500 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); | 9063 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
8501 movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | 9064 movptr(dst, Address(dst, Klass::prototype_header_offset())); |
8502 } | 9065 } |
8503 } | 9066 } |
8504 | 9067 |
8505 void MacroAssembler::store_klass(Register dst, Register src) { | 9068 void MacroAssembler::store_klass(Register dst, Register src) { |
8506 #ifdef _LP64 | 9069 #ifdef _LP64 |
8751 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); | 9314 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
8752 } | 9315 } |
8753 } | 9316 } |
8754 #endif // _LP64 | 9317 #endif // _LP64 |
8755 | 9318 |
9319 | |
9320 // C2 compiled method's prolog code. | |
9321 void MacroAssembler::verified_entry(int framesize, bool stack_bang, bool fp_mode_24b) { | |
9322 | |
9323 // WARNING: Initial instruction MUST be 5 bytes or longer so that | |
9324 // NativeJump::patch_verified_entry will be able to patch out the entry | |
9325 // code safely. The push to verify stack depth is ok at 5 bytes, | |
9326 // the frame allocation can be either 3 or 6 bytes. So if we don't do | |
9327 // stack bang then we must use the 6 byte frame allocation even if | |
9328 // we have no frame. :-( | |
9329 | |
9330 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
9331 // Remove word for return addr | |
9332 framesize -= wordSize; | |
9333 | |
9334 // Calls to C2R adapters often do not accept exceptional returns. | |
9335 // We require that their callers must bang for them. But be careful, because | |
9336 // some VM calls (such as call site linkage) can use several kilobytes of | |
9337 // stack. But the stack safety zone should account for that. | |
9338 // See bugs 4446381, 4468289, 4497237. | |
9339 if (stack_bang) { | |
9340 generate_stack_overflow_check(framesize); | |
9341 | |
9342 // We always push rbp, so that on return to interpreter rbp, will be | |
9343 // restored correctly and we can correct the stack. | |
9344 push(rbp); | |
9345 // Remove word for ebp | |
9346 framesize -= wordSize; | |
9347 | |
9348 // Create frame | |
9349 if (framesize) { | |
9350 subptr(rsp, framesize); | |
9351 } | |
9352 } else { | |
9353 // Create frame (force generation of a 4 byte immediate value) | |
9354 subptr_imm32(rsp, framesize); | |
9355 | |
9356 // Save RBP register now. | |
9357 framesize -= wordSize; | |
9358 movptr(Address(rsp, framesize), rbp); | |
9359 } | |
9360 | |
9361 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth | |
9362 framesize -= wordSize; | |
9363 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); | |
9364 } | |
9365 | |
9366 #ifndef _LP64 | |
9367 // If method sets FPU control word do it now | |
9368 if (fp_mode_24b) { | |
9369 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
9370 } | |
9371 if (UseSSE >= 2 && VerifyFPU) { | |
9372 verify_FPU(0, "FPU stack must be clean on entry"); | |
9373 } | |
9374 #endif | |
9375 | |
9376 #ifdef ASSERT | |
9377 if (VerifyStackAtCalls) { | |
9378 Label L; | |
9379 push(rax); | |
9380 mov(rax, rsp); | |
9381 andptr(rax, StackAlignmentInBytes-1); | |
9382 cmpptr(rax, StackAlignmentInBytes-wordSize); | |
9383 pop(rax); | |
9384 jcc(Assembler::equal, L); | |
9385 stop("Stack is not properly aligned!"); | |
9386 bind(L); | |
9387 } | |
9388 #endif | |
9389 | |
9390 } | |
9391 | |
9392 | |
8756 // IndexOf for constant substrings with size >= 8 chars | 9393 // IndexOf for constant substrings with size >= 8 chars |
8757 // which don't need to be loaded through stack. | 9394 // which don't need to be loaded through stack. |
8758 void MacroAssembler::string_indexofC8(Register str1, Register str2, | 9395 void MacroAssembler::string_indexofC8(Register str1, Register str2, |
8759 Register cnt1, Register cnt2, | 9396 Register cnt1, Register cnt2, |
8760 int int_cnt2, Register result, | 9397 int int_cnt2, Register result, |
8761 XMMRegister vec, Register tmp) { | 9398 XMMRegister vec, Register tmp) { |
9399 ShortBranchVerifier sbv(this); | |
8762 assert(UseSSE42Intrinsics, "SSE4.2 is required"); | 9400 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
8763 | 9401 |
8764 // This method uses pcmpestri inxtruction with bound registers | 9402 // This method uses pcmpestri inxtruction with bound registers |
8765 // inputs: | 9403 // inputs: |
8766 // xmm - substring | 9404 // xmm - substring |
8886 addptr(tmp, cnt2); | 9524 addptr(tmp, cnt2); |
8887 movdqu(vec, Address(str2, tmp, Address::times_2, 0)); | 9525 movdqu(vec, Address(str2, tmp, Address::times_2, 0)); |
8888 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d); | 9526 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d); |
8889 } | 9527 } |
8890 // Need to reload strings pointers if not matched whole vector | 9528 // Need to reload strings pointers if not matched whole vector |
8891 jccb(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 | 9529 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 |
8892 addptr(cnt2, 8); | 9530 addptr(cnt2, 8); |
8893 jccb(Assembler::negative, SCAN_SUBSTR); | 9531 jcc(Assembler::negative, SCAN_SUBSTR); |
8894 // Fall through if found full substring | 9532 // Fall through if found full substring |
8895 | 9533 |
8896 } // (int_cnt2 > 8) | 9534 } // (int_cnt2 > 8) |
8897 | 9535 |
8898 bind(RET_FOUND); | 9536 bind(RET_FOUND); |
8907 // Small strings are loaded through stack if they cross page boundary. | 9545 // Small strings are loaded through stack if they cross page boundary. |
8908 void MacroAssembler::string_indexof(Register str1, Register str2, | 9546 void MacroAssembler::string_indexof(Register str1, Register str2, |
8909 Register cnt1, Register cnt2, | 9547 Register cnt1, Register cnt2, |
8910 int int_cnt2, Register result, | 9548 int int_cnt2, Register result, |
8911 XMMRegister vec, Register tmp) { | 9549 XMMRegister vec, Register tmp) { |
9550 ShortBranchVerifier sbv(this); | |
8912 assert(UseSSE42Intrinsics, "SSE4.2 is required"); | 9551 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
8913 // | 9552 // |
8914 // int_cnt2 is length of small (< 8 chars) constant substring | 9553 // int_cnt2 is length of small (< 8 chars) constant substring |
8915 // or (-1) for non constant substring in which case its length | 9554 // or (-1) for non constant substring in which case its length |
8916 // is in cnt2 register. | 9555 // is in cnt2 register. |
9168 | 9807 |
9169 // Compare strings. | 9808 // Compare strings. |
9170 void MacroAssembler::string_compare(Register str1, Register str2, | 9809 void MacroAssembler::string_compare(Register str1, Register str2, |
9171 Register cnt1, Register cnt2, Register result, | 9810 Register cnt1, Register cnt2, Register result, |
9172 XMMRegister vec1) { | 9811 XMMRegister vec1) { |
9812 ShortBranchVerifier sbv(this); | |
9173 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; | 9813 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; |
9174 | 9814 |
9175 // Compute the minimum of the string lengths and the | 9815 // Compute the minimum of the string lengths and the |
9176 // difference of the string lengths (stack). | 9816 // difference of the string lengths (stack). |
9177 // Do the conditional move stuff | 9817 // Do the conditional move stuff |
9304 | 9944 |
9305 // Compare char[] arrays aligned to 4 bytes or substrings. | 9945 // Compare char[] arrays aligned to 4 bytes or substrings. |
9306 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, | 9946 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
9307 Register limit, Register result, Register chr, | 9947 Register limit, Register result, Register chr, |
9308 XMMRegister vec1, XMMRegister vec2) { | 9948 XMMRegister vec1, XMMRegister vec2) { |
9949 ShortBranchVerifier sbv(this); | |
9309 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; | 9950 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; |
9310 | 9951 |
9311 int length_offset = arrayOopDesc::length_offset_in_bytes(); | 9952 int length_offset = arrayOopDesc::length_offset_in_bytes(); |
9312 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | 9953 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); |
9313 | 9954 |
9423 | 10064 |
9424 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") | 10065 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") |
9425 void MacroAssembler::generate_fill(BasicType t, bool aligned, | 10066 void MacroAssembler::generate_fill(BasicType t, bool aligned, |
9426 Register to, Register value, Register count, | 10067 Register to, Register value, Register count, |
9427 Register rtmp, XMMRegister xtmp) { | 10068 Register rtmp, XMMRegister xtmp) { |
10069 ShortBranchVerifier sbv(this); | |
9428 assert_different_registers(to, value, count, rtmp); | 10070 assert_different_registers(to, value, count, rtmp); |
9429 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; | 10071 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; |
9430 Label L_fill_2_bytes, L_fill_4_bytes; | 10072 Label L_fill_2_bytes, L_fill_4_bytes; |
9431 | 10073 |
9432 int shift = -1; | 10074 int shift = -1; |