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comparison src/cpu/sparc/vm/sparc.ad @ 1575:3657cb01ffc5

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6954029: Improve implicit null check generation with compressed oops Summary: Hoist DecodeN instruction above null check Reviewed-by: never, twisti
author kvn
date Wed, 02 Jun 2010 09:49:32 -0700
parents 2d127394260e
children e9ff18c4ace7
comparison
equal deleted inserted replaced
1574:1eb493f33423 1575:3657cb01ffc5
1757 1757
1758 // Should the Matcher clone shifts on addressing modes, expecting them to 1758 // Should the Matcher clone shifts on addressing modes, expecting them to
1759 // be subsumed into complex addressing expressions or compute them into 1759 // be subsumed into complex addressing expressions or compute them into
1760 // registers? True for Intel but false for most RISCs 1760 // registers? True for Intel but false for most RISCs
1761 const bool Matcher::clone_shift_expressions = false; 1761 const bool Matcher::clone_shift_expressions = false;
1762
1763 bool Matcher::narrow_oop_use_complex_address() {
1764 NOT_LP64(ShouldNotCallThis());
1765 assert(UseCompressedOops, "only for compressed oops code");
1766 return false;
1767 }
1762 1768
1763 // Is it better to copy float constants, or load them directly from memory? 1769 // Is it better to copy float constants, or load them directly from memory?
1764 // Intel can load a float constant from a direct address, requiring no 1770 // Intel can load a float constant from a direct address, requiring no
1765 // extra registers. Most RISCs will have to materialize an address into a 1771 // extra registers. Most RISCs will have to materialize an address into a
1766 // register first, so they would do better to copy the constant from stack. 1772 // register first, so they would do better to copy the constant from stack.