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comparison src/cpu/sparc/vm/sparc.ad @ 558:3b5ac9e7e6ea

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6796746: rename LoadC (char) opcode class to LoadUS (unsigned short) Summary: Renaming LoadC to LoadUS would round up the planned introduction of LoadUB and LoadUI. Reviewed-by: phh, kvn
author twisti
date Mon, 26 Jan 2009 16:22:12 +0100
parents 6c4cda924d2e
children 0fbdb4381b99 98cb887364d3
comparison
equal deleted inserted replaced
557:465813e0303a 558:3b5ac9e7e6ea
760 case Assembler::std_op3: st_op = Op_StoreL; break; 760 case Assembler::std_op3: st_op = Op_StoreL; break;
761 case Assembler::stf_op3: st_op = Op_StoreF; break; 761 case Assembler::stf_op3: st_op = Op_StoreF; break;
762 case Assembler::stdf_op3: st_op = Op_StoreD; break; 762 case Assembler::stdf_op3: st_op = Op_StoreD; break;
763 763
764 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 764 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
765 case Assembler::lduh_op3: ld_op = Op_LoadC; break; 765 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
766 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 766 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
767 case Assembler::ldx_op3: // may become LoadP or stay LoadI 767 case Assembler::ldx_op3: // may become LoadP or stay LoadI
768 case Assembler::ldsw_op3: // may become LoadP or stay LoadI 768 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
769 case Assembler::lduw_op3: ld_op = Op_LoadI; break; 769 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
770 case Assembler::ldd_op3: ld_op = Op_LoadL; break; 770 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
5314 opcode(Assembler::ldub_op3); 5314 opcode(Assembler::ldub_op3);
5315 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5315 ins_encode(simple_form3_mem_reg( mem, dst ) );
5316 ins_pipe(iload_mask_mem); 5316 ins_pipe(iload_mask_mem);
5317 %} 5317 %}
5318 5318
5319 // Load Char (16bit UNsigned) into a Long Register 5319 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5320 instruct loadUCL(iRegL dst, memory mem, immL_FFFF bytemask) %{ 5320 instruct loadUS2L(iRegL dst, memory mem, immL_FFFF bytemask) %{
5321 match(Set dst (AndL (ConvI2L (LoadC mem)) bytemask)); 5321 match(Set dst (AndL (ConvI2L (LoadUS mem)) bytemask));
5322 ins_cost(MEMORY_REF_COST); 5322 ins_cost(MEMORY_REF_COST);
5323 5323
5324 size(4); 5324 size(4);
5325 format %{ "LDUH $mem,$dst" %} 5325 format %{ "LDUH $mem,$dst" %}
5326 opcode(Assembler::lduh_op3); 5326 opcode(Assembler::lduh_op3);
5327 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5327 ins_encode(simple_form3_mem_reg( mem, dst ) );
5328 ins_pipe(iload_mask_mem); 5328 ins_pipe(iload_mask_mem);
5329 %} 5329 %}
5330 5330
5331 // Load Char (16bit unsigned) 5331 // Load Unsigned Short/Char (16bit unsigned)
5332 instruct loadC(iRegI dst, memory mem) %{ 5332 instruct loadUS(iRegI dst, memory mem) %{
5333 match(Set dst (LoadC mem)); 5333 match(Set dst (LoadUS mem));
5334 ins_cost(MEMORY_REF_COST); 5334 ins_cost(MEMORY_REF_COST);
5335 5335
5336 size(4); 5336 size(4);
5337 format %{ "LDUH $mem,$dst" %} 5337 format %{ "LDUH $mem,$dst" %}
5338 opcode(Assembler::lduh_op3); 5338 opcode(Assembler::lduh_op3);