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comparison src/cpu/x86/vm/x86_32.ad @ 71:3d62cb85208d

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6662967: Optimize I2D conversion on new x86 Summary: Use CVTDQ2PS and CVTDQ2PD for integer values conversions to float and double values on new AMD cpu. Reviewed-by: sgoldman, never
author kvn
date Wed, 19 Mar 2008 15:33:25 -0700
parents a61af66fc99e
children ba764ed4b6f2
comparison
equal deleted inserted replaced
70:b683f557224b 71:3d62cb85208d
10968 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst)); 10968 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
10969 ins_pipe( fpu_reg_mem ); 10969 ins_pipe( fpu_reg_mem );
10970 %} 10970 %}
10971 10971
10972 instruct convI2XD_reg(regXD dst, eRegI src) %{ 10972 instruct convI2XD_reg(regXD dst, eRegI src) %{
10973 predicate( UseSSE>=2 ); 10973 predicate( UseSSE>=2 && !UseXmmI2D );
10974 match(Set dst (ConvI2D src)); 10974 match(Set dst (ConvI2D src));
10975 format %{ "CVTSI2SD $dst,$src" %} 10975 format %{ "CVTSI2SD $dst,$src" %}
10976 opcode(0xF2, 0x0F, 0x2A); 10976 opcode(0xF2, 0x0F, 0x2A);
10977 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); 10977 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
10978 ins_pipe( pipe_slow ); 10978 ins_pipe( pipe_slow );
10983 match(Set dst (ConvI2D (LoadI mem))); 10983 match(Set dst (ConvI2D (LoadI mem)));
10984 format %{ "CVTSI2SD $dst,$mem" %} 10984 format %{ "CVTSI2SD $dst,$mem" %}
10985 opcode(0xF2, 0x0F, 0x2A); 10985 opcode(0xF2, 0x0F, 0x2A);
10986 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem)); 10986 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
10987 ins_pipe( pipe_slow ); 10987 ins_pipe( pipe_slow );
10988 %}
10989
10990 instruct convXI2XD_reg(regXD dst, eRegI src)
10991 %{
10992 predicate( UseSSE>=2 && UseXmmI2D );
10993 match(Set dst (ConvI2D src));
10994
10995 format %{ "MOVD $dst,$src\n\t"
10996 "CVTDQ2PD $dst,$dst\t# i2d" %}
10997 ins_encode %{
10998 __ movd($dst$$XMMRegister, $src$$Register);
10999 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11000 %}
11001 ins_pipe(pipe_slow); // XXX
10988 %} 11002 %}
10989 11003
10990 instruct convI2D_mem(regD dst, memory mem) %{ 11004 instruct convI2D_mem(regD dst, memory mem) %{
10991 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); 11005 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
10992 match(Set dst (ConvI2D (LoadI mem))); 11006 match(Set dst (ConvI2D (LoadI mem)));
11060 ins_pipe( fpu_reg_mem ); 11074 ins_pipe( fpu_reg_mem );
11061 %} 11075 %}
11062 11076
11063 // Convert an int to a float in xmm; no rounding step needed. 11077 // Convert an int to a float in xmm; no rounding step needed.
11064 instruct convI2X_reg(regX dst, eRegI src) %{ 11078 instruct convI2X_reg(regX dst, eRegI src) %{
11065 predicate(UseSSE>=1); 11079 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11066 match(Set dst (ConvI2F src)); 11080 match(Set dst (ConvI2F src));
11067 format %{ "CVTSI2SS $dst, $src" %} 11081 format %{ "CVTSI2SS $dst, $src" %}
11068 11082
11069 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */ 11083 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
11070 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); 11084 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11071 ins_pipe( pipe_slow ); 11085 ins_pipe( pipe_slow );
11086 %}
11087
11088 instruct convXI2X_reg(regX dst, eRegI src)
11089 %{
11090 predicate( UseSSE>=2 && UseXmmI2F );
11091 match(Set dst (ConvI2F src));
11092
11093 format %{ "MOVD $dst,$src\n\t"
11094 "CVTDQ2PS $dst,$dst\t# i2f" %}
11095 ins_encode %{
11096 __ movd($dst$$XMMRegister, $src$$Register);
11097 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11098 %}
11099 ins_pipe(pipe_slow); // XXX
11072 %} 11100 %}
11073 11101
11074 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{ 11102 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11075 match(Set dst (ConvI2L src)); 11103 match(Set dst (ConvI2L src));
11076 effect(KILL cr); 11104 effect(KILL cr);