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comparison src/cpu/x86/vm/x86_64.ad @ 71:3d62cb85208d

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6662967: Optimize I2D conversion on new x86 Summary: Use CVTDQ2PS and CVTDQ2PD for integer values conversions to float and double values on new AMD cpu. Reviewed-by: sgoldman, never
author kvn
date Wed, 19 Mar 2008 15:33:25 -0700
parents a61af66fc99e
children ba764ed4b6f2
comparison
equal deleted inserted replaced
70:b683f557224b 71:3d62cb85208d
10096 ins_pipe(pipe_slow); 10096 ins_pipe(pipe_slow);
10097 %} 10097 %}
10098 10098
10099 instruct convI2F_reg_reg(regF dst, rRegI src) 10099 instruct convI2F_reg_reg(regF dst, rRegI src)
10100 %{ 10100 %{
10101 predicate(!UseXmmI2F);
10101 match(Set dst (ConvI2F src)); 10102 match(Set dst (ConvI2F src));
10102 10103
10103 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} 10104 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10104 opcode(0xF3, 0x0F, 0x2A); 10105 opcode(0xF3, 0x0F, 0x2A);
10105 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); 10106 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10116 ins_pipe(pipe_slow); // XXX 10117 ins_pipe(pipe_slow); // XXX
10117 %} 10118 %}
10118 10119
10119 instruct convI2D_reg_reg(regD dst, rRegI src) 10120 instruct convI2D_reg_reg(regD dst, rRegI src)
10120 %{ 10121 %{
10122 predicate(!UseXmmI2D);
10121 match(Set dst (ConvI2D src)); 10123 match(Set dst (ConvI2D src));
10122 10124
10123 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} 10125 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10124 opcode(0xF2, 0x0F, 0x2A); 10126 opcode(0xF2, 0x0F, 0x2A);
10125 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); 10127 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10131 match(Set dst (ConvI2D (LoadI src))); 10133 match(Set dst (ConvI2D (LoadI src)));
10132 10134
10133 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} 10135 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10134 opcode(0xF2, 0x0F, 0x2A); 10136 opcode(0xF2, 0x0F, 0x2A);
10135 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); 10137 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10138 ins_pipe(pipe_slow); // XXX
10139 %}
10140
10141 instruct convXI2F_reg(regF dst, rRegI src)
10142 %{
10143 predicate(UseXmmI2F);
10144 match(Set dst (ConvI2F src));
10145
10146 format %{ "movdl $dst, $src\n\t"
10147 "cvtdq2psl $dst, $dst\t# i2f" %}
10148 ins_encode %{
10149 __ movdl($dst$$XMMRegister, $src$$Register);
10150 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10151 %}
10152 ins_pipe(pipe_slow); // XXX
10153 %}
10154
10155 instruct convXI2D_reg(regD dst, rRegI src)
10156 %{
10157 predicate(UseXmmI2D);
10158 match(Set dst (ConvI2D src));
10159
10160 format %{ "movdl $dst, $src\n\t"
10161 "cvtdq2pdl $dst, $dst\t# i2d" %}
10162 ins_encode %{
10163 __ movdl($dst$$XMMRegister, $src$$Register);
10164 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10165 %}
10136 ins_pipe(pipe_slow); // XXX 10166 ins_pipe(pipe_slow); // XXX
10137 %} 10167 %}
10138 10168
10139 instruct convL2F_reg_reg(regF dst, rRegL src) 10169 instruct convL2F_reg_reg(regF dst, rRegL src)
10140 %{ 10170 %{