Mercurial > hg > truffle
comparison src/cpu/sparc/vm/sparc.ad @ 14457:45467c53f178
Merge
author | kvn |
---|---|
date | Tue, 28 Jan 2014 12:28:17 -0800 |
parents | abec000618bf 7e8bd81ce93e |
children | cd5d10655495 |
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14456:abec000618bf | 14457:45467c53f178 |
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3367 op_cost(0); | 3367 op_cost(0); |
3368 format %{ %} | 3368 format %{ %} |
3369 interface(CONST_INTER); | 3369 interface(CONST_INTER); |
3370 %} | 3370 %} |
3371 | 3371 |
3372 // Unsigned (positive) Integer Immediate: 13-bit | 3372 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13) |
3373 operand immU13() %{ | 3373 operand immU12() %{ |
3374 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | 3374 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); |
3375 match(ConI); | 3375 match(ConI); |
3376 op_cost(0); | 3376 op_cost(0); |
3377 | 3377 |
3378 format %{ %} | 3378 format %{ %} |
3399 | 3399 |
3400 // Integer Immediate: 5-bit | 3400 // Integer Immediate: 5-bit |
3401 operand immI5() %{ | 3401 operand immI5() %{ |
3402 predicate(Assembler::is_simm5(n->get_int())); | 3402 predicate(Assembler::is_simm5(n->get_int())); |
3403 match(ConI); | 3403 match(ConI); |
3404 op_cost(0); | |
3405 format %{ %} | |
3406 interface(CONST_INTER); | |
3407 %} | |
3408 | |
3409 // Int Immediate non-negative | |
3410 operand immU31() | |
3411 %{ | |
3412 predicate(n->get_int() >= 0); | |
3413 match(ConI); | |
3414 | |
3404 op_cost(0); | 3415 op_cost(0); |
3405 format %{ %} | 3416 format %{ %} |
3406 interface(CONST_INTER); | 3417 interface(CONST_INTER); |
3407 %} | 3418 %} |
3408 | 3419 |
5732 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | 5743 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ |
5733 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | 5744 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); |
5734 effect(TEMP dst, TEMP tmp); | 5745 effect(TEMP dst, TEMP tmp); |
5735 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | 5746 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); |
5736 | 5747 |
5737 size((3+1)*4); // set may use two instructions. | |
5738 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" | 5748 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
5739 "SET $mask,$tmp\n\t" | 5749 "SET $mask,$tmp\n\t" |
5740 "AND $dst,$tmp,$dst" %} | 5750 "AND $dst,$tmp,$dst" %} |
5741 ins_encode %{ | 5751 ins_encode %{ |
5742 Register Rdst = $dst$$Register; | 5752 Register Rdst = $dst$$Register; |
5854 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | 5864 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE |
5855 %} | 5865 %} |
5856 ins_pipe(iload_mem); | 5866 ins_pipe(iload_mem); |
5857 %} | 5867 %} |
5858 | 5868 |
5859 // Load Integer with a 13-bit mask into a Long Register | 5869 // Load Integer with a 12-bit mask into a Long Register |
5860 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | 5870 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{ |
5861 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | 5871 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
5862 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | 5872 ins_cost(MEMORY_REF_COST + DEFAULT_COST); |
5863 | 5873 |
5864 size(2*4); | 5874 size(2*4); |
5865 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" | 5875 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t" |
5866 "AND $dst,$mask,$dst" %} | 5876 "AND $dst,$mask,$dst" %} |
5867 ins_encode %{ | 5877 ins_encode %{ |
5868 Register Rdst = $dst$$Register; | 5878 Register Rdst = $dst$$Register; |
5869 __ lduw($mem$$Address, Rdst); | 5879 __ lduw($mem$$Address, Rdst); |
5870 __ and3(Rdst, $mask$$constant, Rdst); | 5880 __ and3(Rdst, $mask$$constant, Rdst); |
5871 %} | 5881 %} |
5872 ins_pipe(iload_mem); | 5882 ins_pipe(iload_mem); |
5873 %} | 5883 %} |
5874 | 5884 |
5875 // Load Integer with a 32-bit mask into a Long Register | 5885 // Load Integer with a 31-bit mask into a Long Register |
5876 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | 5886 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{ |
5877 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | 5887 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
5878 effect(TEMP dst, TEMP tmp); | 5888 effect(TEMP dst, TEMP tmp); |
5879 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | 5889 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); |
5880 | 5890 |
5881 size((3+1)*4); // set may use two instructions. | 5891 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t" |
5882 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" | |
5883 "SET $mask,$tmp\n\t" | 5892 "SET $mask,$tmp\n\t" |
5884 "AND $dst,$tmp,$dst" %} | 5893 "AND $dst,$tmp,$dst" %} |
5885 ins_encode %{ | 5894 ins_encode %{ |
5886 Register Rdst = $dst$$Register; | 5895 Register Rdst = $dst$$Register; |
5887 Register Rtmp = $tmp$$Register; | 5896 Register Rtmp = $tmp$$Register; |
8974 opcode(Assembler::andcc_op3, Assembler::arith_op); | 8983 opcode(Assembler::andcc_op3, Assembler::arith_op); |
8975 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | 8984 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); |
8976 ins_pipe(ialu_cconly_reg_reg); | 8985 ins_pipe(ialu_cconly_reg_reg); |
8977 %} | 8986 %} |
8978 | 8987 |
8979 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | 8988 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{ |
8980 match(Set icc (CmpU op1 op2)); | 8989 match(Set icc (CmpU op1 op2)); |
8981 | 8990 |
8982 size(4); | 8991 size(4); |
8983 format %{ "CMP $op1,$op2\t! unsigned" %} | 8992 format %{ "CMP $op1,$op2\t! unsigned" %} |
8984 opcode(Assembler::subcc_op3, Assembler::arith_op); | 8993 opcode(Assembler::subcc_op3, Assembler::arith_op); |