Mercurial > hg > truffle
comparison src/cpu/sparc/vm/sparc.ad @ 14909:4ca6dc0799b6
Backout jdk9 merge
author | Gilles Duboscq <duboscq@ssw.jku.at> |
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date | Tue, 01 Apr 2014 13:57:07 +0200 |
parents | cd5d10655495 |
children | 89152779163c |
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14908:8db6e76cb658 | 14909:4ca6dc0799b6 |
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755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | 755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); |
756 } | 756 } |
757 #endif | 757 #endif |
758 | 758 |
759 | 759 |
760 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary, | 760 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, |
761 int src1_enc, int disp32, int src2_enc, int dst_enc) { | 761 int src1_enc, int disp32, int src2_enc, int dst_enc) { |
762 | 762 |
763 #ifdef ASSERT | 763 #ifdef ASSERT |
764 // The following code implements the +VerifyOops feature. | 764 // The following code implements the +VerifyOops feature. |
765 // It verifies oop values which are loaded into or stored out of | 765 // It verifies oop values which are loaded into or stored out of |
910 | (src1_enc << 14); | 910 | (src1_enc << 14); |
911 | 911 |
912 uint index = src2_enc; | 912 uint index = src2_enc; |
913 int disp = disp32; | 913 int disp = disp32; |
914 | 914 |
915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) { | 915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) |
916 disp += STACK_BIAS; | 916 disp += STACK_BIAS; |
917 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not | |
918 if (!Assembler::is_simm13(disp)) { | |
919 ra->C->record_method_not_compilable("unable to handle large constant offsets"); | |
920 return; | |
921 } | |
922 } | |
923 | 917 |
924 // We should have a compiler bailout here rather than a guarantee. | 918 // We should have a compiler bailout here rather than a guarantee. |
925 // Better yet would be some mechanism to handle variable-size matches correctly. | 919 // Better yet would be some mechanism to handle variable-size matches correctly. |
926 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | 920 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); |
927 | 921 |
1038 } | 1032 } |
1039 return offset; | 1033 return offset; |
1040 } | 1034 } |
1041 } | 1035 } |
1042 | 1036 |
1043 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } | |
1044 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { | |
1045 ShouldNotReachHere(); | |
1046 } | |
1047 | |
1048 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { | 1037 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
1049 Compile* C = ra_->C; | 1038 Compile* C = ra_->C; |
1050 Compile::ConstantTable& constant_table = C->constant_table(); | 1039 Compile::ConstantTable& constant_table = C->constant_table(); |
1051 MacroAssembler _masm(&cbuf); | 1040 MacroAssembler _masm(&cbuf); |
1052 | 1041 |
1288 if (r->is_Register()) return rc_int; | 1277 if (r->is_Register()) return rc_int; |
1289 assert(r->is_FloatRegister(), "must be"); | 1278 assert(r->is_FloatRegister(), "must be"); |
1290 return rc_float; | 1279 return rc_float; |
1291 } | 1280 } |
1292 | 1281 |
1293 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | 1282 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { |
1294 if (cbuf) { | 1283 if( cbuf ) { |
1295 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | 1284 // Better yet would be some mechanism to handle variable-size matches correctly |
1285 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
1286 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
1287 } else { | |
1288 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
1289 } | |
1296 } | 1290 } |
1297 #ifndef PRODUCT | 1291 #ifndef PRODUCT |
1298 else if (!do_size) { | 1292 else if( !do_size ) { |
1299 if (size != 0) st->print("\n\t"); | 1293 if( size != 0 ) st->print("\n\t"); |
1300 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | 1294 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); |
1301 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | 1295 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); |
1302 } | 1296 } |
1303 #endif | 1297 #endif |
1304 return size+4; | 1298 return size+4; |
1305 } | 1299 } |
1306 | 1300 |
1851 // SPARC doesn't support misaligned vectors store/load. | 1845 // SPARC doesn't support misaligned vectors store/load. |
1852 const bool Matcher::misaligned_vectors_ok() { | 1846 const bool Matcher::misaligned_vectors_ok() { |
1853 return false; | 1847 return false; |
1854 } | 1848 } |
1855 | 1849 |
1856 // Current (2013) SPARC platforms need to read original key | |
1857 // to construct decryption expanded key | |
1858 const bool Matcher::pass_original_key_for_aes() { | |
1859 return true; | |
1860 } | |
1861 | |
1862 // USII supports fxtof through the whole range of number, USIII doesn't | 1850 // USII supports fxtof through the whole range of number, USIII doesn't |
1863 const bool Matcher::convL2FSupported(void) { | 1851 const bool Matcher::convL2FSupported(void) { |
1864 return VM_Version::has_fast_fxtof(); | 1852 return VM_Version::has_fast_fxtof(); |
1865 } | 1853 } |
1866 | 1854 |
1893 | 1881 |
1894 // CMOVF/CMOVD are expensive on T4 and on SPARC64. | 1882 // CMOVF/CMOVD are expensive on T4 and on SPARC64. |
1895 const int Matcher::float_cmove_cost() { | 1883 const int Matcher::float_cmove_cost() { |
1896 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; | 1884 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; |
1897 } | 1885 } |
1898 | |
1899 // Does the CPU require late expand (see block.cpp for description of late expand)? | |
1900 const bool Matcher::require_postalloc_expand = false; | |
1901 | 1886 |
1902 // Should the Matcher clone shifts on addressing modes, expecting them to | 1887 // Should the Matcher clone shifts on addressing modes, expecting them to |
1903 // be subsumed into complex addressing expressions or compute them into | 1888 // be subsumed into complex addressing expressions or compute them into |
1904 // registers? True for Intel but false for most RISCs | 1889 // registers? True for Intel but false for most RISCs |
1905 const bool Matcher::clone_shift_expressions = false; | 1890 const bool Matcher::clone_shift_expressions = false; |
2034 } | 2019 } |
2035 | 2020 |
2036 const RegMask Matcher::method_handle_invoke_SP_save_mask() { | 2021 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
2037 return L7_REGP_mask(); | 2022 return L7_REGP_mask(); |
2038 } | 2023 } |
2024 | |
2025 const RegMask Matcher::mathExactI_result_proj_mask() { | |
2026 return G1_REGI_mask(); | |
2027 } | |
2028 | |
2029 const RegMask Matcher::mathExactL_result_proj_mask() { | |
2030 return G1_REGL_mask(); | |
2031 } | |
2032 | |
2033 const RegMask Matcher::mathExactI_flags_proj_mask() { | |
2034 return INT_FLAGS_mask(); | |
2035 } | |
2036 | |
2039 | 2037 |
2040 %} | 2038 %} |
2041 | 2039 |
2042 | 2040 |
2043 // The intptr_t operand types, defined by textual substitution. | 2041 // The intptr_t operand types, defined by textual substitution. |
2087 __ untested("encoding"); | 2085 __ untested("encoding"); |
2088 #endif | 2086 #endif |
2089 %} | 2087 %} |
2090 | 2088 |
2091 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | 2089 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ |
2092 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary, | 2090 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, |
2093 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | 2091 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
2094 %} | 2092 %} |
2095 | 2093 |
2096 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ | 2094 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
2097 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, | 2095 emit_form3_mem_reg(cbuf, this, $primary, -1, |
2098 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | 2096 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
2099 %} | 2097 %} |
2100 | 2098 |
2101 enc_class form3_mem_prefetch_read( memory mem ) %{ | 2099 enc_class form3_mem_prefetch_read( memory mem ) %{ |
2102 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, | 2100 emit_form3_mem_reg(cbuf, this, $primary, -1, |
2103 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); | 2101 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
2104 %} | 2102 %} |
2105 | 2103 |
2106 enc_class form3_mem_prefetch_write( memory mem ) %{ | 2104 enc_class form3_mem_prefetch_write( memory mem ) %{ |
2107 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, | 2105 emit_form3_mem_reg(cbuf, this, $primary, -1, |
2108 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); | 2106 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
2109 %} | 2107 %} |
2110 | 2108 |
2111 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | 2109 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ |
2112 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); | 2110 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
2113 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); | 2111 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
2114 guarantee($mem$$index == R_G0_enc, "double index?"); | 2112 guarantee($mem$$index == R_G0_enc, "double index?"); |
2115 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); | 2113 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
2116 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); | 2114 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
2117 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); | 2115 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
2118 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | 2116 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); |
2119 %} | 2117 %} |
2120 | 2118 |
2121 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | 2119 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ |
2122 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); | 2120 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
2123 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); | 2121 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
2124 guarantee($mem$$index == R_G0_enc, "double index?"); | 2122 guarantee($mem$$index == R_G0_enc, "double index?"); |
2125 // Load long with 2 instructions | 2123 // Load long with 2 instructions |
2126 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); | 2124 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
2127 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); | 2125 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
2128 %} | 2126 %} |
2129 | 2127 |
2130 //%%% form3_mem_plus_4_reg is a hack--get rid of it | 2128 //%%% form3_mem_plus_4_reg is a hack--get rid of it |
2131 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | 2129 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ |
2132 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | 2130 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); |
2133 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); | 2131 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
2134 %} | 2132 %} |
2135 | 2133 |
2136 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | 2134 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ |
2137 // Encode a reg-reg copy. If it is useless, then empty encoding. | 2135 // Encode a reg-reg copy. If it is useless, then empty encoding. |
2138 if( $rs2$$reg != $rd$$reg ) | 2136 if( $rs2$$reg != $rd$$reg ) |
3241 // Body of function which returns an OptoRegs array locating | 3239 // Body of function which returns an OptoRegs array locating |
3242 // arguments either in registers or in stack slots for callin | 3240 // arguments either in registers or in stack slots for callin |
3243 // C. | 3241 // C. |
3244 c_calling_convention %{ | 3242 c_calling_convention %{ |
3245 // This is obviously always outgoing | 3243 // This is obviously always outgoing |
3246 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); | 3244 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); |
3247 %} | 3245 %} |
3248 | 3246 |
3249 // Location of native (C/C++) and interpreter return values. This is specified to | 3247 // Location of native (C/C++) and interpreter return values. This is specified to |
3250 // be the same as Java. In the 32-bit VM, long values are actually returned from | 3248 // be the same as Java. In the 32-bit VM, long values are actually returned from |
3251 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | 3249 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying |
3354 op_cost(0); | 3352 op_cost(0); |
3355 format %{ %} | 3353 format %{ %} |
3356 interface(CONST_INTER); | 3354 interface(CONST_INTER); |
3357 %} | 3355 %} |
3358 | 3356 |
3359 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13) | 3357 // Unsigned (positive) Integer Immediate: 13-bit |
3360 operand immU12() %{ | 3358 operand immU13() %{ |
3361 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | 3359 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); |
3362 match(ConI); | 3360 match(ConI); |
3363 op_cost(0); | 3361 op_cost(0); |
3364 | 3362 |
3365 format %{ %} | 3363 format %{ %} |
3386 | 3384 |
3387 // Integer Immediate: 5-bit | 3385 // Integer Immediate: 5-bit |
3388 operand immI5() %{ | 3386 operand immI5() %{ |
3389 predicate(Assembler::is_simm5(n->get_int())); | 3387 predicate(Assembler::is_simm5(n->get_int())); |
3390 match(ConI); | 3388 match(ConI); |
3391 op_cost(0); | |
3392 format %{ %} | |
3393 interface(CONST_INTER); | |
3394 %} | |
3395 | |
3396 // Int Immediate non-negative | |
3397 operand immU31() | |
3398 %{ | |
3399 predicate(n->get_int() >= 0); | |
3400 match(ConI); | |
3401 | |
3402 op_cost(0); | 3389 op_cost(0); |
3403 format %{ %} | 3390 format %{ %} |
3404 interface(CONST_INTER); | 3391 interface(CONST_INTER); |
3405 %} | 3392 %} |
3406 | 3393 |
5730 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | 5717 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ |
5731 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | 5718 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); |
5732 effect(TEMP dst, TEMP tmp); | 5719 effect(TEMP dst, TEMP tmp); |
5733 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | 5720 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); |
5734 | 5721 |
5722 size((3+1)*4); // set may use two instructions. | |
5735 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" | 5723 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
5736 "SET $mask,$tmp\n\t" | 5724 "SET $mask,$tmp\n\t" |
5737 "AND $dst,$tmp,$dst" %} | 5725 "AND $dst,$tmp,$dst" %} |
5738 ins_encode %{ | 5726 ins_encode %{ |
5739 Register Rdst = $dst$$Register; | 5727 Register Rdst = $dst$$Register; |
5851 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | 5839 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE |
5852 %} | 5840 %} |
5853 ins_pipe(iload_mem); | 5841 ins_pipe(iload_mem); |
5854 %} | 5842 %} |
5855 | 5843 |
5856 // Load Integer with a 12-bit mask into a Long Register | 5844 // Load Integer with a 13-bit mask into a Long Register |
5857 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{ | 5845 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ |
5858 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | 5846 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
5859 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | 5847 ins_cost(MEMORY_REF_COST + DEFAULT_COST); |
5860 | 5848 |
5861 size(2*4); | 5849 size(2*4); |
5862 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t" | 5850 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" |
5863 "AND $dst,$mask,$dst" %} | 5851 "AND $dst,$mask,$dst" %} |
5864 ins_encode %{ | 5852 ins_encode %{ |
5865 Register Rdst = $dst$$Register; | 5853 Register Rdst = $dst$$Register; |
5866 __ lduw($mem$$Address, Rdst); | 5854 __ lduw($mem$$Address, Rdst); |
5867 __ and3(Rdst, $mask$$constant, Rdst); | 5855 __ and3(Rdst, $mask$$constant, Rdst); |
5868 %} | 5856 %} |
5869 ins_pipe(iload_mem); | 5857 ins_pipe(iload_mem); |
5870 %} | 5858 %} |
5871 | 5859 |
5872 // Load Integer with a 31-bit mask into a Long Register | 5860 // Load Integer with a 32-bit mask into a Long Register |
5873 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{ | 5861 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ |
5874 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | 5862 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
5875 effect(TEMP dst, TEMP tmp); | 5863 effect(TEMP dst, TEMP tmp); |
5876 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | 5864 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); |
5877 | 5865 |
5878 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t" | 5866 size((3+1)*4); // set may use two instructions. |
5867 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" | |
5879 "SET $mask,$tmp\n\t" | 5868 "SET $mask,$tmp\n\t" |
5880 "AND $dst,$tmp,$dst" %} | 5869 "AND $dst,$tmp,$dst" %} |
5881 ins_encode %{ | 5870 ins_encode %{ |
5882 Register Rdst = $dst$$Register; | 5871 Register Rdst = $dst$$Register; |
5883 Register Rtmp = $tmp$$Register; | 5872 Register Rtmp = $tmp$$Register; |
6652 //----------MemBar Instructions----------------------------------------------- | 6641 //----------MemBar Instructions----------------------------------------------- |
6653 // Memory barrier flavors | 6642 // Memory barrier flavors |
6654 | 6643 |
6655 instruct membar_acquire() %{ | 6644 instruct membar_acquire() %{ |
6656 match(MemBarAcquire); | 6645 match(MemBarAcquire); |
6657 match(LoadFence); | |
6658 ins_cost(4*MEMORY_REF_COST); | 6646 ins_cost(4*MEMORY_REF_COST); |
6659 | 6647 |
6660 size(0); | 6648 size(0); |
6661 format %{ "MEMBAR-acquire" %} | 6649 format %{ "MEMBAR-acquire" %} |
6662 ins_encode( enc_membar_acquire ); | 6650 ins_encode( enc_membar_acquire ); |
6673 ins_pipe(empty); | 6661 ins_pipe(empty); |
6674 %} | 6662 %} |
6675 | 6663 |
6676 instruct membar_release() %{ | 6664 instruct membar_release() %{ |
6677 match(MemBarRelease); | 6665 match(MemBarRelease); |
6678 match(StoreFence); | |
6679 ins_cost(4*MEMORY_REF_COST); | 6666 ins_cost(4*MEMORY_REF_COST); |
6680 | 6667 |
6681 size(0); | 6668 size(0); |
6682 format %{ "MEMBAR-release" %} | 6669 format %{ "MEMBAR-release" %} |
6683 ins_encode( enc_membar_release ); | 6670 ins_encode( enc_membar_release ); |
8970 opcode(Assembler::andcc_op3, Assembler::arith_op); | 8957 opcode(Assembler::andcc_op3, Assembler::arith_op); |
8971 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | 8958 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); |
8972 ins_pipe(ialu_cconly_reg_reg); | 8959 ins_pipe(ialu_cconly_reg_reg); |
8973 %} | 8960 %} |
8974 | 8961 |
8975 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{ | 8962 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ |
8976 match(Set icc (CmpU op1 op2)); | 8963 match(Set icc (CmpU op1 op2)); |
8977 | 8964 |
8978 size(4); | 8965 size(4); |
8979 format %{ "CMP $op1,$op2\t! unsigned" %} | 8966 format %{ "CMP $op1,$op2\t! unsigned" %} |
8980 opcode(Assembler::subcc_op3, Assembler::arith_op); | 8967 opcode(Assembler::subcc_op3, Assembler::arith_op); |
9175 effect(USE labl); | 9162 effect(USE labl); |
9176 | 9163 |
9177 size(4); | 9164 size(4); |
9178 ins_cost(BRANCH_COST); | 9165 ins_cost(BRANCH_COST); |
9179 format %{ "BA $labl\t! short branch" %} | 9166 format %{ "BA $labl\t! short branch" %} |
9180 ins_encode %{ | 9167 ins_encode %{ |
9181 Label* L = $labl$$label; | 9168 Label* L = $labl$$label; |
9182 assert(__ use_cbcond(*L), "back to back cbcond"); | 9169 assert(__ use_cbcond(*L), "back to back cbcond"); |
9183 __ ba_short(*L); | 9170 __ ba_short(*L); |
9184 %} | 9171 %} |
9185 ins_short_branch(1); | 9172 ins_short_branch(1); |