Mercurial > hg > truffle
comparison src/cpu/x86/vm/assembler_x86.cpp @ 7458:4daebd4cc1dd
Merge
author | minqi |
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date | Mon, 24 Dec 2012 11:46:38 -0800 |
parents | d02120b7a34f |
children | 00af3a3a8df4 |
comparison
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7457:35431a769282 | 7458:4daebd4cc1dd |
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224 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { | 224 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { |
225 assert(dst->has_byte_register(), "must have byte register"); | 225 assert(dst->has_byte_register(), "must have byte register"); |
226 assert(isByte(op1) && isByte(op2), "wrong opcode"); | 226 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
227 assert(isByte(imm8), "not a byte"); | 227 assert(isByte(imm8), "not a byte"); |
228 assert((op1 & 0x01) == 0, "should be 8bit operation"); | 228 assert((op1 & 0x01) == 0, "should be 8bit operation"); |
229 emit_byte(op1); | 229 emit_int8(op1); |
230 emit_byte(op2 | encode(dst)); | 230 emit_int8(op2 | encode(dst)); |
231 emit_byte(imm8); | 231 emit_int8(imm8); |
232 } | 232 } |
233 | 233 |
234 | 234 |
235 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { | 235 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
236 assert(isByte(op1) && isByte(op2), "wrong opcode"); | 236 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
237 assert((op1 & 0x01) == 1, "should be 32bit operation"); | 237 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
238 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | 238 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); |
239 if (is8bit(imm32)) { | 239 if (is8bit(imm32)) { |
240 emit_byte(op1 | 0x02); // set sign bit | 240 emit_int8(op1 | 0x02); // set sign bit |
241 emit_byte(op2 | encode(dst)); | 241 emit_int8(op2 | encode(dst)); |
242 emit_byte(imm32 & 0xFF); | 242 emit_int8(imm32 & 0xFF); |
243 } else { | 243 } else { |
244 emit_byte(op1); | 244 emit_int8(op1); |
245 emit_byte(op2 | encode(dst)); | 245 emit_int8(op2 | encode(dst)); |
246 emit_long(imm32); | 246 emit_long(imm32); |
247 } | 247 } |
248 } | 248 } |
249 | 249 |
250 // Force generation of a 4 byte immediate value even if it fits into 8bit | 250 // Force generation of a 4 byte immediate value even if it fits into 8bit |
251 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { | 251 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { |
252 assert(isByte(op1) && isByte(op2), "wrong opcode"); | 252 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
253 assert((op1 & 0x01) == 1, "should be 32bit operation"); | 253 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
254 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | 254 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); |
255 emit_byte(op1); | 255 emit_int8(op1); |
256 emit_byte(op2 | encode(dst)); | 256 emit_int8(op2 | encode(dst)); |
257 emit_long(imm32); | 257 emit_long(imm32); |
258 } | 258 } |
259 | 259 |
260 // immediate-to-memory forms | 260 // immediate-to-memory forms |
261 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { | 261 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
262 assert((op1 & 0x01) == 1, "should be 32bit operation"); | 262 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
263 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | 263 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); |
264 if (is8bit(imm32)) { | 264 if (is8bit(imm32)) { |
265 emit_byte(op1 | 0x02); // set sign bit | 265 emit_int8(op1 | 0x02); // set sign bit |
266 emit_operand(rm, adr, 1); | 266 emit_operand(rm, adr, 1); |
267 emit_byte(imm32 & 0xFF); | 267 emit_int8(imm32 & 0xFF); |
268 } else { | 268 } else { |
269 emit_byte(op1); | 269 emit_int8(op1); |
270 emit_operand(rm, adr, 4); | 270 emit_operand(rm, adr, 4); |
271 emit_long(imm32); | 271 emit_long(imm32); |
272 } | 272 } |
273 } | 273 } |
274 | 274 |
275 | 275 |
276 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | 276 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { |
277 assert(isByte(op1) && isByte(op2), "wrong opcode"); | 277 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
278 emit_byte(op1); | 278 emit_int8(op1); |
279 emit_byte(op2 | encode(dst) << 3 | encode(src)); | 279 emit_int8(op2 | encode(dst) << 3 | encode(src)); |
280 } | 280 } |
281 | 281 |
282 | 282 |
283 void Assembler::emit_operand(Register reg, Register base, Register index, | 283 void Assembler::emit_operand(Register reg, Register base, Register index, |
284 Address::ScaleFactor scale, int disp, | 284 Address::ScaleFactor scale, int disp, |
299 if (disp == 0 && rtype == relocInfo::none && | 299 if (disp == 0 && rtype == relocInfo::none && |
300 base != rbp LP64_ONLY(&& base != r13)) { | 300 base != rbp LP64_ONLY(&& base != r13)) { |
301 // [base + index*scale] | 301 // [base + index*scale] |
302 // [00 reg 100][ss index base] | 302 // [00 reg 100][ss index base] |
303 assert(index != rsp, "illegal addressing mode"); | 303 assert(index != rsp, "illegal addressing mode"); |
304 emit_byte(0x04 | regenc); | 304 emit_int8(0x04 | regenc); |
305 emit_byte(scale << 6 | indexenc | baseenc); | 305 emit_int8(scale << 6 | indexenc | baseenc); |
306 } else if (is8bit(disp) && rtype == relocInfo::none) { | 306 } else if (is8bit(disp) && rtype == relocInfo::none) { |
307 // [base + index*scale + imm8] | 307 // [base + index*scale + imm8] |
308 // [01 reg 100][ss index base] imm8 | 308 // [01 reg 100][ss index base] imm8 |
309 assert(index != rsp, "illegal addressing mode"); | 309 assert(index != rsp, "illegal addressing mode"); |
310 emit_byte(0x44 | regenc); | 310 emit_int8(0x44 | regenc); |
311 emit_byte(scale << 6 | indexenc | baseenc); | 311 emit_int8(scale << 6 | indexenc | baseenc); |
312 emit_byte(disp & 0xFF); | 312 emit_int8(disp & 0xFF); |
313 } else { | 313 } else { |
314 // [base + index*scale + disp32] | 314 // [base + index*scale + disp32] |
315 // [10 reg 100][ss index base] disp32 | 315 // [10 reg 100][ss index base] disp32 |
316 assert(index != rsp, "illegal addressing mode"); | 316 assert(index != rsp, "illegal addressing mode"); |
317 emit_byte(0x84 | regenc); | 317 emit_int8(0x84 | regenc); |
318 emit_byte(scale << 6 | indexenc | baseenc); | 318 emit_int8(scale << 6 | indexenc | baseenc); |
319 emit_data(disp, rspec, disp32_operand); | 319 emit_data(disp, rspec, disp32_operand); |
320 } | 320 } |
321 } else if (base == rsp LP64_ONLY(|| base == r12)) { | 321 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
322 // [rsp + disp] | 322 // [rsp + disp] |
323 if (disp == 0 && rtype == relocInfo::none) { | 323 if (disp == 0 && rtype == relocInfo::none) { |
324 // [rsp] | 324 // [rsp] |
325 // [00 reg 100][00 100 100] | 325 // [00 reg 100][00 100 100] |
326 emit_byte(0x04 | regenc); | 326 emit_int8(0x04 | regenc); |
327 emit_byte(0x24); | 327 emit_int8(0x24); |
328 } else if (is8bit(disp) && rtype == relocInfo::none) { | 328 } else if (is8bit(disp) && rtype == relocInfo::none) { |
329 // [rsp + imm8] | 329 // [rsp + imm8] |
330 // [01 reg 100][00 100 100] disp8 | 330 // [01 reg 100][00 100 100] disp8 |
331 emit_byte(0x44 | regenc); | 331 emit_int8(0x44 | regenc); |
332 emit_byte(0x24); | 332 emit_int8(0x24); |
333 emit_byte(disp & 0xFF); | 333 emit_int8(disp & 0xFF); |
334 } else { | 334 } else { |
335 // [rsp + imm32] | 335 // [rsp + imm32] |
336 // [10 reg 100][00 100 100] disp32 | 336 // [10 reg 100][00 100 100] disp32 |
337 emit_byte(0x84 | regenc); | 337 emit_int8(0x84 | regenc); |
338 emit_byte(0x24); | 338 emit_int8(0x24); |
339 emit_data(disp, rspec, disp32_operand); | 339 emit_data(disp, rspec, disp32_operand); |
340 } | 340 } |
341 } else { | 341 } else { |
342 // [base + disp] | 342 // [base + disp] |
343 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); | 343 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
344 if (disp == 0 && rtype == relocInfo::none && | 344 if (disp == 0 && rtype == relocInfo::none && |
345 base != rbp LP64_ONLY(&& base != r13)) { | 345 base != rbp LP64_ONLY(&& base != r13)) { |
346 // [base] | 346 // [base] |
347 // [00 reg base] | 347 // [00 reg base] |
348 emit_byte(0x00 | regenc | baseenc); | 348 emit_int8(0x00 | regenc | baseenc); |
349 } else if (is8bit(disp) && rtype == relocInfo::none) { | 349 } else if (is8bit(disp) && rtype == relocInfo::none) { |
350 // [base + disp8] | 350 // [base + disp8] |
351 // [01 reg base] disp8 | 351 // [01 reg base] disp8 |
352 emit_byte(0x40 | regenc | baseenc); | 352 emit_int8(0x40 | regenc | baseenc); |
353 emit_byte(disp & 0xFF); | 353 emit_int8(disp & 0xFF); |
354 } else { | 354 } else { |
355 // [base + disp32] | 355 // [base + disp32] |
356 // [10 reg base] disp32 | 356 // [10 reg base] disp32 |
357 emit_byte(0x80 | regenc | baseenc); | 357 emit_int8(0x80 | regenc | baseenc); |
358 emit_data(disp, rspec, disp32_operand); | 358 emit_data(disp, rspec, disp32_operand); |
359 } | 359 } |
360 } | 360 } |
361 } else { | 361 } else { |
362 if (index->is_valid()) { | 362 if (index->is_valid()) { |
363 assert(scale != Address::no_scale, "inconsistent address"); | 363 assert(scale != Address::no_scale, "inconsistent address"); |
364 // [index*scale + disp] | 364 // [index*scale + disp] |
365 // [00 reg 100][ss index 101] disp32 | 365 // [00 reg 100][ss index 101] disp32 |
366 assert(index != rsp, "illegal addressing mode"); | 366 assert(index != rsp, "illegal addressing mode"); |
367 emit_byte(0x04 | regenc); | 367 emit_int8(0x04 | regenc); |
368 emit_byte(scale << 6 | indexenc | 0x05); | 368 emit_int8(scale << 6 | indexenc | 0x05); |
369 emit_data(disp, rspec, disp32_operand); | 369 emit_data(disp, rspec, disp32_operand); |
370 } else if (rtype != relocInfo::none ) { | 370 } else if (rtype != relocInfo::none ) { |
371 // [disp] (64bit) RIP-RELATIVE (32bit) abs | 371 // [disp] (64bit) RIP-RELATIVE (32bit) abs |
372 // [00 000 101] disp32 | 372 // [00 000 101] disp32 |
373 | 373 |
374 emit_byte(0x05 | regenc); | 374 emit_int8(0x05 | regenc); |
375 // Note that the RIP-rel. correction applies to the generated | 375 // Note that the RIP-rel. correction applies to the generated |
376 // disp field, but _not_ to the target address in the rspec. | 376 // disp field, but _not_ to the target address in the rspec. |
377 | 377 |
378 // disp was created by converting the target address minus the pc | 378 // disp was created by converting the target address minus the pc |
379 // at the start of the instruction. That needs more correction here. | 379 // at the start of the instruction. That needs more correction here. |
389 | 389 |
390 } else { | 390 } else { |
391 // 32bit never did this, did everything as the rip-rel/disp code above | 391 // 32bit never did this, did everything as the rip-rel/disp code above |
392 // [disp] ABSOLUTE | 392 // [disp] ABSOLUTE |
393 // [00 reg 100][00 100 101] disp32 | 393 // [00 reg 100][00 100 101] disp32 |
394 emit_byte(0x04 | regenc); | 394 emit_int8(0x04 | regenc); |
395 emit_byte(0x25); | 395 emit_int8(0x25); |
396 emit_data(disp, rspec, disp32_operand); | 396 emit_data(disp, rspec, disp32_operand); |
397 } | 397 } |
398 } | 398 } |
399 } | 399 } |
400 | 400 |
881 | 881 |
882 | 882 |
883 void Assembler::emit_farith(int b1, int b2, int i) { | 883 void Assembler::emit_farith(int b1, int b2, int i) { |
884 assert(isByte(b1) && isByte(b2), "wrong opcode"); | 884 assert(isByte(b1) && isByte(b2), "wrong opcode"); |
885 assert(0 <= i && i < 8, "illegal stack offset"); | 885 assert(0 <= i && i < 8, "illegal stack offset"); |
886 emit_byte(b1); | 886 emit_int8(b1); |
887 emit_byte(b2 + i); | 887 emit_int8(b2 + i); |
888 } | 888 } |
889 | 889 |
890 | 890 |
891 // Now the Assembler instructions (identical for 32/64 bits) | 891 // Now the Assembler instructions (identical for 32/64 bits) |
892 | 892 |
897 } | 897 } |
898 | 898 |
899 void Assembler::adcl(Address dst, Register src) { | 899 void Assembler::adcl(Address dst, Register src) { |
900 InstructionMark im(this); | 900 InstructionMark im(this); |
901 prefix(dst, src); | 901 prefix(dst, src); |
902 emit_byte(0x11); | 902 emit_int8(0x11); |
903 emit_operand(src, dst); | 903 emit_operand(src, dst); |
904 } | 904 } |
905 | 905 |
906 void Assembler::adcl(Register dst, int32_t imm32) { | 906 void Assembler::adcl(Register dst, int32_t imm32) { |
907 prefix(dst); | 907 prefix(dst); |
909 } | 909 } |
910 | 910 |
911 void Assembler::adcl(Register dst, Address src) { | 911 void Assembler::adcl(Register dst, Address src) { |
912 InstructionMark im(this); | 912 InstructionMark im(this); |
913 prefix(src, dst); | 913 prefix(src, dst); |
914 emit_byte(0x13); | 914 emit_int8(0x13); |
915 emit_operand(dst, src); | 915 emit_operand(dst, src); |
916 } | 916 } |
917 | 917 |
918 void Assembler::adcl(Register dst, Register src) { | 918 void Assembler::adcl(Register dst, Register src) { |
919 (void) prefix_and_encode(dst->encoding(), src->encoding()); | 919 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
927 } | 927 } |
928 | 928 |
929 void Assembler::addl(Address dst, Register src) { | 929 void Assembler::addl(Address dst, Register src) { |
930 InstructionMark im(this); | 930 InstructionMark im(this); |
931 prefix(dst, src); | 931 prefix(dst, src); |
932 emit_byte(0x01); | 932 emit_int8(0x01); |
933 emit_operand(src, dst); | 933 emit_operand(src, dst); |
934 } | 934 } |
935 | 935 |
936 void Assembler::addl(Register dst, int32_t imm32) { | 936 void Assembler::addl(Register dst, int32_t imm32) { |
937 prefix(dst); | 937 prefix(dst); |
939 } | 939 } |
940 | 940 |
941 void Assembler::addl(Register dst, Address src) { | 941 void Assembler::addl(Register dst, Address src) { |
942 InstructionMark im(this); | 942 InstructionMark im(this); |
943 prefix(src, dst); | 943 prefix(src, dst); |
944 emit_byte(0x03); | 944 emit_int8(0x03); |
945 emit_operand(dst, src); | 945 emit_operand(dst, src); |
946 } | 946 } |
947 | 947 |
948 void Assembler::addl(Register dst, Register src) { | 948 void Assembler::addl(Register dst, Register src) { |
949 (void) prefix_and_encode(dst->encoding(), src->encoding()); | 949 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
951 } | 951 } |
952 | 952 |
953 void Assembler::addr_nop_4() { | 953 void Assembler::addr_nop_4() { |
954 assert(UseAddressNop, "no CPU support"); | 954 assert(UseAddressNop, "no CPU support"); |
955 // 4 bytes: NOP DWORD PTR [EAX+0] | 955 // 4 bytes: NOP DWORD PTR [EAX+0] |
956 emit_byte(0x0F); | 956 emit_int8(0x0F); |
957 emit_byte(0x1F); | 957 emit_int8(0x1F); |
958 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); | 958 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); |
959 emit_byte(0); // 8-bits offset (1 byte) | 959 emit_int8(0); // 8-bits offset (1 byte) |
960 } | 960 } |
961 | 961 |
962 void Assembler::addr_nop_5() { | 962 void Assembler::addr_nop_5() { |
963 assert(UseAddressNop, "no CPU support"); | 963 assert(UseAddressNop, "no CPU support"); |
964 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset | 964 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset |
965 emit_byte(0x0F); | 965 emit_int8(0x0F); |
966 emit_byte(0x1F); | 966 emit_int8(0x1F); |
967 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); | 967 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); |
968 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | 968 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); |
969 emit_byte(0); // 8-bits offset (1 byte) | 969 emit_int8(0); // 8-bits offset (1 byte) |
970 } | 970 } |
971 | 971 |
972 void Assembler::addr_nop_7() { | 972 void Assembler::addr_nop_7() { |
973 assert(UseAddressNop, "no CPU support"); | 973 assert(UseAddressNop, "no CPU support"); |
974 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset | 974 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset |
975 emit_byte(0x0F); | 975 emit_int8(0x0F); |
976 emit_byte(0x1F); | 976 emit_int8(0x1F); |
977 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); | 977 emit_int8((unsigned char)0x80); |
978 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); | |
978 emit_long(0); // 32-bits offset (4 bytes) | 979 emit_long(0); // 32-bits offset (4 bytes) |
979 } | 980 } |
980 | 981 |
981 void Assembler::addr_nop_8() { | 982 void Assembler::addr_nop_8() { |
982 assert(UseAddressNop, "no CPU support"); | 983 assert(UseAddressNop, "no CPU support"); |
983 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset | 984 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset |
984 emit_byte(0x0F); | 985 emit_int8(0x0F); |
985 emit_byte(0x1F); | 986 emit_int8(0x1F); |
986 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); | 987 emit_int8((unsigned char)0x84); |
987 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | 988 // emit_rm(cbuf, 0x2, EAX_enc, 0x4); |
989 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
988 emit_long(0); // 32-bits offset (4 bytes) | 990 emit_long(0); // 32-bits offset (4 bytes) |
989 } | 991 } |
990 | 992 |
991 void Assembler::addsd(XMMRegister dst, XMMRegister src) { | 993 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
992 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 994 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1010 | 1012 |
1011 void Assembler::aesdec(XMMRegister dst, Address src) { | 1013 void Assembler::aesdec(XMMRegister dst, Address src) { |
1012 assert(VM_Version::supports_aes(), ""); | 1014 assert(VM_Version::supports_aes(), ""); |
1013 InstructionMark im(this); | 1015 InstructionMark im(this); |
1014 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 1016 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
1015 emit_byte(0xde); | 1017 emit_int8((unsigned char)0xDE); |
1016 emit_operand(dst, src); | 1018 emit_operand(dst, src); |
1017 } | 1019 } |
1018 | 1020 |
1019 void Assembler::aesdec(XMMRegister dst, XMMRegister src) { | 1021 void Assembler::aesdec(XMMRegister dst, XMMRegister src) { |
1020 assert(VM_Version::supports_aes(), ""); | 1022 assert(VM_Version::supports_aes(), ""); |
1021 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 1023 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
1022 emit_byte(0xde); | 1024 emit_int8((unsigned char)0xDE); |
1023 emit_byte(0xC0 | encode); | 1025 emit_int8(0xC0 | encode); |
1024 } | 1026 } |
1025 | 1027 |
1026 void Assembler::aesdeclast(XMMRegister dst, Address src) { | 1028 void Assembler::aesdeclast(XMMRegister dst, Address src) { |
1027 assert(VM_Version::supports_aes(), ""); | 1029 assert(VM_Version::supports_aes(), ""); |
1028 InstructionMark im(this); | 1030 InstructionMark im(this); |
1029 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 1031 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
1030 emit_byte(0xdf); | 1032 emit_int8((unsigned char)0xDF); |
1031 emit_operand(dst, src); | 1033 emit_operand(dst, src); |
1032 } | 1034 } |
1033 | 1035 |
1034 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) { | 1036 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) { |
1035 assert(VM_Version::supports_aes(), ""); | 1037 assert(VM_Version::supports_aes(), ""); |
1036 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 1038 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
1037 emit_byte(0xdf); | 1039 emit_int8((unsigned char)0xDF); |
1038 emit_byte(0xC0 | encode); | 1040 emit_int8((unsigned char)(0xC0 | encode)); |
1039 } | 1041 } |
1040 | 1042 |
1041 void Assembler::aesenc(XMMRegister dst, Address src) { | 1043 void Assembler::aesenc(XMMRegister dst, Address src) { |
1042 assert(VM_Version::supports_aes(), ""); | 1044 assert(VM_Version::supports_aes(), ""); |
1043 InstructionMark im(this); | 1045 InstructionMark im(this); |
1044 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 1046 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
1045 emit_byte(0xdc); | 1047 emit_int8((unsigned char)0xDC); |
1046 emit_operand(dst, src); | 1048 emit_operand(dst, src); |
1047 } | 1049 } |
1048 | 1050 |
1049 void Assembler::aesenc(XMMRegister dst, XMMRegister src) { | 1051 void Assembler::aesenc(XMMRegister dst, XMMRegister src) { |
1050 assert(VM_Version::supports_aes(), ""); | 1052 assert(VM_Version::supports_aes(), ""); |
1051 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 1053 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
1052 emit_byte(0xdc); | 1054 emit_int8((unsigned char)0xDC); |
1053 emit_byte(0xC0 | encode); | 1055 emit_int8(0xC0 | encode); |
1054 } | 1056 } |
1055 | 1057 |
1056 void Assembler::aesenclast(XMMRegister dst, Address src) { | 1058 void Assembler::aesenclast(XMMRegister dst, Address src) { |
1057 assert(VM_Version::supports_aes(), ""); | 1059 assert(VM_Version::supports_aes(), ""); |
1058 InstructionMark im(this); | 1060 InstructionMark im(this); |
1059 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 1061 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
1060 emit_byte(0xdd); | 1062 emit_int8((unsigned char)0xDD); |
1061 emit_operand(dst, src); | 1063 emit_operand(dst, src); |
1062 } | 1064 } |
1063 | 1065 |
1064 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { | 1066 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { |
1065 assert(VM_Version::supports_aes(), ""); | 1067 assert(VM_Version::supports_aes(), ""); |
1066 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 1068 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
1067 emit_byte(0xdd); | 1069 emit_int8((unsigned char)0xDD); |
1068 emit_byte(0xC0 | encode); | 1070 emit_int8((unsigned char)(0xC0 | encode)); |
1069 } | 1071 } |
1070 | 1072 |
1071 | 1073 |
1072 void Assembler::andl(Address dst, int32_t imm32) { | 1074 void Assembler::andl(Address dst, int32_t imm32) { |
1073 InstructionMark im(this); | 1075 InstructionMark im(this); |
1074 prefix(dst); | 1076 prefix(dst); |
1075 emit_byte(0x81); | 1077 emit_int8((unsigned char)0x81); |
1076 emit_operand(rsp, dst, 4); | 1078 emit_operand(rsp, dst, 4); |
1077 emit_long(imm32); | 1079 emit_long(imm32); |
1078 } | 1080 } |
1079 | 1081 |
1080 void Assembler::andl(Register dst, int32_t imm32) { | 1082 void Assembler::andl(Register dst, int32_t imm32) { |
1083 } | 1085 } |
1084 | 1086 |
1085 void Assembler::andl(Register dst, Address src) { | 1087 void Assembler::andl(Register dst, Address src) { |
1086 InstructionMark im(this); | 1088 InstructionMark im(this); |
1087 prefix(src, dst); | 1089 prefix(src, dst); |
1088 emit_byte(0x23); | 1090 emit_int8(0x23); |
1089 emit_operand(dst, src); | 1091 emit_operand(dst, src); |
1090 } | 1092 } |
1091 | 1093 |
1092 void Assembler::andl(Register dst, Register src) { | 1094 void Assembler::andl(Register dst, Register src) { |
1093 (void) prefix_and_encode(dst->encoding(), src->encoding()); | 1095 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
1094 emit_arith(0x23, 0xC0, dst, src); | 1096 emit_arith(0x23, 0xC0, dst, src); |
1095 } | 1097 } |
1096 | 1098 |
1097 void Assembler::bsfl(Register dst, Register src) { | 1099 void Assembler::bsfl(Register dst, Register src) { |
1098 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 1100 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
1099 emit_byte(0x0F); | 1101 emit_int8(0x0F); |
1100 emit_byte(0xBC); | 1102 emit_int8((unsigned char)0xBC); |
1101 emit_byte(0xC0 | encode); | 1103 emit_int8((unsigned char)(0xC0 | encode)); |
1102 } | 1104 } |
1103 | 1105 |
1104 void Assembler::bsrl(Register dst, Register src) { | 1106 void Assembler::bsrl(Register dst, Register src) { |
1105 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); | 1107 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
1106 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 1108 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
1107 emit_byte(0x0F); | 1109 emit_int8(0x0F); |
1108 emit_byte(0xBD); | 1110 emit_int8((unsigned char)0xBD); |
1109 emit_byte(0xC0 | encode); | 1111 emit_int8((unsigned char)(0xC0 | encode)); |
1110 } | 1112 } |
1111 | 1113 |
1112 void Assembler::bswapl(Register reg) { // bswap | 1114 void Assembler::bswapl(Register reg) { // bswap |
1113 int encode = prefix_and_encode(reg->encoding()); | 1115 int encode = prefix_and_encode(reg->encoding()); |
1114 emit_byte(0x0F); | 1116 emit_int8(0x0F); |
1115 emit_byte(0xC8 | encode); | 1117 emit_int8((unsigned char)(0xC8 | encode)); |
1116 } | 1118 } |
1117 | 1119 |
1118 void Assembler::call(Label& L, relocInfo::relocType rtype) { | 1120 void Assembler::call(Label& L, relocInfo::relocType rtype) { |
1119 // suspect disp32 is always good | 1121 // suspect disp32 is always good |
1120 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | 1122 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); |
1123 const int long_size = 5; | 1125 const int long_size = 5; |
1124 int offs = (int)( target(L) - pc() ); | 1126 int offs = (int)( target(L) - pc() ); |
1125 assert(offs <= 0, "assembler error"); | 1127 assert(offs <= 0, "assembler error"); |
1126 InstructionMark im(this); | 1128 InstructionMark im(this); |
1127 // 1110 1000 #32-bit disp | 1129 // 1110 1000 #32-bit disp |
1128 emit_byte(0xE8); | 1130 emit_int8((unsigned char)0xE8); |
1129 emit_data(offs - long_size, rtype, operand); | 1131 emit_data(offs - long_size, rtype, operand); |
1130 } else { | 1132 } else { |
1131 InstructionMark im(this); | 1133 InstructionMark im(this); |
1132 // 1110 1000 #32-bit disp | 1134 // 1110 1000 #32-bit disp |
1133 L.add_patch_at(code(), locator()); | 1135 L.add_patch_at(code(), locator()); |
1134 | 1136 |
1135 emit_byte(0xE8); | 1137 emit_int8((unsigned char)0xE8); |
1136 emit_data(int(0), rtype, operand); | 1138 emit_data(int(0), rtype, operand); |
1137 } | 1139 } |
1138 } | 1140 } |
1139 | 1141 |
1140 void Assembler::call(Register dst) { | 1142 void Assembler::call(Register dst) { |
1141 int encode = prefix_and_encode(dst->encoding()); | 1143 int encode = prefix_and_encode(dst->encoding()); |
1142 emit_byte(0xFF); | 1144 emit_int8((unsigned char)0xFF); |
1143 emit_byte(0xD0 | encode); | 1145 emit_int8((unsigned char)(0xD0 | encode)); |
1144 } | 1146 } |
1145 | 1147 |
1146 | 1148 |
1147 void Assembler::call(Address adr) { | 1149 void Assembler::call(Address adr) { |
1148 InstructionMark im(this); | 1150 InstructionMark im(this); |
1149 prefix(adr); | 1151 prefix(adr); |
1150 emit_byte(0xFF); | 1152 emit_int8((unsigned char)0xFF); |
1151 emit_operand(rdx, adr); | 1153 emit_operand(rdx, adr); |
1152 } | 1154 } |
1153 | 1155 |
1154 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | 1156 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { |
1155 assert(entry != NULL, "call most probably wrong"); | 1157 assert(entry != NULL, "call most probably wrong"); |
1156 InstructionMark im(this); | 1158 InstructionMark im(this); |
1157 emit_byte(0xE8); | 1159 emit_int8((unsigned char)0xE8); |
1158 intptr_t disp = entry - (pc() + sizeof(int32_t)); | 1160 intptr_t disp = entry - (pc() + sizeof(int32_t)); |
1159 assert(is_simm32(disp), "must be 32bit offset (call2)"); | 1161 assert(is_simm32(disp), "must be 32bit offset (call2)"); |
1160 // Technically, should use call32_operand, but this format is | 1162 // Technically, should use call32_operand, but this format is |
1161 // implied by the fact that we're emitting a call instruction. | 1163 // implied by the fact that we're emitting a call instruction. |
1162 | 1164 |
1163 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | 1165 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); |
1164 emit_data((int) disp, rspec, operand); | 1166 emit_data((int) disp, rspec, operand); |
1165 } | 1167 } |
1166 | 1168 |
1167 void Assembler::cdql() { | 1169 void Assembler::cdql() { |
1168 emit_byte(0x99); | 1170 emit_int8((unsigned char)0x99); |
1169 } | 1171 } |
1170 | 1172 |
1171 void Assembler::cld() { | 1173 void Assembler::cld() { |
1172 emit_byte(0xfc); | 1174 emit_int8((unsigned char)0xFC); |
1173 } | 1175 } |
1174 | 1176 |
1175 void Assembler::cmovl(Condition cc, Register dst, Register src) { | 1177 void Assembler::cmovl(Condition cc, Register dst, Register src) { |
1176 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | 1178 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); |
1177 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 1179 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
1178 emit_byte(0x0F); | 1180 emit_int8(0x0F); |
1179 emit_byte(0x40 | cc); | 1181 emit_int8(0x40 | cc); |
1180 emit_byte(0xC0 | encode); | 1182 emit_int8((unsigned char)(0xC0 | encode)); |
1181 } | 1183 } |
1182 | 1184 |
1183 | 1185 |
1184 void Assembler::cmovl(Condition cc, Register dst, Address src) { | 1186 void Assembler::cmovl(Condition cc, Register dst, Address src) { |
1185 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | 1187 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); |
1186 prefix(src, dst); | 1188 prefix(src, dst); |
1187 emit_byte(0x0F); | 1189 emit_int8(0x0F); |
1188 emit_byte(0x40 | cc); | 1190 emit_int8(0x40 | cc); |
1189 emit_operand(dst, src); | 1191 emit_operand(dst, src); |
1190 } | 1192 } |
1191 | 1193 |
1192 void Assembler::cmpb(Address dst, int imm8) { | 1194 void Assembler::cmpb(Address dst, int imm8) { |
1193 InstructionMark im(this); | 1195 InstructionMark im(this); |
1194 prefix(dst); | 1196 prefix(dst); |
1195 emit_byte(0x80); | 1197 emit_int8((unsigned char)0x80); |
1196 emit_operand(rdi, dst, 1); | 1198 emit_operand(rdi, dst, 1); |
1197 emit_byte(imm8); | 1199 emit_int8(imm8); |
1198 } | 1200 } |
1199 | 1201 |
1200 void Assembler::cmpl(Address dst, int32_t imm32) { | 1202 void Assembler::cmpl(Address dst, int32_t imm32) { |
1201 InstructionMark im(this); | 1203 InstructionMark im(this); |
1202 prefix(dst); | 1204 prefix(dst); |
1203 emit_byte(0x81); | 1205 emit_int8((unsigned char)0x81); |
1204 emit_operand(rdi, dst, 4); | 1206 emit_operand(rdi, dst, 4); |
1205 emit_long(imm32); | 1207 emit_long(imm32); |
1206 } | 1208 } |
1207 | 1209 |
1208 void Assembler::cmpl(Register dst, int32_t imm32) { | 1210 void Assembler::cmpl(Register dst, int32_t imm32) { |
1217 | 1219 |
1218 | 1220 |
1219 void Assembler::cmpl(Register dst, Address src) { | 1221 void Assembler::cmpl(Register dst, Address src) { |
1220 InstructionMark im(this); | 1222 InstructionMark im(this); |
1221 prefix(src, dst); | 1223 prefix(src, dst); |
1222 emit_byte(0x3B); | 1224 emit_int8((unsigned char)0x3B); |
1223 emit_operand(dst, src); | 1225 emit_operand(dst, src); |
1224 } | 1226 } |
1225 | 1227 |
1226 void Assembler::cmpw(Address dst, int imm16) { | 1228 void Assembler::cmpw(Address dst, int imm16) { |
1227 InstructionMark im(this); | 1229 InstructionMark im(this); |
1228 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | 1230 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); |
1229 emit_byte(0x66); | 1231 emit_int8(0x66); |
1230 emit_byte(0x81); | 1232 emit_int8((unsigned char)0x81); |
1231 emit_operand(rdi, dst, 2); | 1233 emit_operand(rdi, dst, 2); |
1232 emit_word(imm16); | 1234 emit_int16(imm16); |
1233 } | 1235 } |
1234 | 1236 |
1235 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | 1237 // The 32-bit cmpxchg compares the value at adr with the contents of rax, |
1236 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | 1238 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. |
1237 // The ZF is set if the compared values were equal, and cleared otherwise. | 1239 // The ZF is set if the compared values were equal, and cleared otherwise. |
1238 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | 1240 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg |
1239 InstructionMark im(this); | 1241 InstructionMark im(this); |
1240 prefix(adr, reg); | 1242 prefix(adr, reg); |
1241 emit_byte(0x0F); | 1243 emit_int8(0x0F); |
1242 emit_byte(0xB1); | 1244 emit_int8((unsigned char)0xB1); |
1243 emit_operand(reg, adr); | 1245 emit_operand(reg, adr); |
1244 } | 1246 } |
1245 | 1247 |
1246 void Assembler::comisd(XMMRegister dst, Address src) { | 1248 void Assembler::comisd(XMMRegister dst, Address src) { |
1247 // NOTE: dbx seems to decode this as comiss even though the | 1249 // NOTE: dbx seems to decode this as comiss even though the |
1264 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1266 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1265 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); | 1267 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); |
1266 } | 1268 } |
1267 | 1269 |
1268 void Assembler::cpuid() { | 1270 void Assembler::cpuid() { |
1269 emit_byte(0x0F); | 1271 emit_int8(0x0F); |
1270 emit_byte(0xA2); | 1272 emit_int8((unsigned char)0xA2); |
1271 } | 1273 } |
1272 | 1274 |
1273 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { | 1275 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { |
1274 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1276 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1275 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3); | 1277 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3); |
1291 } | 1293 } |
1292 | 1294 |
1293 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { | 1295 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { |
1294 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1296 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1295 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); | 1297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1296 emit_byte(0x2A); | 1298 emit_int8(0x2A); |
1297 emit_byte(0xC0 | encode); | 1299 emit_int8((unsigned char)(0xC0 | encode)); |
1298 } | 1300 } |
1299 | 1301 |
1300 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { | 1302 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { |
1301 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1303 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1302 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2); | 1304 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2); |
1303 } | 1305 } |
1304 | 1306 |
1305 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { | 1307 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { |
1306 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1308 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1307 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); | 1309 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1308 emit_byte(0x2A); | 1310 emit_int8(0x2A); |
1309 emit_byte(0xC0 | encode); | 1311 emit_int8((unsigned char)(0xC0 | encode)); |
1310 } | 1312 } |
1311 | 1313 |
1312 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { | 1314 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { |
1313 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1315 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1314 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3); | 1316 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3); |
1326 | 1328 |
1327 | 1329 |
1328 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { | 1330 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { |
1329 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1331 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1330 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); | 1332 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
1331 emit_byte(0x2C); | 1333 emit_int8(0x2C); |
1332 emit_byte(0xC0 | encode); | 1334 emit_int8((unsigned char)(0xC0 | encode)); |
1333 } | 1335 } |
1334 | 1336 |
1335 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | 1337 void Assembler::cvttss2sil(Register dst, XMMRegister src) { |
1336 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1338 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1337 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); | 1339 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
1338 emit_byte(0x2C); | 1340 emit_int8(0x2C); |
1339 emit_byte(0xC0 | encode); | 1341 emit_int8((unsigned char)(0xC0 | encode)); |
1340 } | 1342 } |
1341 | 1343 |
1342 void Assembler::decl(Address dst) { | 1344 void Assembler::decl(Address dst) { |
1343 // Don't use it directly. Use MacroAssembler::decrement() instead. | 1345 // Don't use it directly. Use MacroAssembler::decrement() instead. |
1344 InstructionMark im(this); | 1346 InstructionMark im(this); |
1345 prefix(dst); | 1347 prefix(dst); |
1346 emit_byte(0xFF); | 1348 emit_int8((unsigned char)0xFF); |
1347 emit_operand(rcx, dst); | 1349 emit_operand(rcx, dst); |
1348 } | 1350 } |
1349 | 1351 |
1350 void Assembler::divsd(XMMRegister dst, Address src) { | 1352 void Assembler::divsd(XMMRegister dst, Address src) { |
1351 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1353 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1367 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); | 1369 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); |
1368 } | 1370 } |
1369 | 1371 |
1370 void Assembler::emms() { | 1372 void Assembler::emms() { |
1371 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | 1373 NOT_LP64(assert(VM_Version::supports_mmx(), "")); |
1372 emit_byte(0x0F); | 1374 emit_int8(0x0F); |
1373 emit_byte(0x77); | 1375 emit_int8(0x77); |
1374 } | 1376 } |
1375 | 1377 |
1376 void Assembler::hlt() { | 1378 void Assembler::hlt() { |
1377 emit_byte(0xF4); | 1379 emit_int8((unsigned char)0xF4); |
1378 } | 1380 } |
1379 | 1381 |
1380 void Assembler::idivl(Register src) { | 1382 void Assembler::idivl(Register src) { |
1381 int encode = prefix_and_encode(src->encoding()); | 1383 int encode = prefix_and_encode(src->encoding()); |
1382 emit_byte(0xF7); | 1384 emit_int8((unsigned char)0xF7); |
1383 emit_byte(0xF8 | encode); | 1385 emit_int8((unsigned char)(0xF8 | encode)); |
1384 } | 1386 } |
1385 | 1387 |
1386 void Assembler::divl(Register src) { // Unsigned | 1388 void Assembler::divl(Register src) { // Unsigned |
1387 int encode = prefix_and_encode(src->encoding()); | 1389 int encode = prefix_and_encode(src->encoding()); |
1388 emit_byte(0xF7); | 1390 emit_int8((unsigned char)0xF7); |
1389 emit_byte(0xF0 | encode); | 1391 emit_int8((unsigned char)(0xF0 | encode)); |
1390 } | 1392 } |
1391 | 1393 |
1392 void Assembler::imull(Register dst, Register src) { | 1394 void Assembler::imull(Register dst, Register src) { |
1393 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 1395 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
1394 emit_byte(0x0F); | 1396 emit_int8(0x0F); |
1395 emit_byte(0xAF); | 1397 emit_int8((unsigned char)0xAF); |
1396 emit_byte(0xC0 | encode); | 1398 emit_int8((unsigned char)(0xC0 | encode)); |
1397 } | 1399 } |
1398 | 1400 |
1399 | 1401 |
1400 void Assembler::imull(Register dst, Register src, int value) { | 1402 void Assembler::imull(Register dst, Register src, int value) { |
1401 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 1403 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
1402 if (is8bit(value)) { | 1404 if (is8bit(value)) { |
1403 emit_byte(0x6B); | 1405 emit_int8(0x6B); |
1404 emit_byte(0xC0 | encode); | 1406 emit_int8((unsigned char)(0xC0 | encode)); |
1405 emit_byte(value & 0xFF); | 1407 emit_int8(value & 0xFF); |
1406 } else { | 1408 } else { |
1407 emit_byte(0x69); | 1409 emit_int8(0x69); |
1408 emit_byte(0xC0 | encode); | 1410 emit_int8((unsigned char)(0xC0 | encode)); |
1409 emit_long(value); | 1411 emit_long(value); |
1410 } | 1412 } |
1411 } | 1413 } |
1412 | 1414 |
1413 void Assembler::incl(Address dst) { | 1415 void Assembler::incl(Address dst) { |
1414 // Don't use it directly. Use MacroAssembler::increment() instead. | 1416 // Don't use it directly. Use MacroAssembler::increment() instead. |
1415 InstructionMark im(this); | 1417 InstructionMark im(this); |
1416 prefix(dst); | 1418 prefix(dst); |
1417 emit_byte(0xFF); | 1419 emit_int8((unsigned char)0xFF); |
1418 emit_operand(rax, dst); | 1420 emit_operand(rax, dst); |
1419 } | 1421 } |
1420 | 1422 |
1421 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { | 1423 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { |
1422 InstructionMark im(this); | 1424 InstructionMark im(this); |
1428 const int short_size = 2; | 1430 const int short_size = 2; |
1429 const int long_size = 6; | 1431 const int long_size = 6; |
1430 intptr_t offs = (intptr_t)dst - (intptr_t)pc(); | 1432 intptr_t offs = (intptr_t)dst - (intptr_t)pc(); |
1431 if (maybe_short && is8bit(offs - short_size)) { | 1433 if (maybe_short && is8bit(offs - short_size)) { |
1432 // 0111 tttn #8-bit disp | 1434 // 0111 tttn #8-bit disp |
1433 emit_byte(0x70 | cc); | 1435 emit_int8(0x70 | cc); |
1434 emit_byte((offs - short_size) & 0xFF); | 1436 emit_int8((offs - short_size) & 0xFF); |
1435 } else { | 1437 } else { |
1436 // 0000 1111 1000 tttn #32-bit disp | 1438 // 0000 1111 1000 tttn #32-bit disp |
1437 assert(is_simm32(offs - long_size), | 1439 assert(is_simm32(offs - long_size), |
1438 "must be 32bit offset (call4)"); | 1440 "must be 32bit offset (call4)"); |
1439 emit_byte(0x0F); | 1441 emit_int8(0x0F); |
1440 emit_byte(0x80 | cc); | 1442 emit_int8((unsigned char)(0x80 | cc)); |
1441 emit_long(offs - long_size); | 1443 emit_long(offs - long_size); |
1442 } | 1444 } |
1443 } else { | 1445 } else { |
1444 // Note: could eliminate cond. jumps to this jump if condition | 1446 // Note: could eliminate cond. jumps to this jump if condition |
1445 // is the same however, seems to be rather unlikely case. | 1447 // is the same however, seems to be rather unlikely case. |
1446 // Note: use jccb() if label to be bound is very close to get | 1448 // Note: use jccb() if label to be bound is very close to get |
1447 // an 8-bit displacement | 1449 // an 8-bit displacement |
1448 L.add_patch_at(code(), locator()); | 1450 L.add_patch_at(code(), locator()); |
1449 emit_byte(0x0F); | 1451 emit_int8(0x0F); |
1450 emit_byte(0x80 | cc); | 1452 emit_int8((unsigned char)(0x80 | cc)); |
1451 emit_long(0); | 1453 emit_long(0); |
1452 } | 1454 } |
1453 } | 1455 } |
1454 | 1456 |
1455 void Assembler::jccb(Condition cc, Label& L) { | 1457 void Assembler::jccb(Condition cc, Label& L) { |
1464 } | 1466 } |
1465 assert(is8bit(dist), "Dispacement too large for a short jmp"); | 1467 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
1466 #endif | 1468 #endif |
1467 intptr_t offs = (intptr_t)entry - (intptr_t)pc(); | 1469 intptr_t offs = (intptr_t)entry - (intptr_t)pc(); |
1468 // 0111 tttn #8-bit disp | 1470 // 0111 tttn #8-bit disp |
1469 emit_byte(0x70 | cc); | 1471 emit_int8(0x70 | cc); |
1470 emit_byte((offs - short_size) & 0xFF); | 1472 emit_int8((offs - short_size) & 0xFF); |
1471 } else { | 1473 } else { |
1472 InstructionMark im(this); | 1474 InstructionMark im(this); |
1473 L.add_patch_at(code(), locator()); | 1475 L.add_patch_at(code(), locator()); |
1474 emit_byte(0x70 | cc); | 1476 emit_int8(0x70 | cc); |
1475 emit_byte(0); | 1477 emit_int8(0); |
1476 } | 1478 } |
1477 } | 1479 } |
1478 | 1480 |
1479 void Assembler::jmp(Address adr) { | 1481 void Assembler::jmp(Address adr) { |
1480 InstructionMark im(this); | 1482 InstructionMark im(this); |
1481 prefix(adr); | 1483 prefix(adr); |
1482 emit_byte(0xFF); | 1484 emit_int8((unsigned char)0xFF); |
1483 emit_operand(rsp, adr); | 1485 emit_operand(rsp, adr); |
1484 } | 1486 } |
1485 | 1487 |
1486 void Assembler::jmp(Label& L, bool maybe_short) { | 1488 void Assembler::jmp(Label& L, bool maybe_short) { |
1487 if (L.is_bound()) { | 1489 if (L.is_bound()) { |
1490 InstructionMark im(this); | 1492 InstructionMark im(this); |
1491 const int short_size = 2; | 1493 const int short_size = 2; |
1492 const int long_size = 5; | 1494 const int long_size = 5; |
1493 intptr_t offs = entry - pc(); | 1495 intptr_t offs = entry - pc(); |
1494 if (maybe_short && is8bit(offs - short_size)) { | 1496 if (maybe_short && is8bit(offs - short_size)) { |
1495 emit_byte(0xEB); | 1497 emit_int8((unsigned char)0xEB); |
1496 emit_byte((offs - short_size) & 0xFF); | 1498 emit_int8((offs - short_size) & 0xFF); |
1497 } else { | 1499 } else { |
1498 emit_byte(0xE9); | 1500 emit_int8((unsigned char)0xE9); |
1499 emit_long(offs - long_size); | 1501 emit_long(offs - long_size); |
1500 } | 1502 } |
1501 } else { | 1503 } else { |
1502 // By default, forward jumps are always 32-bit displacements, since | 1504 // By default, forward jumps are always 32-bit displacements, since |
1503 // we can't yet know where the label will be bound. If you're sure that | 1505 // we can't yet know where the label will be bound. If you're sure that |
1504 // the forward jump will not run beyond 256 bytes, use jmpb to | 1506 // the forward jump will not run beyond 256 bytes, use jmpb to |
1505 // force an 8-bit displacement. | 1507 // force an 8-bit displacement. |
1506 InstructionMark im(this); | 1508 InstructionMark im(this); |
1507 L.add_patch_at(code(), locator()); | 1509 L.add_patch_at(code(), locator()); |
1508 emit_byte(0xE9); | 1510 emit_int8((unsigned char)0xE9); |
1509 emit_long(0); | 1511 emit_long(0); |
1510 } | 1512 } |
1511 } | 1513 } |
1512 | 1514 |
1513 void Assembler::jmp(Register entry) { | 1515 void Assembler::jmp(Register entry) { |
1514 int encode = prefix_and_encode(entry->encoding()); | 1516 int encode = prefix_and_encode(entry->encoding()); |
1515 emit_byte(0xFF); | 1517 emit_int8((unsigned char)0xFF); |
1516 emit_byte(0xE0 | encode); | 1518 emit_int8((unsigned char)(0xE0 | encode)); |
1517 } | 1519 } |
1518 | 1520 |
1519 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | 1521 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { |
1520 InstructionMark im(this); | 1522 InstructionMark im(this); |
1521 emit_byte(0xE9); | 1523 emit_int8((unsigned char)0xE9); |
1522 assert(dest != NULL, "must have a target"); | 1524 assert(dest != NULL, "must have a target"); |
1523 intptr_t disp = dest - (pc() + sizeof(int32_t)); | 1525 intptr_t disp = dest - (pc() + sizeof(int32_t)); |
1524 assert(is_simm32(disp), "must be 32bit offset (jmp)"); | 1526 assert(is_simm32(disp), "must be 32bit offset (jmp)"); |
1525 emit_data(disp, rspec.reloc(), call32_operand); | 1527 emit_data(disp, rspec.reloc(), call32_operand); |
1526 } | 1528 } |
1537 dist += (dist < 0 ? (-delta) :delta); | 1539 dist += (dist < 0 ? (-delta) :delta); |
1538 } | 1540 } |
1539 assert(is8bit(dist), "Dispacement too large for a short jmp"); | 1541 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
1540 #endif | 1542 #endif |
1541 intptr_t offs = entry - pc(); | 1543 intptr_t offs = entry - pc(); |
1542 emit_byte(0xEB); | 1544 emit_int8((unsigned char)0xEB); |
1543 emit_byte((offs - short_size) & 0xFF); | 1545 emit_int8((offs - short_size) & 0xFF); |
1544 } else { | 1546 } else { |
1545 InstructionMark im(this); | 1547 InstructionMark im(this); |
1546 L.add_patch_at(code(), locator()); | 1548 L.add_patch_at(code(), locator()); |
1547 emit_byte(0xEB); | 1549 emit_int8((unsigned char)0xEB); |
1548 emit_byte(0); | 1550 emit_int8(0); |
1549 } | 1551 } |
1550 } | 1552 } |
1551 | 1553 |
1552 void Assembler::ldmxcsr( Address src) { | 1554 void Assembler::ldmxcsr( Address src) { |
1553 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1555 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1554 InstructionMark im(this); | 1556 InstructionMark im(this); |
1555 prefix(src); | 1557 prefix(src); |
1556 emit_byte(0x0F); | 1558 emit_int8(0x0F); |
1557 emit_byte(0xAE); | 1559 emit_int8((unsigned char)0xAE); |
1558 emit_operand(as_Register(2), src); | 1560 emit_operand(as_Register(2), src); |
1559 } | 1561 } |
1560 | 1562 |
1561 void Assembler::leal(Register dst, Address src) { | 1563 void Assembler::leal(Register dst, Address src) { |
1562 InstructionMark im(this); | 1564 InstructionMark im(this); |
1563 #ifdef _LP64 | 1565 #ifdef _LP64 |
1564 emit_byte(0x67); // addr32 | 1566 emit_int8(0x67); // addr32 |
1565 prefix(src, dst); | 1567 prefix(src, dst); |
1566 #endif // LP64 | 1568 #endif // LP64 |
1567 emit_byte(0x8D); | 1569 emit_int8((unsigned char)0x8D); |
1568 emit_operand(dst, src); | 1570 emit_operand(dst, src); |
1569 } | 1571 } |
1570 | 1572 |
1571 void Assembler::lfence() { | 1573 void Assembler::lfence() { |
1572 emit_byte(0x0F); | 1574 emit_int8(0x0F); |
1573 emit_byte(0xAE); | 1575 emit_int8((unsigned char)0xAE); |
1574 emit_byte(0xE8); | 1576 emit_int8((unsigned char)0xE8); |
1575 } | 1577 } |
1576 | 1578 |
1577 void Assembler::lock() { | 1579 void Assembler::lock() { |
1578 emit_byte(0xF0); | 1580 emit_int8((unsigned char)0xF0); |
1579 } | 1581 } |
1580 | 1582 |
1581 void Assembler::lzcntl(Register dst, Register src) { | 1583 void Assembler::lzcntl(Register dst, Register src) { |
1582 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); | 1584 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
1583 emit_byte(0xF3); | 1585 emit_int8((unsigned char)0xF3); |
1584 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 1586 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
1585 emit_byte(0x0F); | 1587 emit_int8(0x0F); |
1586 emit_byte(0xBD); | 1588 emit_int8((unsigned char)0xBD); |
1587 emit_byte(0xC0 | encode); | 1589 emit_int8((unsigned char)(0xC0 | encode)); |
1588 } | 1590 } |
1589 | 1591 |
1590 // Emit mfence instruction | 1592 // Emit mfence instruction |
1591 void Assembler::mfence() { | 1593 void Assembler::mfence() { |
1592 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) | 1594 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
1593 emit_byte( 0x0F ); | 1595 emit_int8(0x0F); |
1594 emit_byte( 0xAE ); | 1596 emit_int8((unsigned char)0xAE); |
1595 emit_byte( 0xF0 ); | 1597 emit_int8((unsigned char)0xF0); |
1596 } | 1598 } |
1597 | 1599 |
1598 void Assembler::mov(Register dst, Register src) { | 1600 void Assembler::mov(Register dst, Register src) { |
1599 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | 1601 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); |
1600 } | 1602 } |
1610 } | 1612 } |
1611 | 1613 |
1612 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { | 1614 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { |
1613 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1615 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1614 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE); | 1616 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE); |
1615 emit_byte(0x16); | 1617 emit_int8(0x16); |
1616 emit_byte(0xC0 | encode); | 1618 emit_int8((unsigned char)(0xC0 | encode)); |
1617 } | 1619 } |
1618 | 1620 |
1619 void Assembler::movb(Register dst, Address src) { | 1621 void Assembler::movb(Register dst, Address src) { |
1620 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | 1622 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); |
1621 InstructionMark im(this); | 1623 InstructionMark im(this); |
1622 prefix(src, dst, true); | 1624 prefix(src, dst, true); |
1623 emit_byte(0x8A); | 1625 emit_int8((unsigned char)0x8A); |
1624 emit_operand(dst, src); | 1626 emit_operand(dst, src); |
1625 } | 1627 } |
1626 | 1628 |
1627 | 1629 |
1628 void Assembler::movb(Address dst, int imm8) { | 1630 void Assembler::movb(Address dst, int imm8) { |
1629 InstructionMark im(this); | 1631 InstructionMark im(this); |
1630 prefix(dst); | 1632 prefix(dst); |
1631 emit_byte(0xC6); | 1633 emit_int8((unsigned char)0xC6); |
1632 emit_operand(rax, dst, 1); | 1634 emit_operand(rax, dst, 1); |
1633 emit_byte(imm8); | 1635 emit_int8(imm8); |
1634 } | 1636 } |
1635 | 1637 |
1636 | 1638 |
1637 void Assembler::movb(Address dst, Register src) { | 1639 void Assembler::movb(Address dst, Register src) { |
1638 assert(src->has_byte_register(), "must have byte register"); | 1640 assert(src->has_byte_register(), "must have byte register"); |
1639 InstructionMark im(this); | 1641 InstructionMark im(this); |
1640 prefix(dst, src, true); | 1642 prefix(dst, src, true); |
1641 emit_byte(0x88); | 1643 emit_int8((unsigned char)0x88); |
1642 emit_operand(src, dst); | 1644 emit_operand(src, dst); |
1643 } | 1645 } |
1644 | 1646 |
1645 void Assembler::movdl(XMMRegister dst, Register src) { | 1647 void Assembler::movdl(XMMRegister dst, Register src) { |
1646 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1648 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1647 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); | 1649 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
1648 emit_byte(0x6E); | 1650 emit_int8(0x6E); |
1649 emit_byte(0xC0 | encode); | 1651 emit_int8((unsigned char)(0xC0 | encode)); |
1650 } | 1652 } |
1651 | 1653 |
1652 void Assembler::movdl(Register dst, XMMRegister src) { | 1654 void Assembler::movdl(Register dst, XMMRegister src) { |
1653 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1655 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1654 // swap src/dst to get correct prefix | 1656 // swap src/dst to get correct prefix |
1655 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66); | 1657 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66); |
1656 emit_byte(0x7E); | 1658 emit_int8(0x7E); |
1657 emit_byte(0xC0 | encode); | 1659 emit_int8((unsigned char)(0xC0 | encode)); |
1658 } | 1660 } |
1659 | 1661 |
1660 void Assembler::movdl(XMMRegister dst, Address src) { | 1662 void Assembler::movdl(XMMRegister dst, Address src) { |
1661 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1663 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1662 InstructionMark im(this); | 1664 InstructionMark im(this); |
1663 simd_prefix(dst, src, VEX_SIMD_66); | 1665 simd_prefix(dst, src, VEX_SIMD_66); |
1664 emit_byte(0x6E); | 1666 emit_int8(0x6E); |
1665 emit_operand(dst, src); | 1667 emit_operand(dst, src); |
1666 } | 1668 } |
1667 | 1669 |
1668 void Assembler::movdl(Address dst, XMMRegister src) { | 1670 void Assembler::movdl(Address dst, XMMRegister src) { |
1669 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1671 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1670 InstructionMark im(this); | 1672 InstructionMark im(this); |
1671 simd_prefix(dst, src, VEX_SIMD_66); | 1673 simd_prefix(dst, src, VEX_SIMD_66); |
1672 emit_byte(0x7E); | 1674 emit_int8(0x7E); |
1673 emit_operand(src, dst); | 1675 emit_operand(src, dst); |
1674 } | 1676 } |
1675 | 1677 |
1676 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { | 1678 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { |
1677 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1679 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1690 | 1692 |
1691 void Assembler::movdqu(Address dst, XMMRegister src) { | 1693 void Assembler::movdqu(Address dst, XMMRegister src) { |
1692 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1694 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1693 InstructionMark im(this); | 1695 InstructionMark im(this); |
1694 simd_prefix(dst, src, VEX_SIMD_F3); | 1696 simd_prefix(dst, src, VEX_SIMD_F3); |
1695 emit_byte(0x7F); | 1697 emit_int8(0x7F); |
1696 emit_operand(src, dst); | 1698 emit_operand(src, dst); |
1697 } | 1699 } |
1698 | 1700 |
1699 // Move Unaligned 256bit Vector | 1701 // Move Unaligned 256bit Vector |
1700 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { | 1702 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { |
1701 assert(UseAVX, ""); | 1703 assert(UseAVX, ""); |
1702 bool vector256 = true; | 1704 bool vector256 = true; |
1703 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256); | 1705 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
1704 emit_byte(0x6F); | 1706 emit_int8(0x6F); |
1705 emit_byte(0xC0 | encode); | 1707 emit_int8((unsigned char)(0xC0 | encode)); |
1706 } | 1708 } |
1707 | 1709 |
1708 void Assembler::vmovdqu(XMMRegister dst, Address src) { | 1710 void Assembler::vmovdqu(XMMRegister dst, Address src) { |
1709 assert(UseAVX, ""); | 1711 assert(UseAVX, ""); |
1710 InstructionMark im(this); | 1712 InstructionMark im(this); |
1711 bool vector256 = true; | 1713 bool vector256 = true; |
1712 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256); | 1714 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
1713 emit_byte(0x6F); | 1715 emit_int8(0x6F); |
1714 emit_operand(dst, src); | 1716 emit_operand(dst, src); |
1715 } | 1717 } |
1716 | 1718 |
1717 void Assembler::vmovdqu(Address dst, XMMRegister src) { | 1719 void Assembler::vmovdqu(Address dst, XMMRegister src) { |
1718 assert(UseAVX, ""); | 1720 assert(UseAVX, ""); |
1719 InstructionMark im(this); | 1721 InstructionMark im(this); |
1720 bool vector256 = true; | 1722 bool vector256 = true; |
1721 // swap src<->dst for encoding | 1723 // swap src<->dst for encoding |
1722 assert(src != xnoreg, "sanity"); | 1724 assert(src != xnoreg, "sanity"); |
1723 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256); | 1725 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256); |
1724 emit_byte(0x7F); | 1726 emit_int8(0x7F); |
1725 emit_operand(src, dst); | 1727 emit_operand(src, dst); |
1726 } | 1728 } |
1727 | 1729 |
1728 // Uses zero extension on 64bit | 1730 // Uses zero extension on 64bit |
1729 | 1731 |
1730 void Assembler::movl(Register dst, int32_t imm32) { | 1732 void Assembler::movl(Register dst, int32_t imm32) { |
1731 int encode = prefix_and_encode(dst->encoding()); | 1733 int encode = prefix_and_encode(dst->encoding()); |
1732 emit_byte(0xB8 | encode); | 1734 emit_int8((unsigned char)(0xB8 | encode)); |
1733 emit_long(imm32); | 1735 emit_long(imm32); |
1734 } | 1736 } |
1735 | 1737 |
1736 void Assembler::movl(Register dst, Register src) { | 1738 void Assembler::movl(Register dst, Register src) { |
1737 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 1739 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
1738 emit_byte(0x8B); | 1740 emit_int8((unsigned char)0x8B); |
1739 emit_byte(0xC0 | encode); | 1741 emit_int8((unsigned char)(0xC0 | encode)); |
1740 } | 1742 } |
1741 | 1743 |
1742 void Assembler::movl(Register dst, Address src) { | 1744 void Assembler::movl(Register dst, Address src) { |
1743 InstructionMark im(this); | 1745 InstructionMark im(this); |
1744 prefix(src, dst); | 1746 prefix(src, dst); |
1745 emit_byte(0x8B); | 1747 emit_int8((unsigned char)0x8B); |
1746 emit_operand(dst, src); | 1748 emit_operand(dst, src); |
1747 } | 1749 } |
1748 | 1750 |
1749 void Assembler::movl(Address dst, int32_t imm32) { | 1751 void Assembler::movl(Address dst, int32_t imm32) { |
1750 InstructionMark im(this); | 1752 InstructionMark im(this); |
1751 prefix(dst); | 1753 prefix(dst); |
1752 emit_byte(0xC7); | 1754 emit_int8((unsigned char)0xC7); |
1753 emit_operand(rax, dst, 4); | 1755 emit_operand(rax, dst, 4); |
1754 emit_long(imm32); | 1756 emit_long(imm32); |
1755 } | 1757 } |
1756 | 1758 |
1757 void Assembler::movl(Address dst, Register src) { | 1759 void Assembler::movl(Address dst, Register src) { |
1758 InstructionMark im(this); | 1760 InstructionMark im(this); |
1759 prefix(dst, src); | 1761 prefix(dst, src); |
1760 emit_byte(0x89); | 1762 emit_int8((unsigned char)0x89); |
1761 emit_operand(src, dst); | 1763 emit_operand(src, dst); |
1762 } | 1764 } |
1763 | 1765 |
1764 // New cpus require to use movsd and movss to avoid partial register stall | 1766 // New cpus require to use movsd and movss to avoid partial register stall |
1765 // when loading from memory. But for old Opteron use movlpd instead of movsd. | 1767 // when loading from memory. But for old Opteron use movlpd instead of movsd. |
1769 emit_simd_arith(0x12, dst, src, VEX_SIMD_66); | 1771 emit_simd_arith(0x12, dst, src, VEX_SIMD_66); |
1770 } | 1772 } |
1771 | 1773 |
1772 void Assembler::movq( MMXRegister dst, Address src ) { | 1774 void Assembler::movq( MMXRegister dst, Address src ) { |
1773 assert( VM_Version::supports_mmx(), "" ); | 1775 assert( VM_Version::supports_mmx(), "" ); |
1774 emit_byte(0x0F); | 1776 emit_int8(0x0F); |
1775 emit_byte(0x6F); | 1777 emit_int8(0x6F); |
1776 emit_operand(dst, src); | 1778 emit_operand(dst, src); |
1777 } | 1779 } |
1778 | 1780 |
1779 void Assembler::movq( Address dst, MMXRegister src ) { | 1781 void Assembler::movq( Address dst, MMXRegister src ) { |
1780 assert( VM_Version::supports_mmx(), "" ); | 1782 assert( VM_Version::supports_mmx(), "" ); |
1781 emit_byte(0x0F); | 1783 emit_int8(0x0F); |
1782 emit_byte(0x7F); | 1784 emit_int8(0x7F); |
1783 // workaround gcc (3.2.1-7a) bug | 1785 // workaround gcc (3.2.1-7a) bug |
1784 // In that version of gcc with only an emit_operand(MMX, Address) | 1786 // In that version of gcc with only an emit_operand(MMX, Address) |
1785 // gcc will tail jump and try and reverse the parameters completely | 1787 // gcc will tail jump and try and reverse the parameters completely |
1786 // obliterating dst in the process. By having a version available | 1788 // obliterating dst in the process. By having a version available |
1787 // that doesn't need to swap the args at the tail jump the bug is | 1789 // that doesn't need to swap the args at the tail jump the bug is |
1791 | 1793 |
1792 void Assembler::movq(XMMRegister dst, Address src) { | 1794 void Assembler::movq(XMMRegister dst, Address src) { |
1793 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1795 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1794 InstructionMark im(this); | 1796 InstructionMark im(this); |
1795 simd_prefix(dst, src, VEX_SIMD_F3); | 1797 simd_prefix(dst, src, VEX_SIMD_F3); |
1796 emit_byte(0x7E); | 1798 emit_int8(0x7E); |
1797 emit_operand(dst, src); | 1799 emit_operand(dst, src); |
1798 } | 1800 } |
1799 | 1801 |
1800 void Assembler::movq(Address dst, XMMRegister src) { | 1802 void Assembler::movq(Address dst, XMMRegister src) { |
1801 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1803 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1802 InstructionMark im(this); | 1804 InstructionMark im(this); |
1803 simd_prefix(dst, src, VEX_SIMD_66); | 1805 simd_prefix(dst, src, VEX_SIMD_66); |
1804 emit_byte(0xD6); | 1806 emit_int8((unsigned char)0xD6); |
1805 emit_operand(src, dst); | 1807 emit_operand(src, dst); |
1806 } | 1808 } |
1807 | 1809 |
1808 void Assembler::movsbl(Register dst, Address src) { // movsxb | 1810 void Assembler::movsbl(Register dst, Address src) { // movsxb |
1809 InstructionMark im(this); | 1811 InstructionMark im(this); |
1810 prefix(src, dst); | 1812 prefix(src, dst); |
1811 emit_byte(0x0F); | 1813 emit_int8(0x0F); |
1812 emit_byte(0xBE); | 1814 emit_int8((unsigned char)0xBE); |
1813 emit_operand(dst, src); | 1815 emit_operand(dst, src); |
1814 } | 1816 } |
1815 | 1817 |
1816 void Assembler::movsbl(Register dst, Register src) { // movsxb | 1818 void Assembler::movsbl(Register dst, Register src) { // movsxb |
1817 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | 1819 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); |
1818 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | 1820 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); |
1819 emit_byte(0x0F); | 1821 emit_int8(0x0F); |
1820 emit_byte(0xBE); | 1822 emit_int8((unsigned char)0xBE); |
1821 emit_byte(0xC0 | encode); | 1823 emit_int8((unsigned char)(0xC0 | encode)); |
1822 } | 1824 } |
1823 | 1825 |
1824 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | 1826 void Assembler::movsd(XMMRegister dst, XMMRegister src) { |
1825 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1827 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1826 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2); | 1828 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2); |
1833 | 1835 |
1834 void Assembler::movsd(Address dst, XMMRegister src) { | 1836 void Assembler::movsd(Address dst, XMMRegister src) { |
1835 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1837 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1836 InstructionMark im(this); | 1838 InstructionMark im(this); |
1837 simd_prefix(dst, src, VEX_SIMD_F2); | 1839 simd_prefix(dst, src, VEX_SIMD_F2); |
1838 emit_byte(0x11); | 1840 emit_int8(0x11); |
1839 emit_operand(src, dst); | 1841 emit_operand(src, dst); |
1840 } | 1842 } |
1841 | 1843 |
1842 void Assembler::movss(XMMRegister dst, XMMRegister src) { | 1844 void Assembler::movss(XMMRegister dst, XMMRegister src) { |
1843 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1845 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1851 | 1853 |
1852 void Assembler::movss(Address dst, XMMRegister src) { | 1854 void Assembler::movss(Address dst, XMMRegister src) { |
1853 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1855 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1854 InstructionMark im(this); | 1856 InstructionMark im(this); |
1855 simd_prefix(dst, src, VEX_SIMD_F3); | 1857 simd_prefix(dst, src, VEX_SIMD_F3); |
1856 emit_byte(0x11); | 1858 emit_int8(0x11); |
1857 emit_operand(src, dst); | 1859 emit_operand(src, dst); |
1858 } | 1860 } |
1859 | 1861 |
1860 void Assembler::movswl(Register dst, Address src) { // movsxw | 1862 void Assembler::movswl(Register dst, Address src) { // movsxw |
1861 InstructionMark im(this); | 1863 InstructionMark im(this); |
1862 prefix(src, dst); | 1864 prefix(src, dst); |
1863 emit_byte(0x0F); | 1865 emit_int8(0x0F); |
1864 emit_byte(0xBF); | 1866 emit_int8((unsigned char)0xBF); |
1865 emit_operand(dst, src); | 1867 emit_operand(dst, src); |
1866 } | 1868 } |
1867 | 1869 |
1868 void Assembler::movswl(Register dst, Register src) { // movsxw | 1870 void Assembler::movswl(Register dst, Register src) { // movsxw |
1869 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 1871 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
1870 emit_byte(0x0F); | 1872 emit_int8(0x0F); |
1871 emit_byte(0xBF); | 1873 emit_int8((unsigned char)0xBF); |
1872 emit_byte(0xC0 | encode); | 1874 emit_int8((unsigned char)(0xC0 | encode)); |
1873 } | 1875 } |
1874 | 1876 |
1875 void Assembler::movw(Address dst, int imm16) { | 1877 void Assembler::movw(Address dst, int imm16) { |
1876 InstructionMark im(this); | 1878 InstructionMark im(this); |
1877 | 1879 |
1878 emit_byte(0x66); // switch to 16-bit mode | 1880 emit_int8(0x66); // switch to 16-bit mode |
1879 prefix(dst); | 1881 prefix(dst); |
1880 emit_byte(0xC7); | 1882 emit_int8((unsigned char)0xC7); |
1881 emit_operand(rax, dst, 2); | 1883 emit_operand(rax, dst, 2); |
1882 emit_word(imm16); | 1884 emit_int16(imm16); |
1883 } | 1885 } |
1884 | 1886 |
1885 void Assembler::movw(Register dst, Address src) { | 1887 void Assembler::movw(Register dst, Address src) { |
1886 InstructionMark im(this); | 1888 InstructionMark im(this); |
1887 emit_byte(0x66); | 1889 emit_int8(0x66); |
1888 prefix(src, dst); | 1890 prefix(src, dst); |
1889 emit_byte(0x8B); | 1891 emit_int8((unsigned char)0x8B); |
1890 emit_operand(dst, src); | 1892 emit_operand(dst, src); |
1891 } | 1893 } |
1892 | 1894 |
1893 void Assembler::movw(Address dst, Register src) { | 1895 void Assembler::movw(Address dst, Register src) { |
1894 InstructionMark im(this); | 1896 InstructionMark im(this); |
1895 emit_byte(0x66); | 1897 emit_int8(0x66); |
1896 prefix(dst, src); | 1898 prefix(dst, src); |
1897 emit_byte(0x89); | 1899 emit_int8((unsigned char)0x89); |
1898 emit_operand(src, dst); | 1900 emit_operand(src, dst); |
1899 } | 1901 } |
1900 | 1902 |
1901 void Assembler::movzbl(Register dst, Address src) { // movzxb | 1903 void Assembler::movzbl(Register dst, Address src) { // movzxb |
1902 InstructionMark im(this); | 1904 InstructionMark im(this); |
1903 prefix(src, dst); | 1905 prefix(src, dst); |
1904 emit_byte(0x0F); | 1906 emit_int8(0x0F); |
1905 emit_byte(0xB6); | 1907 emit_int8((unsigned char)0xB6); |
1906 emit_operand(dst, src); | 1908 emit_operand(dst, src); |
1907 } | 1909 } |
1908 | 1910 |
1909 void Assembler::movzbl(Register dst, Register src) { // movzxb | 1911 void Assembler::movzbl(Register dst, Register src) { // movzxb |
1910 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | 1912 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); |
1911 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | 1913 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); |
1912 emit_byte(0x0F); | 1914 emit_int8(0x0F); |
1913 emit_byte(0xB6); | 1915 emit_int8((unsigned char)0xB6); |
1914 emit_byte(0xC0 | encode); | 1916 emit_int8(0xC0 | encode); |
1915 } | 1917 } |
1916 | 1918 |
1917 void Assembler::movzwl(Register dst, Address src) { // movzxw | 1919 void Assembler::movzwl(Register dst, Address src) { // movzxw |
1918 InstructionMark im(this); | 1920 InstructionMark im(this); |
1919 prefix(src, dst); | 1921 prefix(src, dst); |
1920 emit_byte(0x0F); | 1922 emit_int8(0x0F); |
1921 emit_byte(0xB7); | 1923 emit_int8((unsigned char)0xB7); |
1922 emit_operand(dst, src); | 1924 emit_operand(dst, src); |
1923 } | 1925 } |
1924 | 1926 |
1925 void Assembler::movzwl(Register dst, Register src) { // movzxw | 1927 void Assembler::movzwl(Register dst, Register src) { // movzxw |
1926 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 1928 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
1927 emit_byte(0x0F); | 1929 emit_int8(0x0F); |
1928 emit_byte(0xB7); | 1930 emit_int8((unsigned char)0xB7); |
1929 emit_byte(0xC0 | encode); | 1931 emit_int8(0xC0 | encode); |
1930 } | 1932 } |
1931 | 1933 |
1932 void Assembler::mull(Address src) { | 1934 void Assembler::mull(Address src) { |
1933 InstructionMark im(this); | 1935 InstructionMark im(this); |
1934 prefix(src); | 1936 prefix(src); |
1935 emit_byte(0xF7); | 1937 emit_int8((unsigned char)0xF7); |
1936 emit_operand(rsp, src); | 1938 emit_operand(rsp, src); |
1937 } | 1939 } |
1938 | 1940 |
1939 void Assembler::mull(Register src) { | 1941 void Assembler::mull(Register src) { |
1940 int encode = prefix_and_encode(src->encoding()); | 1942 int encode = prefix_and_encode(src->encoding()); |
1941 emit_byte(0xF7); | 1943 emit_int8((unsigned char)0xF7); |
1942 emit_byte(0xE0 | encode); | 1944 emit_int8((unsigned char)(0xE0 | encode)); |
1943 } | 1945 } |
1944 | 1946 |
1945 void Assembler::mulsd(XMMRegister dst, Address src) { | 1947 void Assembler::mulsd(XMMRegister dst, Address src) { |
1946 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1948 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1947 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); | 1949 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); |
1962 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); | 1964 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); |
1963 } | 1965 } |
1964 | 1966 |
1965 void Assembler::negl(Register dst) { | 1967 void Assembler::negl(Register dst) { |
1966 int encode = prefix_and_encode(dst->encoding()); | 1968 int encode = prefix_and_encode(dst->encoding()); |
1967 emit_byte(0xF7); | 1969 emit_int8((unsigned char)0xF7); |
1968 emit_byte(0xD8 | encode); | 1970 emit_int8((unsigned char)(0xD8 | encode)); |
1969 } | 1971 } |
1970 | 1972 |
1971 void Assembler::nop(int i) { | 1973 void Assembler::nop(int i) { |
1972 #ifdef ASSERT | 1974 #ifdef ASSERT |
1973 assert(i > 0, " "); | 1975 assert(i > 0, " "); |
1974 // The fancy nops aren't currently recognized by debuggers making it a | 1976 // The fancy nops aren't currently recognized by debuggers making it a |
1975 // pain to disassemble code while debugging. If asserts are on clearly | 1977 // pain to disassemble code while debugging. If asserts are on clearly |
1976 // speed is not an issue so simply use the single byte traditional nop | 1978 // speed is not an issue so simply use the single byte traditional nop |
1977 // to do alignment. | 1979 // to do alignment. |
1978 | 1980 |
1979 for (; i > 0 ; i--) emit_byte(0x90); | 1981 for (; i > 0 ; i--) emit_int8((unsigned char)0x90); |
1980 return; | 1982 return; |
1981 | 1983 |
1982 #endif // ASSERT | 1984 #endif // ASSERT |
1983 | 1985 |
1984 if (UseAddressNop && VM_Version::is_intel()) { | 1986 if (UseAddressNop && VM_Version::is_intel()) { |
2004 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | 2006 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 |
2005 | 2007 |
2006 while(i >= 15) { | 2008 while(i >= 15) { |
2007 // For Intel don't generate consecutive addess nops (mix with regular nops) | 2009 // For Intel don't generate consecutive addess nops (mix with regular nops) |
2008 i -= 15; | 2010 i -= 15; |
2009 emit_byte(0x66); // size prefix | 2011 emit_int8(0x66); // size prefix |
2010 emit_byte(0x66); // size prefix | 2012 emit_int8(0x66); // size prefix |
2011 emit_byte(0x66); // size prefix | 2013 emit_int8(0x66); // size prefix |
2012 addr_nop_8(); | 2014 addr_nop_8(); |
2013 emit_byte(0x66); // size prefix | 2015 emit_int8(0x66); // size prefix |
2014 emit_byte(0x66); // size prefix | 2016 emit_int8(0x66); // size prefix |
2015 emit_byte(0x66); // size prefix | 2017 emit_int8(0x66); // size prefix |
2016 emit_byte(0x90); // nop | 2018 emit_int8((unsigned char)0x90); |
2019 // nop | |
2017 } | 2020 } |
2018 switch (i) { | 2021 switch (i) { |
2019 case 14: | 2022 case 14: |
2020 emit_byte(0x66); // size prefix | 2023 emit_int8(0x66); // size prefix |
2021 case 13: | 2024 case 13: |
2022 emit_byte(0x66); // size prefix | 2025 emit_int8(0x66); // size prefix |
2023 case 12: | 2026 case 12: |
2024 addr_nop_8(); | 2027 addr_nop_8(); |
2025 emit_byte(0x66); // size prefix | 2028 emit_int8(0x66); // size prefix |
2026 emit_byte(0x66); // size prefix | 2029 emit_int8(0x66); // size prefix |
2027 emit_byte(0x66); // size prefix | 2030 emit_int8(0x66); // size prefix |
2028 emit_byte(0x90); // nop | 2031 emit_int8((unsigned char)0x90); |
2032 // nop | |
2029 break; | 2033 break; |
2030 case 11: | 2034 case 11: |
2031 emit_byte(0x66); // size prefix | 2035 emit_int8(0x66); // size prefix |
2032 case 10: | 2036 case 10: |
2033 emit_byte(0x66); // size prefix | 2037 emit_int8(0x66); // size prefix |
2034 case 9: | 2038 case 9: |
2035 emit_byte(0x66); // size prefix | 2039 emit_int8(0x66); // size prefix |
2036 case 8: | 2040 case 8: |
2037 addr_nop_8(); | 2041 addr_nop_8(); |
2038 break; | 2042 break; |
2039 case 7: | 2043 case 7: |
2040 addr_nop_7(); | 2044 addr_nop_7(); |
2041 break; | 2045 break; |
2042 case 6: | 2046 case 6: |
2043 emit_byte(0x66); // size prefix | 2047 emit_int8(0x66); // size prefix |
2044 case 5: | 2048 case 5: |
2045 addr_nop_5(); | 2049 addr_nop_5(); |
2046 break; | 2050 break; |
2047 case 4: | 2051 case 4: |
2048 addr_nop_4(); | 2052 addr_nop_4(); |
2049 break; | 2053 break; |
2050 case 3: | 2054 case 3: |
2051 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | 2055 // Don't use "0x0F 0x1F 0x00" - need patching safe padding |
2052 emit_byte(0x66); // size prefix | 2056 emit_int8(0x66); // size prefix |
2053 case 2: | 2057 case 2: |
2054 emit_byte(0x66); // size prefix | 2058 emit_int8(0x66); // size prefix |
2055 case 1: | 2059 case 1: |
2056 emit_byte(0x90); // nop | 2060 emit_int8((unsigned char)0x90); |
2061 // nop | |
2057 break; | 2062 break; |
2058 default: | 2063 default: |
2059 assert(i == 0, " "); | 2064 assert(i == 0, " "); |
2060 } | 2065 } |
2061 return; | 2066 return; |
2084 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | 2089 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 |
2085 // Size prefixes (0x66) are added for larger sizes | 2090 // Size prefixes (0x66) are added for larger sizes |
2086 | 2091 |
2087 while(i >= 22) { | 2092 while(i >= 22) { |
2088 i -= 11; | 2093 i -= 11; |
2089 emit_byte(0x66); // size prefix | 2094 emit_int8(0x66); // size prefix |
2090 emit_byte(0x66); // size prefix | 2095 emit_int8(0x66); // size prefix |
2091 emit_byte(0x66); // size prefix | 2096 emit_int8(0x66); // size prefix |
2092 addr_nop_8(); | 2097 addr_nop_8(); |
2093 } | 2098 } |
2094 // Generate first nop for size between 21-12 | 2099 // Generate first nop for size between 21-12 |
2095 switch (i) { | 2100 switch (i) { |
2096 case 21: | 2101 case 21: |
2097 i -= 1; | 2102 i -= 1; |
2098 emit_byte(0x66); // size prefix | 2103 emit_int8(0x66); // size prefix |
2099 case 20: | 2104 case 20: |
2100 case 19: | 2105 case 19: |
2101 i -= 1; | 2106 i -= 1; |
2102 emit_byte(0x66); // size prefix | 2107 emit_int8(0x66); // size prefix |
2103 case 18: | 2108 case 18: |
2104 case 17: | 2109 case 17: |
2105 i -= 1; | 2110 i -= 1; |
2106 emit_byte(0x66); // size prefix | 2111 emit_int8(0x66); // size prefix |
2107 case 16: | 2112 case 16: |
2108 case 15: | 2113 case 15: |
2109 i -= 8; | 2114 i -= 8; |
2110 addr_nop_8(); | 2115 addr_nop_8(); |
2111 break; | 2116 break; |
2114 i -= 7; | 2119 i -= 7; |
2115 addr_nop_7(); | 2120 addr_nop_7(); |
2116 break; | 2121 break; |
2117 case 12: | 2122 case 12: |
2118 i -= 6; | 2123 i -= 6; |
2119 emit_byte(0x66); // size prefix | 2124 emit_int8(0x66); // size prefix |
2120 addr_nop_5(); | 2125 addr_nop_5(); |
2121 break; | 2126 break; |
2122 default: | 2127 default: |
2123 assert(i < 12, " "); | 2128 assert(i < 12, " "); |
2124 } | 2129 } |
2125 | 2130 |
2126 // Generate second nop for size between 11-1 | 2131 // Generate second nop for size between 11-1 |
2127 switch (i) { | 2132 switch (i) { |
2128 case 11: | 2133 case 11: |
2129 emit_byte(0x66); // size prefix | 2134 emit_int8(0x66); // size prefix |
2130 case 10: | 2135 case 10: |
2131 emit_byte(0x66); // size prefix | 2136 emit_int8(0x66); // size prefix |
2132 case 9: | 2137 case 9: |
2133 emit_byte(0x66); // size prefix | 2138 emit_int8(0x66); // size prefix |
2134 case 8: | 2139 case 8: |
2135 addr_nop_8(); | 2140 addr_nop_8(); |
2136 break; | 2141 break; |
2137 case 7: | 2142 case 7: |
2138 addr_nop_7(); | 2143 addr_nop_7(); |
2139 break; | 2144 break; |
2140 case 6: | 2145 case 6: |
2141 emit_byte(0x66); // size prefix | 2146 emit_int8(0x66); // size prefix |
2142 case 5: | 2147 case 5: |
2143 addr_nop_5(); | 2148 addr_nop_5(); |
2144 break; | 2149 break; |
2145 case 4: | 2150 case 4: |
2146 addr_nop_4(); | 2151 addr_nop_4(); |
2147 break; | 2152 break; |
2148 case 3: | 2153 case 3: |
2149 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | 2154 // Don't use "0x0F 0x1F 0x00" - need patching safe padding |
2150 emit_byte(0x66); // size prefix | 2155 emit_int8(0x66); // size prefix |
2151 case 2: | 2156 case 2: |
2152 emit_byte(0x66); // size prefix | 2157 emit_int8(0x66); // size prefix |
2153 case 1: | 2158 case 1: |
2154 emit_byte(0x90); // nop | 2159 emit_int8((unsigned char)0x90); |
2160 // nop | |
2155 break; | 2161 break; |
2156 default: | 2162 default: |
2157 assert(i == 0, " "); | 2163 assert(i == 0, " "); |
2158 } | 2164 } |
2159 return; | 2165 return; |
2172 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | 2178 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 |
2173 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | 2179 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 |
2174 // | 2180 // |
2175 while(i > 12) { | 2181 while(i > 12) { |
2176 i -= 4; | 2182 i -= 4; |
2177 emit_byte(0x66); // size prefix | 2183 emit_int8(0x66); // size prefix |
2178 emit_byte(0x66); | 2184 emit_int8(0x66); |
2179 emit_byte(0x66); | 2185 emit_int8(0x66); |
2180 emit_byte(0x90); // nop | 2186 emit_int8((unsigned char)0x90); |
2187 // nop | |
2181 } | 2188 } |
2182 // 1 - 12 nops | 2189 // 1 - 12 nops |
2183 if(i > 8) { | 2190 if(i > 8) { |
2184 if(i > 9) { | 2191 if(i > 9) { |
2185 i -= 1; | 2192 i -= 1; |
2186 emit_byte(0x66); | 2193 emit_int8(0x66); |
2187 } | 2194 } |
2188 i -= 3; | 2195 i -= 3; |
2189 emit_byte(0x66); | 2196 emit_int8(0x66); |
2190 emit_byte(0x66); | 2197 emit_int8(0x66); |
2191 emit_byte(0x90); | 2198 emit_int8((unsigned char)0x90); |
2192 } | 2199 } |
2193 // 1 - 8 nops | 2200 // 1 - 8 nops |
2194 if(i > 4) { | 2201 if(i > 4) { |
2195 if(i > 6) { | 2202 if(i > 6) { |
2196 i -= 1; | 2203 i -= 1; |
2197 emit_byte(0x66); | 2204 emit_int8(0x66); |
2198 } | 2205 } |
2199 i -= 3; | 2206 i -= 3; |
2200 emit_byte(0x66); | 2207 emit_int8(0x66); |
2201 emit_byte(0x66); | 2208 emit_int8(0x66); |
2202 emit_byte(0x90); | 2209 emit_int8((unsigned char)0x90); |
2203 } | 2210 } |
2204 switch (i) { | 2211 switch (i) { |
2205 case 4: | 2212 case 4: |
2206 emit_byte(0x66); | 2213 emit_int8(0x66); |
2207 case 3: | 2214 case 3: |
2208 emit_byte(0x66); | 2215 emit_int8(0x66); |
2209 case 2: | 2216 case 2: |
2210 emit_byte(0x66); | 2217 emit_int8(0x66); |
2211 case 1: | 2218 case 1: |
2212 emit_byte(0x90); | 2219 emit_int8((unsigned char)0x90); |
2213 break; | 2220 break; |
2214 default: | 2221 default: |
2215 assert(i == 0, " "); | 2222 assert(i == 0, " "); |
2216 } | 2223 } |
2217 } | 2224 } |
2218 | 2225 |
2219 void Assembler::notl(Register dst) { | 2226 void Assembler::notl(Register dst) { |
2220 int encode = prefix_and_encode(dst->encoding()); | 2227 int encode = prefix_and_encode(dst->encoding()); |
2221 emit_byte(0xF7); | 2228 emit_int8((unsigned char)0xF7); |
2222 emit_byte(0xD0 | encode ); | 2229 emit_int8((unsigned char)(0xD0 | encode)); |
2223 } | 2230 } |
2224 | 2231 |
2225 void Assembler::orl(Address dst, int32_t imm32) { | 2232 void Assembler::orl(Address dst, int32_t imm32) { |
2226 InstructionMark im(this); | 2233 InstructionMark im(this); |
2227 prefix(dst); | 2234 prefix(dst); |
2234 } | 2241 } |
2235 | 2242 |
2236 void Assembler::orl(Register dst, Address src) { | 2243 void Assembler::orl(Register dst, Address src) { |
2237 InstructionMark im(this); | 2244 InstructionMark im(this); |
2238 prefix(src, dst); | 2245 prefix(src, dst); |
2239 emit_byte(0x0B); | 2246 emit_int8(0x0B); |
2240 emit_operand(dst, src); | 2247 emit_operand(dst, src); |
2241 } | 2248 } |
2242 | 2249 |
2243 void Assembler::orl(Register dst, Register src) { | 2250 void Assembler::orl(Register dst, Register src) { |
2244 (void) prefix_and_encode(dst->encoding(), src->encoding()); | 2251 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
2258 | 2265 |
2259 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { | 2266 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
2260 assert(VM_Version::supports_sse4_2(), ""); | 2267 assert(VM_Version::supports_sse4_2(), ""); |
2261 InstructionMark im(this); | 2268 InstructionMark im(this); |
2262 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); | 2269 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
2263 emit_byte(0x61); | 2270 emit_int8(0x61); |
2264 emit_operand(dst, src); | 2271 emit_operand(dst, src); |
2265 emit_byte(imm8); | 2272 emit_int8(imm8); |
2266 } | 2273 } |
2267 | 2274 |
2268 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | 2275 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { |
2269 assert(VM_Version::supports_sse4_2(), ""); | 2276 assert(VM_Version::supports_sse4_2(), ""); |
2270 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); | 2277 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
2271 emit_byte(0x61); | 2278 emit_int8(0x61); |
2272 emit_byte(0xC0 | encode); | 2279 emit_int8((unsigned char)(0xC0 | encode)); |
2273 emit_byte(imm8); | 2280 emit_int8(imm8); |
2274 } | 2281 } |
2275 | 2282 |
2276 void Assembler::pmovzxbw(XMMRegister dst, Address src) { | 2283 void Assembler::pmovzxbw(XMMRegister dst, Address src) { |
2277 assert(VM_Version::supports_sse4_1(), ""); | 2284 assert(VM_Version::supports_sse4_1(), ""); |
2278 InstructionMark im(this); | 2285 InstructionMark im(this); |
2279 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 2286 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
2280 emit_byte(0x30); | 2287 emit_int8(0x30); |
2281 emit_operand(dst, src); | 2288 emit_operand(dst, src); |
2282 } | 2289 } |
2283 | 2290 |
2284 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { | 2291 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { |
2285 assert(VM_Version::supports_sse4_1(), ""); | 2292 assert(VM_Version::supports_sse4_1(), ""); |
2286 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 2293 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
2287 emit_byte(0x30); | 2294 emit_int8(0x30); |
2288 emit_byte(0xC0 | encode); | 2295 emit_int8((unsigned char)(0xC0 | encode)); |
2289 } | 2296 } |
2290 | 2297 |
2291 // generic | 2298 // generic |
2292 void Assembler::pop(Register dst) { | 2299 void Assembler::pop(Register dst) { |
2293 int encode = prefix_and_encode(dst->encoding()); | 2300 int encode = prefix_and_encode(dst->encoding()); |
2294 emit_byte(0x58 | encode); | 2301 emit_int8(0x58 | encode); |
2295 } | 2302 } |
2296 | 2303 |
2297 void Assembler::popcntl(Register dst, Address src) { | 2304 void Assembler::popcntl(Register dst, Address src) { |
2298 assert(VM_Version::supports_popcnt(), "must support"); | 2305 assert(VM_Version::supports_popcnt(), "must support"); |
2299 InstructionMark im(this); | 2306 InstructionMark im(this); |
2300 emit_byte(0xF3); | 2307 emit_int8((unsigned char)0xF3); |
2301 prefix(src, dst); | 2308 prefix(src, dst); |
2302 emit_byte(0x0F); | 2309 emit_int8(0x0F); |
2303 emit_byte(0xB8); | 2310 emit_int8((unsigned char)0xB8); |
2304 emit_operand(dst, src); | 2311 emit_operand(dst, src); |
2305 } | 2312 } |
2306 | 2313 |
2307 void Assembler::popcntl(Register dst, Register src) { | 2314 void Assembler::popcntl(Register dst, Register src) { |
2308 assert(VM_Version::supports_popcnt(), "must support"); | 2315 assert(VM_Version::supports_popcnt(), "must support"); |
2309 emit_byte(0xF3); | 2316 emit_int8((unsigned char)0xF3); |
2310 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 2317 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
2311 emit_byte(0x0F); | 2318 emit_int8(0x0F); |
2312 emit_byte(0xB8); | 2319 emit_int8((unsigned char)0xB8); |
2313 emit_byte(0xC0 | encode); | 2320 emit_int8((unsigned char)(0xC0 | encode)); |
2314 } | 2321 } |
2315 | 2322 |
2316 void Assembler::popf() { | 2323 void Assembler::popf() { |
2317 emit_byte(0x9D); | 2324 emit_int8((unsigned char)0x9D); |
2318 } | 2325 } |
2319 | 2326 |
2320 #ifndef _LP64 // no 32bit push/pop on amd64 | 2327 #ifndef _LP64 // no 32bit push/pop on amd64 |
2321 void Assembler::popl(Address dst) { | 2328 void Assembler::popl(Address dst) { |
2322 // NOTE: this will adjust stack by 8byte on 64bits | 2329 // NOTE: this will adjust stack by 8byte on 64bits |
2323 InstructionMark im(this); | 2330 InstructionMark im(this); |
2324 prefix(dst); | 2331 prefix(dst); |
2325 emit_byte(0x8F); | 2332 emit_int8((unsigned char)0x8F); |
2326 emit_operand(rax, dst); | 2333 emit_operand(rax, dst); |
2327 } | 2334 } |
2328 #endif | 2335 #endif |
2329 | 2336 |
2330 void Assembler::prefetch_prefix(Address src) { | 2337 void Assembler::prefetch_prefix(Address src) { |
2331 prefix(src); | 2338 prefix(src); |
2332 emit_byte(0x0F); | 2339 emit_int8(0x0F); |
2333 } | 2340 } |
2334 | 2341 |
2335 void Assembler::prefetchnta(Address src) { | 2342 void Assembler::prefetchnta(Address src) { |
2336 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | 2343 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); |
2337 InstructionMark im(this); | 2344 InstructionMark im(this); |
2338 prefetch_prefix(src); | 2345 prefetch_prefix(src); |
2339 emit_byte(0x18); | 2346 emit_int8(0x18); |
2340 emit_operand(rax, src); // 0, src | 2347 emit_operand(rax, src); // 0, src |
2341 } | 2348 } |
2342 | 2349 |
2343 void Assembler::prefetchr(Address src) { | 2350 void Assembler::prefetchr(Address src) { |
2344 assert(VM_Version::supports_3dnow_prefetch(), "must support"); | 2351 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
2345 InstructionMark im(this); | 2352 InstructionMark im(this); |
2346 prefetch_prefix(src); | 2353 prefetch_prefix(src); |
2347 emit_byte(0x0D); | 2354 emit_int8(0x0D); |
2348 emit_operand(rax, src); // 0, src | 2355 emit_operand(rax, src); // 0, src |
2349 } | 2356 } |
2350 | 2357 |
2351 void Assembler::prefetcht0(Address src) { | 2358 void Assembler::prefetcht0(Address src) { |
2352 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | 2359 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); |
2353 InstructionMark im(this); | 2360 InstructionMark im(this); |
2354 prefetch_prefix(src); | 2361 prefetch_prefix(src); |
2355 emit_byte(0x18); | 2362 emit_int8(0x18); |
2356 emit_operand(rcx, src); // 1, src | 2363 emit_operand(rcx, src); // 1, src |
2357 } | 2364 } |
2358 | 2365 |
2359 void Assembler::prefetcht1(Address src) { | 2366 void Assembler::prefetcht1(Address src) { |
2360 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | 2367 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); |
2361 InstructionMark im(this); | 2368 InstructionMark im(this); |
2362 prefetch_prefix(src); | 2369 prefetch_prefix(src); |
2363 emit_byte(0x18); | 2370 emit_int8(0x18); |
2364 emit_operand(rdx, src); // 2, src | 2371 emit_operand(rdx, src); // 2, src |
2365 } | 2372 } |
2366 | 2373 |
2367 void Assembler::prefetcht2(Address src) { | 2374 void Assembler::prefetcht2(Address src) { |
2368 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | 2375 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); |
2369 InstructionMark im(this); | 2376 InstructionMark im(this); |
2370 prefetch_prefix(src); | 2377 prefetch_prefix(src); |
2371 emit_byte(0x18); | 2378 emit_int8(0x18); |
2372 emit_operand(rbx, src); // 3, src | 2379 emit_operand(rbx, src); // 3, src |
2373 } | 2380 } |
2374 | 2381 |
2375 void Assembler::prefetchw(Address src) { | 2382 void Assembler::prefetchw(Address src) { |
2376 assert(VM_Version::supports_3dnow_prefetch(), "must support"); | 2383 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
2377 InstructionMark im(this); | 2384 InstructionMark im(this); |
2378 prefetch_prefix(src); | 2385 prefetch_prefix(src); |
2379 emit_byte(0x0D); | 2386 emit_int8(0x0D); |
2380 emit_operand(rcx, src); // 1, src | 2387 emit_operand(rcx, src); // 1, src |
2381 } | 2388 } |
2382 | 2389 |
2383 void Assembler::prefix(Prefix p) { | 2390 void Assembler::prefix(Prefix p) { |
2384 a_byte(p); | 2391 emit_int8(p); |
2385 } | 2392 } |
2386 | 2393 |
2387 void Assembler::pshufb(XMMRegister dst, XMMRegister src) { | 2394 void Assembler::pshufb(XMMRegister dst, XMMRegister src) { |
2388 assert(VM_Version::supports_ssse3(), ""); | 2395 assert(VM_Version::supports_ssse3(), ""); |
2389 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 2396 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
2390 emit_byte(0x00); | 2397 emit_int8(0x00); |
2391 emit_byte(0xC0 | encode); | 2398 emit_int8((unsigned char)(0xC0 | encode)); |
2392 } | 2399 } |
2393 | 2400 |
2394 void Assembler::pshufb(XMMRegister dst, Address src) { | 2401 void Assembler::pshufb(XMMRegister dst, Address src) { |
2395 assert(VM_Version::supports_ssse3(), ""); | 2402 assert(VM_Version::supports_ssse3(), ""); |
2396 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
2397 InstructionMark im(this); | 2403 InstructionMark im(this); |
2398 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 2404 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
2399 emit_byte(0x00); | 2405 emit_int8(0x00); |
2400 emit_operand(dst, src); | 2406 emit_operand(dst, src); |
2401 } | 2407 } |
2402 | 2408 |
2403 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { | 2409 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
2404 assert(isByte(mode), "invalid value"); | 2410 assert(isByte(mode), "invalid value"); |
2405 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2411 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2406 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66); | 2412 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66); |
2407 emit_byte(mode & 0xFF); | 2413 emit_int8(mode & 0xFF); |
2408 | 2414 |
2409 } | 2415 } |
2410 | 2416 |
2411 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | 2417 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { |
2412 assert(isByte(mode), "invalid value"); | 2418 assert(isByte(mode), "invalid value"); |
2413 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2419 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2414 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | 2420 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2415 InstructionMark im(this); | 2421 InstructionMark im(this); |
2416 simd_prefix(dst, src, VEX_SIMD_66); | 2422 simd_prefix(dst, src, VEX_SIMD_66); |
2417 emit_byte(0x70); | 2423 emit_int8(0x70); |
2418 emit_operand(dst, src); | 2424 emit_operand(dst, src); |
2419 emit_byte(mode & 0xFF); | 2425 emit_int8(mode & 0xFF); |
2420 } | 2426 } |
2421 | 2427 |
2422 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | 2428 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { |
2423 assert(isByte(mode), "invalid value"); | 2429 assert(isByte(mode), "invalid value"); |
2424 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2430 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2425 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2); | 2431 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2); |
2426 emit_byte(mode & 0xFF); | 2432 emit_int8(mode & 0xFF); |
2427 } | 2433 } |
2428 | 2434 |
2429 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | 2435 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { |
2430 assert(isByte(mode), "invalid value"); | 2436 assert(isByte(mode), "invalid value"); |
2431 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2437 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2432 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | 2438 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2433 InstructionMark im(this); | 2439 InstructionMark im(this); |
2434 simd_prefix(dst, src, VEX_SIMD_F2); | 2440 simd_prefix(dst, src, VEX_SIMD_F2); |
2435 emit_byte(0x70); | 2441 emit_int8(0x70); |
2436 emit_operand(dst, src); | 2442 emit_operand(dst, src); |
2437 emit_byte(mode & 0xFF); | 2443 emit_int8(mode & 0xFF); |
2438 } | 2444 } |
2439 | 2445 |
2440 void Assembler::psrldq(XMMRegister dst, int shift) { | 2446 void Assembler::psrldq(XMMRegister dst, int shift) { |
2441 // Shift 128 bit value in xmm register by number of bytes. | 2447 // Shift 128 bit value in xmm register by number of bytes. |
2442 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2448 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2443 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66); | 2449 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66); |
2444 emit_byte(0x73); | 2450 emit_int8(0x73); |
2445 emit_byte(0xC0 | encode); | 2451 emit_int8((unsigned char)(0xC0 | encode)); |
2446 emit_byte(shift); | 2452 emit_int8(shift); |
2447 } | 2453 } |
2448 | 2454 |
2449 void Assembler::ptest(XMMRegister dst, Address src) { | 2455 void Assembler::ptest(XMMRegister dst, Address src) { |
2450 assert(VM_Version::supports_sse4_1(), ""); | 2456 assert(VM_Version::supports_sse4_1(), ""); |
2451 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | 2457 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2452 InstructionMark im(this); | 2458 InstructionMark im(this); |
2453 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 2459 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
2454 emit_byte(0x17); | 2460 emit_int8(0x17); |
2455 emit_operand(dst, src); | 2461 emit_operand(dst, src); |
2456 } | 2462 } |
2457 | 2463 |
2458 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | 2464 void Assembler::ptest(XMMRegister dst, XMMRegister src) { |
2459 assert(VM_Version::supports_sse4_1(), ""); | 2465 assert(VM_Version::supports_sse4_1(), ""); |
2460 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 2466 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
2461 emit_byte(0x17); | 2467 emit_int8(0x17); |
2462 emit_byte(0xC0 | encode); | 2468 emit_int8((unsigned char)(0xC0 | encode)); |
2463 } | 2469 } |
2464 | 2470 |
2465 void Assembler::punpcklbw(XMMRegister dst, Address src) { | 2471 void Assembler::punpcklbw(XMMRegister dst, Address src) { |
2466 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2472 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2467 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | 2473 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2490 } | 2496 } |
2491 | 2497 |
2492 void Assembler::push(int32_t imm32) { | 2498 void Assembler::push(int32_t imm32) { |
2493 // in 64bits we push 64bits onto the stack but only | 2499 // in 64bits we push 64bits onto the stack but only |
2494 // take a 32bit immediate | 2500 // take a 32bit immediate |
2495 emit_byte(0x68); | 2501 emit_int8(0x68); |
2496 emit_long(imm32); | 2502 emit_long(imm32); |
2497 } | 2503 } |
2498 | 2504 |
2499 void Assembler::push(Register src) { | 2505 void Assembler::push(Register src) { |
2500 int encode = prefix_and_encode(src->encoding()); | 2506 int encode = prefix_and_encode(src->encoding()); |
2501 | 2507 |
2502 emit_byte(0x50 | encode); | 2508 emit_int8(0x50 | encode); |
2503 } | 2509 } |
2504 | 2510 |
2505 void Assembler::pushf() { | 2511 void Assembler::pushf() { |
2506 emit_byte(0x9C); | 2512 emit_int8((unsigned char)0x9C); |
2507 } | 2513 } |
2508 | 2514 |
2509 #ifndef _LP64 // no 32bit push/pop on amd64 | 2515 #ifndef _LP64 // no 32bit push/pop on amd64 |
2510 void Assembler::pushl(Address src) { | 2516 void Assembler::pushl(Address src) { |
2511 // Note this will push 64bit on 64bit | 2517 // Note this will push 64bit on 64bit |
2512 InstructionMark im(this); | 2518 InstructionMark im(this); |
2513 prefix(src); | 2519 prefix(src); |
2514 emit_byte(0xFF); | 2520 emit_int8((unsigned char)0xFF); |
2515 emit_operand(rsi, src); | 2521 emit_operand(rsi, src); |
2516 } | 2522 } |
2517 #endif | 2523 #endif |
2518 | 2524 |
2519 void Assembler::rcll(Register dst, int imm8) { | 2525 void Assembler::rcll(Register dst, int imm8) { |
2520 assert(isShiftCount(imm8), "illegal shift count"); | 2526 assert(isShiftCount(imm8), "illegal shift count"); |
2521 int encode = prefix_and_encode(dst->encoding()); | 2527 int encode = prefix_and_encode(dst->encoding()); |
2522 if (imm8 == 1) { | 2528 if (imm8 == 1) { |
2523 emit_byte(0xD1); | 2529 emit_int8((unsigned char)0xD1); |
2524 emit_byte(0xD0 | encode); | 2530 emit_int8((unsigned char)(0xD0 | encode)); |
2525 } else { | 2531 } else { |
2526 emit_byte(0xC1); | 2532 emit_int8((unsigned char)0xC1); |
2527 emit_byte(0xD0 | encode); | 2533 emit_int8((unsigned char)0xD0 | encode); |
2528 emit_byte(imm8); | 2534 emit_int8(imm8); |
2529 } | 2535 } |
2530 } | 2536 } |
2531 | 2537 |
2532 // copies data from [esi] to [edi] using rcx pointer sized words | 2538 // copies data from [esi] to [edi] using rcx pointer sized words |
2533 // generic | 2539 // generic |
2534 void Assembler::rep_mov() { | 2540 void Assembler::rep_mov() { |
2535 emit_byte(0xF3); | 2541 emit_int8((unsigned char)0xF3); |
2536 // MOVSQ | 2542 // MOVSQ |
2537 LP64_ONLY(prefix(REX_W)); | 2543 LP64_ONLY(prefix(REX_W)); |
2538 emit_byte(0xA5); | 2544 emit_int8((unsigned char)0xA5); |
2539 } | 2545 } |
2540 | 2546 |
2541 // sets rcx pointer sized words with rax, value at [edi] | 2547 // sets rcx pointer sized words with rax, value at [edi] |
2542 // generic | 2548 // generic |
2543 void Assembler::rep_set() { // rep_set | 2549 void Assembler::rep_set() { // rep_set |
2544 emit_byte(0xF3); | 2550 emit_int8((unsigned char)0xF3); |
2545 // STOSQ | 2551 // STOSQ |
2546 LP64_ONLY(prefix(REX_W)); | 2552 LP64_ONLY(prefix(REX_W)); |
2547 emit_byte(0xAB); | 2553 emit_int8((unsigned char)0xAB); |
2548 } | 2554 } |
2549 | 2555 |
2550 // scans rcx pointer sized words at [edi] for occurance of rax, | 2556 // scans rcx pointer sized words at [edi] for occurance of rax, |
2551 // generic | 2557 // generic |
2552 void Assembler::repne_scan() { // repne_scan | 2558 void Assembler::repne_scan() { // repne_scan |
2553 emit_byte(0xF2); | 2559 emit_int8((unsigned char)0xF2); |
2554 // SCASQ | 2560 // SCASQ |
2555 LP64_ONLY(prefix(REX_W)); | 2561 LP64_ONLY(prefix(REX_W)); |
2556 emit_byte(0xAF); | 2562 emit_int8((unsigned char)0xAF); |
2557 } | 2563 } |
2558 | 2564 |
2559 #ifdef _LP64 | 2565 #ifdef _LP64 |
2560 // scans rcx 4 byte words at [edi] for occurance of rax, | 2566 // scans rcx 4 byte words at [edi] for occurance of rax, |
2561 // generic | 2567 // generic |
2562 void Assembler::repne_scanl() { // repne_scan | 2568 void Assembler::repne_scanl() { // repne_scan |
2563 emit_byte(0xF2); | 2569 emit_int8((unsigned char)0xF2); |
2564 // SCASL | 2570 // SCASL |
2565 emit_byte(0xAF); | 2571 emit_int8((unsigned char)0xAF); |
2566 } | 2572 } |
2567 #endif | 2573 #endif |
2568 | 2574 |
2569 void Assembler::ret(int imm16) { | 2575 void Assembler::ret(int imm16) { |
2570 if (imm16 == 0) { | 2576 if (imm16 == 0) { |
2571 emit_byte(0xC3); | 2577 emit_int8((unsigned char)0xC3); |
2572 } else { | 2578 } else { |
2573 emit_byte(0xC2); | 2579 emit_int8((unsigned char)0xC2); |
2574 emit_word(imm16); | 2580 emit_int16(imm16); |
2575 } | 2581 } |
2576 } | 2582 } |
2577 | 2583 |
2578 void Assembler::sahf() { | 2584 void Assembler::sahf() { |
2579 #ifdef _LP64 | 2585 #ifdef _LP64 |
2580 // Not supported in 64bit mode | 2586 // Not supported in 64bit mode |
2581 ShouldNotReachHere(); | 2587 ShouldNotReachHere(); |
2582 #endif | 2588 #endif |
2583 emit_byte(0x9E); | 2589 emit_int8((unsigned char)0x9E); |
2584 } | 2590 } |
2585 | 2591 |
2586 void Assembler::sarl(Register dst, int imm8) { | 2592 void Assembler::sarl(Register dst, int imm8) { |
2587 int encode = prefix_and_encode(dst->encoding()); | 2593 int encode = prefix_and_encode(dst->encoding()); |
2588 assert(isShiftCount(imm8), "illegal shift count"); | 2594 assert(isShiftCount(imm8), "illegal shift count"); |
2589 if (imm8 == 1) { | 2595 if (imm8 == 1) { |
2590 emit_byte(0xD1); | 2596 emit_int8((unsigned char)0xD1); |
2591 emit_byte(0xF8 | encode); | 2597 emit_int8((unsigned char)(0xF8 | encode)); |
2592 } else { | 2598 } else { |
2593 emit_byte(0xC1); | 2599 emit_int8((unsigned char)0xC1); |
2594 emit_byte(0xF8 | encode); | 2600 emit_int8((unsigned char)(0xF8 | encode)); |
2595 emit_byte(imm8); | 2601 emit_int8(imm8); |
2596 } | 2602 } |
2597 } | 2603 } |
2598 | 2604 |
2599 void Assembler::sarl(Register dst) { | 2605 void Assembler::sarl(Register dst) { |
2600 int encode = prefix_and_encode(dst->encoding()); | 2606 int encode = prefix_and_encode(dst->encoding()); |
2601 emit_byte(0xD3); | 2607 emit_int8((unsigned char)0xD3); |
2602 emit_byte(0xF8 | encode); | 2608 emit_int8((unsigned char)(0xF8 | encode)); |
2603 } | 2609 } |
2604 | 2610 |
2605 void Assembler::sbbl(Address dst, int32_t imm32) { | 2611 void Assembler::sbbl(Address dst, int32_t imm32) { |
2606 InstructionMark im(this); | 2612 InstructionMark im(this); |
2607 prefix(dst); | 2613 prefix(dst); |
2615 | 2621 |
2616 | 2622 |
2617 void Assembler::sbbl(Register dst, Address src) { | 2623 void Assembler::sbbl(Register dst, Address src) { |
2618 InstructionMark im(this); | 2624 InstructionMark im(this); |
2619 prefix(src, dst); | 2625 prefix(src, dst); |
2620 emit_byte(0x1B); | 2626 emit_int8(0x1B); |
2621 emit_operand(dst, src); | 2627 emit_operand(dst, src); |
2622 } | 2628 } |
2623 | 2629 |
2624 void Assembler::sbbl(Register dst, Register src) { | 2630 void Assembler::sbbl(Register dst, Register src) { |
2625 (void) prefix_and_encode(dst->encoding(), src->encoding()); | 2631 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
2627 } | 2633 } |
2628 | 2634 |
2629 void Assembler::setb(Condition cc, Register dst) { | 2635 void Assembler::setb(Condition cc, Register dst) { |
2630 assert(0 <= cc && cc < 16, "illegal cc"); | 2636 assert(0 <= cc && cc < 16, "illegal cc"); |
2631 int encode = prefix_and_encode(dst->encoding(), true); | 2637 int encode = prefix_and_encode(dst->encoding(), true); |
2632 emit_byte(0x0F); | 2638 emit_int8(0x0F); |
2633 emit_byte(0x90 | cc); | 2639 emit_int8((unsigned char)0x90 | cc); |
2634 emit_byte(0xC0 | encode); | 2640 emit_int8((unsigned char)(0xC0 | encode)); |
2635 } | 2641 } |
2636 | 2642 |
2637 void Assembler::shll(Register dst, int imm8) { | 2643 void Assembler::shll(Register dst, int imm8) { |
2638 assert(isShiftCount(imm8), "illegal shift count"); | 2644 assert(isShiftCount(imm8), "illegal shift count"); |
2639 int encode = prefix_and_encode(dst->encoding()); | 2645 int encode = prefix_and_encode(dst->encoding()); |
2640 if (imm8 == 1 ) { | 2646 if (imm8 == 1 ) { |
2641 emit_byte(0xD1); | 2647 emit_int8((unsigned char)0xD1); |
2642 emit_byte(0xE0 | encode); | 2648 emit_int8((unsigned char)(0xE0 | encode)); |
2643 } else { | 2649 } else { |
2644 emit_byte(0xC1); | 2650 emit_int8((unsigned char)0xC1); |
2645 emit_byte(0xE0 | encode); | 2651 emit_int8((unsigned char)(0xE0 | encode)); |
2646 emit_byte(imm8); | 2652 emit_int8(imm8); |
2647 } | 2653 } |
2648 } | 2654 } |
2649 | 2655 |
2650 void Assembler::shll(Register dst) { | 2656 void Assembler::shll(Register dst) { |
2651 int encode = prefix_and_encode(dst->encoding()); | 2657 int encode = prefix_and_encode(dst->encoding()); |
2652 emit_byte(0xD3); | 2658 emit_int8((unsigned char)0xD3); |
2653 emit_byte(0xE0 | encode); | 2659 emit_int8((unsigned char)(0xE0 | encode)); |
2654 } | 2660 } |
2655 | 2661 |
2656 void Assembler::shrl(Register dst, int imm8) { | 2662 void Assembler::shrl(Register dst, int imm8) { |
2657 assert(isShiftCount(imm8), "illegal shift count"); | 2663 assert(isShiftCount(imm8), "illegal shift count"); |
2658 int encode = prefix_and_encode(dst->encoding()); | 2664 int encode = prefix_and_encode(dst->encoding()); |
2659 emit_byte(0xC1); | 2665 emit_int8((unsigned char)0xC1); |
2660 emit_byte(0xE8 | encode); | 2666 emit_int8((unsigned char)(0xE8 | encode)); |
2661 emit_byte(imm8); | 2667 emit_int8(imm8); |
2662 } | 2668 } |
2663 | 2669 |
2664 void Assembler::shrl(Register dst) { | 2670 void Assembler::shrl(Register dst) { |
2665 int encode = prefix_and_encode(dst->encoding()); | 2671 int encode = prefix_and_encode(dst->encoding()); |
2666 emit_byte(0xD3); | 2672 emit_int8((unsigned char)0xD3); |
2667 emit_byte(0xE8 | encode); | 2673 emit_int8((unsigned char)(0xE8 | encode)); |
2668 } | 2674 } |
2669 | 2675 |
2670 // copies a single word from [esi] to [edi] | 2676 // copies a single word from [esi] to [edi] |
2671 void Assembler::smovl() { | 2677 void Assembler::smovl() { |
2672 emit_byte(0xA5); | 2678 emit_int8((unsigned char)0xA5); |
2673 } | 2679 } |
2674 | 2680 |
2675 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { | 2681 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
2676 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2682 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2677 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); | 2683 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); |
2686 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2692 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2687 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); | 2693 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
2688 } | 2694 } |
2689 | 2695 |
2690 void Assembler::std() { | 2696 void Assembler::std() { |
2691 emit_byte(0xfd); | 2697 emit_int8((unsigned char)0xFD); |
2692 } | 2698 } |
2693 | 2699 |
2694 void Assembler::sqrtss(XMMRegister dst, Address src) { | 2700 void Assembler::sqrtss(XMMRegister dst, Address src) { |
2695 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2701 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2696 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); | 2702 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
2698 | 2704 |
2699 void Assembler::stmxcsr( Address dst) { | 2705 void Assembler::stmxcsr( Address dst) { |
2700 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2706 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2701 InstructionMark im(this); | 2707 InstructionMark im(this); |
2702 prefix(dst); | 2708 prefix(dst); |
2703 emit_byte(0x0F); | 2709 emit_int8(0x0F); |
2704 emit_byte(0xAE); | 2710 emit_int8((unsigned char)0xAE); |
2705 emit_operand(as_Register(3), dst); | 2711 emit_operand(as_Register(3), dst); |
2706 } | 2712 } |
2707 | 2713 |
2708 void Assembler::subl(Address dst, int32_t imm32) { | 2714 void Assembler::subl(Address dst, int32_t imm32) { |
2709 InstructionMark im(this); | 2715 InstructionMark im(this); |
2712 } | 2718 } |
2713 | 2719 |
2714 void Assembler::subl(Address dst, Register src) { | 2720 void Assembler::subl(Address dst, Register src) { |
2715 InstructionMark im(this); | 2721 InstructionMark im(this); |
2716 prefix(dst, src); | 2722 prefix(dst, src); |
2717 emit_byte(0x29); | 2723 emit_int8(0x29); |
2718 emit_operand(src, dst); | 2724 emit_operand(src, dst); |
2719 } | 2725 } |
2720 | 2726 |
2721 void Assembler::subl(Register dst, int32_t imm32) { | 2727 void Assembler::subl(Register dst, int32_t imm32) { |
2722 prefix(dst); | 2728 prefix(dst); |
2730 } | 2736 } |
2731 | 2737 |
2732 void Assembler::subl(Register dst, Address src) { | 2738 void Assembler::subl(Register dst, Address src) { |
2733 InstructionMark im(this); | 2739 InstructionMark im(this); |
2734 prefix(src, dst); | 2740 prefix(src, dst); |
2735 emit_byte(0x2B); | 2741 emit_int8(0x2B); |
2736 emit_operand(dst, src); | 2742 emit_operand(dst, src); |
2737 } | 2743 } |
2738 | 2744 |
2739 void Assembler::subl(Register dst, Register src) { | 2745 void Assembler::subl(Register dst, Register src) { |
2740 (void) prefix_and_encode(dst->encoding(), src->encoding()); | 2746 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
2771 // not using emit_arith because test | 2777 // not using emit_arith because test |
2772 // doesn't support sign-extension of | 2778 // doesn't support sign-extension of |
2773 // 8bit operands | 2779 // 8bit operands |
2774 int encode = dst->encoding(); | 2780 int encode = dst->encoding(); |
2775 if (encode == 0) { | 2781 if (encode == 0) { |
2776 emit_byte(0xA9); | 2782 emit_int8((unsigned char)0xA9); |
2777 } else { | 2783 } else { |
2778 encode = prefix_and_encode(encode); | 2784 encode = prefix_and_encode(encode); |
2779 emit_byte(0xF7); | 2785 emit_int8((unsigned char)0xF7); |
2780 emit_byte(0xC0 | encode); | 2786 emit_int8((unsigned char)(0xC0 | encode)); |
2781 } | 2787 } |
2782 emit_long(imm32); | 2788 emit_long(imm32); |
2783 } | 2789 } |
2784 | 2790 |
2785 void Assembler::testl(Register dst, Register src) { | 2791 void Assembler::testl(Register dst, Register src) { |
2788 } | 2794 } |
2789 | 2795 |
2790 void Assembler::testl(Register dst, Address src) { | 2796 void Assembler::testl(Register dst, Address src) { |
2791 InstructionMark im(this); | 2797 InstructionMark im(this); |
2792 prefix(src, dst); | 2798 prefix(src, dst); |
2793 emit_byte(0x85); | 2799 emit_int8((unsigned char)0x85); |
2794 emit_operand(dst, src); | 2800 emit_operand(dst, src); |
2795 } | 2801 } |
2796 | 2802 |
2797 void Assembler::ucomisd(XMMRegister dst, Address src) { | 2803 void Assembler::ucomisd(XMMRegister dst, Address src) { |
2798 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2804 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2816 | 2822 |
2817 | 2823 |
2818 void Assembler::xaddl(Address dst, Register src) { | 2824 void Assembler::xaddl(Address dst, Register src) { |
2819 InstructionMark im(this); | 2825 InstructionMark im(this); |
2820 prefix(dst, src); | 2826 prefix(dst, src); |
2821 emit_byte(0x0F); | 2827 emit_int8(0x0F); |
2822 emit_byte(0xC1); | 2828 emit_int8((unsigned char)0xC1); |
2823 emit_operand(src, dst); | 2829 emit_operand(src, dst); |
2824 } | 2830 } |
2825 | 2831 |
2826 void Assembler::xchgl(Register dst, Address src) { // xchg | 2832 void Assembler::xchgl(Register dst, Address src) { // xchg |
2827 InstructionMark im(this); | 2833 InstructionMark im(this); |
2828 prefix(src, dst); | 2834 prefix(src, dst); |
2829 emit_byte(0x87); | 2835 emit_int8((unsigned char)0x87); |
2830 emit_operand(dst, src); | 2836 emit_operand(dst, src); |
2831 } | 2837 } |
2832 | 2838 |
2833 void Assembler::xchgl(Register dst, Register src) { | 2839 void Assembler::xchgl(Register dst, Register src) { |
2834 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 2840 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
2835 emit_byte(0x87); | 2841 emit_int8((unsigned char)0x87); |
2836 emit_byte(0xc0 | encode); | 2842 emit_int8((unsigned char)(0xC0 | encode)); |
2837 } | 2843 } |
2838 | 2844 |
2839 void Assembler::xgetbv() { | 2845 void Assembler::xgetbv() { |
2840 emit_byte(0x0F); | 2846 emit_int8(0x0F); |
2841 emit_byte(0x01); | 2847 emit_int8(0x01); |
2842 emit_byte(0xD0); | 2848 emit_int8((unsigned char)0xD0); |
2843 } | 2849 } |
2844 | 2850 |
2845 void Assembler::xorl(Register dst, int32_t imm32) { | 2851 void Assembler::xorl(Register dst, int32_t imm32) { |
2846 prefix(dst); | 2852 prefix(dst); |
2847 emit_arith(0x81, 0xF0, dst, imm32); | 2853 emit_arith(0x81, 0xF0, dst, imm32); |
2848 } | 2854 } |
2849 | 2855 |
2850 void Assembler::xorl(Register dst, Address src) { | 2856 void Assembler::xorl(Register dst, Address src) { |
2851 InstructionMark im(this); | 2857 InstructionMark im(this); |
2852 prefix(src, dst); | 2858 prefix(src, dst); |
2853 emit_byte(0x33); | 2859 emit_int8(0x33); |
2854 emit_operand(dst, src); | 2860 emit_operand(dst, src); |
2855 } | 2861 } |
2856 | 2862 |
2857 void Assembler::xorl(Register dst, Register src) { | 2863 void Assembler::xorl(Register dst, Register src) { |
2858 (void) prefix_and_encode(dst->encoding(), src->encoding()); | 2864 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
3274 } | 3280 } |
3275 | 3281 |
3276 void Assembler::pmulld(XMMRegister dst, XMMRegister src) { | 3282 void Assembler::pmulld(XMMRegister dst, XMMRegister src) { |
3277 assert(VM_Version::supports_sse4_1(), ""); | 3283 assert(VM_Version::supports_sse4_1(), ""); |
3278 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 3284 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
3279 emit_byte(0x40); | 3285 emit_int8(0x40); |
3280 emit_byte(0xC0 | encode); | 3286 emit_int8((unsigned char)(0xC0 | encode)); |
3281 } | 3287 } |
3282 | 3288 |
3283 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | 3289 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
3284 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | 3290 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3285 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); | 3291 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); |
3286 } | 3292 } |
3287 | 3293 |
3288 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | 3294 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
3289 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | 3295 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3290 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); | 3296 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
3291 emit_byte(0x40); | 3297 emit_int8(0x40); |
3292 emit_byte(0xC0 | encode); | 3298 emit_int8((unsigned char)(0xC0 | encode)); |
3293 } | 3299 } |
3294 | 3300 |
3295 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | 3301 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
3296 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | 3302 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3297 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); | 3303 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); |
3301 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | 3307 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3302 InstructionMark im(this); | 3308 InstructionMark im(this); |
3303 int dst_enc = dst->encoding(); | 3309 int dst_enc = dst->encoding(); |
3304 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | 3310 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
3305 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256); | 3311 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256); |
3306 emit_byte(0x40); | 3312 emit_int8(0x40); |
3307 emit_operand(dst, src); | 3313 emit_operand(dst, src); |
3308 } | 3314 } |
3309 | 3315 |
3310 // Shift packed integers left by specified number of bits. | 3316 // Shift packed integers left by specified number of bits. |
3311 void Assembler::psllw(XMMRegister dst, int shift) { | 3317 void Assembler::psllw(XMMRegister dst, int shift) { |
3312 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 3318 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3313 // XMM6 is for /6 encoding: 66 0F 71 /6 ib | 3319 // XMM6 is for /6 encoding: 66 0F 71 /6 ib |
3314 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); | 3320 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
3315 emit_byte(0x71); | 3321 emit_int8(0x71); |
3316 emit_byte(0xC0 | encode); | 3322 emit_int8((unsigned char)(0xC0 | encode)); |
3317 emit_byte(shift & 0xFF); | 3323 emit_int8(shift & 0xFF); |
3318 } | 3324 } |
3319 | 3325 |
3320 void Assembler::pslld(XMMRegister dst, int shift) { | 3326 void Assembler::pslld(XMMRegister dst, int shift) { |
3321 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 3327 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3322 // XMM6 is for /6 encoding: 66 0F 72 /6 ib | 3328 // XMM6 is for /6 encoding: 66 0F 72 /6 ib |
3323 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); | 3329 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
3324 emit_byte(0x72); | 3330 emit_int8(0x72); |
3325 emit_byte(0xC0 | encode); | 3331 emit_int8((unsigned char)(0xC0 | encode)); |
3326 emit_byte(shift & 0xFF); | 3332 emit_int8(shift & 0xFF); |
3327 } | 3333 } |
3328 | 3334 |
3329 void Assembler::psllq(XMMRegister dst, int shift) { | 3335 void Assembler::psllq(XMMRegister dst, int shift) { |
3330 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 3336 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3331 // XMM6 is for /6 encoding: 66 0F 73 /6 ib | 3337 // XMM6 is for /6 encoding: 66 0F 73 /6 ib |
3332 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); | 3338 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
3333 emit_byte(0x73); | 3339 emit_int8(0x73); |
3334 emit_byte(0xC0 | encode); | 3340 emit_int8((unsigned char)(0xC0 | encode)); |
3335 emit_byte(shift & 0xFF); | 3341 emit_int8(shift & 0xFF); |
3336 } | 3342 } |
3337 | 3343 |
3338 void Assembler::psllw(XMMRegister dst, XMMRegister shift) { | 3344 void Assembler::psllw(XMMRegister dst, XMMRegister shift) { |
3339 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 3345 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3340 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66); | 3346 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66); |
3352 | 3358 |
3353 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | 3359 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
3354 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | 3360 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3355 // XMM6 is for /6 encoding: 66 0F 71 /6 ib | 3361 // XMM6 is for /6 encoding: 66 0F 71 /6 ib |
3356 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256); | 3362 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256); |
3357 emit_byte(shift & 0xFF); | 3363 emit_int8(shift & 0xFF); |
3358 } | 3364 } |
3359 | 3365 |
3360 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | 3366 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
3361 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | 3367 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3362 // XMM6 is for /6 encoding: 66 0F 72 /6 ib | 3368 // XMM6 is for /6 encoding: 66 0F 72 /6 ib |
3363 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256); | 3369 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256); |
3364 emit_byte(shift & 0xFF); | 3370 emit_int8(shift & 0xFF); |
3365 } | 3371 } |
3366 | 3372 |
3367 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | 3373 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
3368 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | 3374 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3369 // XMM6 is for /6 encoding: 66 0F 73 /6 ib | 3375 // XMM6 is for /6 encoding: 66 0F 73 /6 ib |
3370 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256); | 3376 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256); |
3371 emit_byte(shift & 0xFF); | 3377 emit_int8(shift & 0xFF); |
3372 } | 3378 } |
3373 | 3379 |
3374 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { | 3380 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
3375 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | 3381 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3376 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256); | 3382 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256); |
3389 // Shift packed integers logically right by specified number of bits. | 3395 // Shift packed integers logically right by specified number of bits. |
3390 void Assembler::psrlw(XMMRegister dst, int shift) { | 3396 void Assembler::psrlw(XMMRegister dst, int shift) { |
3391 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 3397 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3392 // XMM2 is for /2 encoding: 66 0F 71 /2 ib | 3398 // XMM2 is for /2 encoding: 66 0F 71 /2 ib |
3393 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); | 3399 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
3394 emit_byte(0x71); | 3400 emit_int8(0x71); |
3395 emit_byte(0xC0 | encode); | 3401 emit_int8((unsigned char)(0xC0 | encode)); |
3396 emit_byte(shift & 0xFF); | 3402 emit_int8(shift & 0xFF); |
3397 } | 3403 } |
3398 | 3404 |
3399 void Assembler::psrld(XMMRegister dst, int shift) { | 3405 void Assembler::psrld(XMMRegister dst, int shift) { |
3400 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 3406 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3401 // XMM2 is for /2 encoding: 66 0F 72 /2 ib | 3407 // XMM2 is for /2 encoding: 66 0F 72 /2 ib |
3402 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); | 3408 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
3403 emit_byte(0x72); | 3409 emit_int8(0x72); |
3404 emit_byte(0xC0 | encode); | 3410 emit_int8((unsigned char)(0xC0 | encode)); |
3405 emit_byte(shift & 0xFF); | 3411 emit_int8(shift & 0xFF); |
3406 } | 3412 } |
3407 | 3413 |
3408 void Assembler::psrlq(XMMRegister dst, int shift) { | 3414 void Assembler::psrlq(XMMRegister dst, int shift) { |
3409 // Do not confuse it with psrldq SSE2 instruction which | 3415 // Do not confuse it with psrldq SSE2 instruction which |
3410 // shifts 128 bit value in xmm register by number of bytes. | 3416 // shifts 128 bit value in xmm register by number of bytes. |
3411 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 3417 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3412 // XMM2 is for /2 encoding: 66 0F 73 /2 ib | 3418 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
3413 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); | 3419 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
3414 emit_byte(0x73); | 3420 emit_int8(0x73); |
3415 emit_byte(0xC0 | encode); | 3421 emit_int8((unsigned char)(0xC0 | encode)); |
3416 emit_byte(shift & 0xFF); | 3422 emit_int8(shift & 0xFF); |
3417 } | 3423 } |
3418 | 3424 |
3419 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { | 3425 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { |
3420 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 3426 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3421 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66); | 3427 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66); |
3433 | 3439 |
3434 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | 3440 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
3435 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | 3441 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3436 // XMM2 is for /2 encoding: 66 0F 73 /2 ib | 3442 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
3437 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256); | 3443 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256); |
3438 emit_byte(shift & 0xFF); | 3444 emit_int8(shift & 0xFF); |
3439 } | 3445 } |
3440 | 3446 |
3441 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | 3447 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
3442 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | 3448 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3443 // XMM2 is for /2 encoding: 66 0F 73 /2 ib | 3449 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
3444 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256); | 3450 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256); |
3445 emit_byte(shift & 0xFF); | 3451 emit_int8(shift & 0xFF); |
3446 } | 3452 } |
3447 | 3453 |
3448 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | 3454 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
3449 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | 3455 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3450 // XMM2 is for /2 encoding: 66 0F 73 /2 ib | 3456 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
3451 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256); | 3457 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256); |
3452 emit_byte(shift & 0xFF); | 3458 emit_int8(shift & 0xFF); |
3453 } | 3459 } |
3454 | 3460 |
3455 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { | 3461 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
3456 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | 3462 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3457 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256); | 3463 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256); |
3470 // Shift packed integers arithmetically right by specified number of bits. | 3476 // Shift packed integers arithmetically right by specified number of bits. |
3471 void Assembler::psraw(XMMRegister dst, int shift) { | 3477 void Assembler::psraw(XMMRegister dst, int shift) { |
3472 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 3478 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3473 // XMM4 is for /4 encoding: 66 0F 71 /4 ib | 3479 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
3474 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); | 3480 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); |
3475 emit_byte(0x71); | 3481 emit_int8(0x71); |
3476 emit_byte(0xC0 | encode); | 3482 emit_int8((unsigned char)(0xC0 | encode)); |
3477 emit_byte(shift & 0xFF); | 3483 emit_int8(shift & 0xFF); |
3478 } | 3484 } |
3479 | 3485 |
3480 void Assembler::psrad(XMMRegister dst, int shift) { | 3486 void Assembler::psrad(XMMRegister dst, int shift) { |
3481 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 3487 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3482 // XMM4 is for /4 encoding: 66 0F 72 /4 ib | 3488 // XMM4 is for /4 encoding: 66 0F 72 /4 ib |
3483 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); | 3489 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); |
3484 emit_byte(0x72); | 3490 emit_int8(0x72); |
3485 emit_byte(0xC0 | encode); | 3491 emit_int8((unsigned char)(0xC0 | encode)); |
3486 emit_byte(shift & 0xFF); | 3492 emit_int8(shift & 0xFF); |
3487 } | 3493 } |
3488 | 3494 |
3489 void Assembler::psraw(XMMRegister dst, XMMRegister shift) { | 3495 void Assembler::psraw(XMMRegister dst, XMMRegister shift) { |
3490 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 3496 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3491 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66); | 3497 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66); |
3498 | 3504 |
3499 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | 3505 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
3500 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | 3506 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3501 // XMM4 is for /4 encoding: 66 0F 71 /4 ib | 3507 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
3502 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256); | 3508 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256); |
3503 emit_byte(shift & 0xFF); | 3509 emit_int8(shift & 0xFF); |
3504 } | 3510 } |
3505 | 3511 |
3506 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | 3512 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
3507 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | 3513 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3508 // XMM4 is for /4 encoding: 66 0F 71 /4 ib | 3514 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
3509 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256); | 3515 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256); |
3510 emit_byte(shift & 0xFF); | 3516 emit_int8(shift & 0xFF); |
3511 } | 3517 } |
3512 | 3518 |
3513 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { | 3519 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
3514 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | 3520 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3515 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256); | 3521 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256); |
3570 | 3576 |
3571 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { | 3577 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
3572 assert(VM_Version::supports_avx(), ""); | 3578 assert(VM_Version::supports_avx(), ""); |
3573 bool vector256 = true; | 3579 bool vector256 = true; |
3574 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); | 3580 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); |
3575 emit_byte(0x18); | 3581 emit_int8(0x18); |
3576 emit_byte(0xC0 | encode); | 3582 emit_int8((unsigned char)(0xC0 | encode)); |
3577 // 0x00 - insert into lower 128 bits | 3583 // 0x00 - insert into lower 128 bits |
3578 // 0x01 - insert into upper 128 bits | 3584 // 0x01 - insert into upper 128 bits |
3579 emit_byte(0x01); | 3585 emit_int8(0x01); |
3580 } | 3586 } |
3581 | 3587 |
3582 void Assembler::vinsertf128h(XMMRegister dst, Address src) { | 3588 void Assembler::vinsertf128h(XMMRegister dst, Address src) { |
3583 assert(VM_Version::supports_avx(), ""); | 3589 assert(VM_Version::supports_avx(), ""); |
3584 InstructionMark im(this); | 3590 InstructionMark im(this); |
3585 bool vector256 = true; | 3591 bool vector256 = true; |
3586 assert(dst != xnoreg, "sanity"); | 3592 assert(dst != xnoreg, "sanity"); |
3587 int dst_enc = dst->encoding(); | 3593 int dst_enc = dst->encoding(); |
3588 // swap src<->dst for encoding | 3594 // swap src<->dst for encoding |
3589 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); | 3595 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
3590 emit_byte(0x18); | 3596 emit_int8(0x18); |
3591 emit_operand(dst, src); | 3597 emit_operand(dst, src); |
3592 // 0x01 - insert into upper 128 bits | 3598 // 0x01 - insert into upper 128 bits |
3593 emit_byte(0x01); | 3599 emit_int8(0x01); |
3594 } | 3600 } |
3595 | 3601 |
3596 void Assembler::vextractf128h(Address dst, XMMRegister src) { | 3602 void Assembler::vextractf128h(Address dst, XMMRegister src) { |
3597 assert(VM_Version::supports_avx(), ""); | 3603 assert(VM_Version::supports_avx(), ""); |
3598 InstructionMark im(this); | 3604 InstructionMark im(this); |
3599 bool vector256 = true; | 3605 bool vector256 = true; |
3600 assert(src != xnoreg, "sanity"); | 3606 assert(src != xnoreg, "sanity"); |
3601 int src_enc = src->encoding(); | 3607 int src_enc = src->encoding(); |
3602 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); | 3608 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
3603 emit_byte(0x19); | 3609 emit_int8(0x19); |
3604 emit_operand(src, dst); | 3610 emit_operand(src, dst); |
3605 // 0x01 - extract from upper 128 bits | 3611 // 0x01 - extract from upper 128 bits |
3606 emit_byte(0x01); | 3612 emit_int8(0x01); |
3607 } | 3613 } |
3608 | 3614 |
3609 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { | 3615 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
3610 assert(VM_Version::supports_avx2(), ""); | 3616 assert(VM_Version::supports_avx2(), ""); |
3611 bool vector256 = true; | 3617 bool vector256 = true; |
3612 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); | 3618 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); |
3613 emit_byte(0x38); | 3619 emit_int8(0x38); |
3614 emit_byte(0xC0 | encode); | 3620 emit_int8((unsigned char)(0xC0 | encode)); |
3615 // 0x00 - insert into lower 128 bits | 3621 // 0x00 - insert into lower 128 bits |
3616 // 0x01 - insert into upper 128 bits | 3622 // 0x01 - insert into upper 128 bits |
3617 emit_byte(0x01); | 3623 emit_int8(0x01); |
3618 } | 3624 } |
3619 | 3625 |
3620 void Assembler::vinserti128h(XMMRegister dst, Address src) { | 3626 void Assembler::vinserti128h(XMMRegister dst, Address src) { |
3621 assert(VM_Version::supports_avx2(), ""); | 3627 assert(VM_Version::supports_avx2(), ""); |
3622 InstructionMark im(this); | 3628 InstructionMark im(this); |
3623 bool vector256 = true; | 3629 bool vector256 = true; |
3624 assert(dst != xnoreg, "sanity"); | 3630 assert(dst != xnoreg, "sanity"); |
3625 int dst_enc = dst->encoding(); | 3631 int dst_enc = dst->encoding(); |
3626 // swap src<->dst for encoding | 3632 // swap src<->dst for encoding |
3627 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); | 3633 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
3628 emit_byte(0x38); | 3634 emit_int8(0x38); |
3629 emit_operand(dst, src); | 3635 emit_operand(dst, src); |
3630 // 0x01 - insert into upper 128 bits | 3636 // 0x01 - insert into upper 128 bits |
3631 emit_byte(0x01); | 3637 emit_int8(0x01); |
3632 } | 3638 } |
3633 | 3639 |
3634 void Assembler::vextracti128h(Address dst, XMMRegister src) { | 3640 void Assembler::vextracti128h(Address dst, XMMRegister src) { |
3635 assert(VM_Version::supports_avx2(), ""); | 3641 assert(VM_Version::supports_avx2(), ""); |
3636 InstructionMark im(this); | 3642 InstructionMark im(this); |
3637 bool vector256 = true; | 3643 bool vector256 = true; |
3638 assert(src != xnoreg, "sanity"); | 3644 assert(src != xnoreg, "sanity"); |
3639 int src_enc = src->encoding(); | 3645 int src_enc = src->encoding(); |
3640 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); | 3646 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
3641 emit_byte(0x39); | 3647 emit_int8(0x39); |
3642 emit_operand(src, dst); | 3648 emit_operand(src, dst); |
3643 // 0x01 - extract from upper 128 bits | 3649 // 0x01 - extract from upper 128 bits |
3644 emit_byte(0x01); | 3650 emit_int8(0x01); |
3645 } | 3651 } |
3646 | 3652 |
3647 void Assembler::vzeroupper() { | 3653 void Assembler::vzeroupper() { |
3648 assert(VM_Version::supports_avx(), ""); | 3654 assert(VM_Version::supports_avx(), ""); |
3649 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE); | 3655 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE); |
3650 emit_byte(0x77); | 3656 emit_int8(0x77); |
3651 } | 3657 } |
3652 | 3658 |
3653 | 3659 |
3654 #ifndef _LP64 | 3660 #ifndef _LP64 |
3655 // 32bit only pieces of the assembler | 3661 // 32bit only pieces of the assembler |
3656 | 3662 |
3657 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | 3663 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
3658 // NO PREFIX AS NEVER 64BIT | 3664 // NO PREFIX AS NEVER 64BIT |
3659 InstructionMark im(this); | 3665 InstructionMark im(this); |
3660 emit_byte(0x81); | 3666 emit_int8((unsigned char)0x81); |
3661 emit_byte(0xF8 | src1->encoding()); | 3667 emit_int8((unsigned char)(0xF8 | src1->encoding())); |
3662 emit_data(imm32, rspec, 0); | 3668 emit_data(imm32, rspec, 0); |
3663 } | 3669 } |
3664 | 3670 |
3665 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | 3671 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
3666 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | 3672 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs |
3667 InstructionMark im(this); | 3673 InstructionMark im(this); |
3668 emit_byte(0x81); | 3674 emit_int8((unsigned char)0x81); |
3669 emit_operand(rdi, src1); | 3675 emit_operand(rdi, src1); |
3670 emit_data(imm32, rspec, 0); | 3676 emit_data(imm32, rspec, 0); |
3671 } | 3677 } |
3672 | 3678 |
3673 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | 3679 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, |
3674 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | 3680 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded |
3675 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | 3681 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. |
3676 void Assembler::cmpxchg8(Address adr) { | 3682 void Assembler::cmpxchg8(Address adr) { |
3677 InstructionMark im(this); | 3683 InstructionMark im(this); |
3678 emit_byte(0x0F); | 3684 emit_int8(0x0F); |
3679 emit_byte(0xc7); | 3685 emit_int8((unsigned char)0xC7); |
3680 emit_operand(rcx, adr); | 3686 emit_operand(rcx, adr); |
3681 } | 3687 } |
3682 | 3688 |
3683 void Assembler::decl(Register dst) { | 3689 void Assembler::decl(Register dst) { |
3684 // Don't use it directly. Use MacroAssembler::decrementl() instead. | 3690 // Don't use it directly. Use MacroAssembler::decrementl() instead. |
3685 emit_byte(0x48 | dst->encoding()); | 3691 emit_int8(0x48 | dst->encoding()); |
3686 } | 3692 } |
3687 | 3693 |
3688 #endif // _LP64 | 3694 #endif // _LP64 |
3689 | 3695 |
3690 // 64bit typically doesn't use the x87 but needs to for the trig funcs | 3696 // 64bit typically doesn't use the x87 but needs to for the trig funcs |
3691 | 3697 |
3692 void Assembler::fabs() { | 3698 void Assembler::fabs() { |
3693 emit_byte(0xD9); | 3699 emit_int8((unsigned char)0xD9); |
3694 emit_byte(0xE1); | 3700 emit_int8((unsigned char)0xE1); |
3695 } | 3701 } |
3696 | 3702 |
3697 void Assembler::fadd(int i) { | 3703 void Assembler::fadd(int i) { |
3698 emit_farith(0xD8, 0xC0, i); | 3704 emit_farith(0xD8, 0xC0, i); |
3699 } | 3705 } |
3700 | 3706 |
3701 void Assembler::fadd_d(Address src) { | 3707 void Assembler::fadd_d(Address src) { |
3702 InstructionMark im(this); | 3708 InstructionMark im(this); |
3703 emit_byte(0xDC); | 3709 emit_int8((unsigned char)0xDC); |
3704 emit_operand32(rax, src); | 3710 emit_operand32(rax, src); |
3705 } | 3711 } |
3706 | 3712 |
3707 void Assembler::fadd_s(Address src) { | 3713 void Assembler::fadd_s(Address src) { |
3708 InstructionMark im(this); | 3714 InstructionMark im(this); |
3709 emit_byte(0xD8); | 3715 emit_int8((unsigned char)0xD8); |
3710 emit_operand32(rax, src); | 3716 emit_operand32(rax, src); |
3711 } | 3717 } |
3712 | 3718 |
3713 void Assembler::fadda(int i) { | 3719 void Assembler::fadda(int i) { |
3714 emit_farith(0xDC, 0xC0, i); | 3720 emit_farith(0xDC, 0xC0, i); |
3717 void Assembler::faddp(int i) { | 3723 void Assembler::faddp(int i) { |
3718 emit_farith(0xDE, 0xC0, i); | 3724 emit_farith(0xDE, 0xC0, i); |
3719 } | 3725 } |
3720 | 3726 |
3721 void Assembler::fchs() { | 3727 void Assembler::fchs() { |
3722 emit_byte(0xD9); | 3728 emit_int8((unsigned char)0xD9); |
3723 emit_byte(0xE0); | 3729 emit_int8((unsigned char)0xE0); |
3724 } | 3730 } |
3725 | 3731 |
3726 void Assembler::fcom(int i) { | 3732 void Assembler::fcom(int i) { |
3727 emit_farith(0xD8, 0xD0, i); | 3733 emit_farith(0xD8, 0xD0, i); |
3728 } | 3734 } |
3731 emit_farith(0xD8, 0xD8, i); | 3737 emit_farith(0xD8, 0xD8, i); |
3732 } | 3738 } |
3733 | 3739 |
3734 void Assembler::fcomp_d(Address src) { | 3740 void Assembler::fcomp_d(Address src) { |
3735 InstructionMark im(this); | 3741 InstructionMark im(this); |
3736 emit_byte(0xDC); | 3742 emit_int8((unsigned char)0xDC); |
3737 emit_operand32(rbx, src); | 3743 emit_operand32(rbx, src); |
3738 } | 3744 } |
3739 | 3745 |
3740 void Assembler::fcomp_s(Address src) { | 3746 void Assembler::fcomp_s(Address src) { |
3741 InstructionMark im(this); | 3747 InstructionMark im(this); |
3742 emit_byte(0xD8); | 3748 emit_int8((unsigned char)0xD8); |
3743 emit_operand32(rbx, src); | 3749 emit_operand32(rbx, src); |
3744 } | 3750 } |
3745 | 3751 |
3746 void Assembler::fcompp() { | 3752 void Assembler::fcompp() { |
3747 emit_byte(0xDE); | 3753 emit_int8((unsigned char)0xDE); |
3748 emit_byte(0xD9); | 3754 emit_int8((unsigned char)0xD9); |
3749 } | 3755 } |
3750 | 3756 |
3751 void Assembler::fcos() { | 3757 void Assembler::fcos() { |
3752 emit_byte(0xD9); | 3758 emit_int8((unsigned char)0xD9); |
3753 emit_byte(0xFF); | 3759 emit_int8((unsigned char)0xFF); |
3754 } | 3760 } |
3755 | 3761 |
3756 void Assembler::fdecstp() { | 3762 void Assembler::fdecstp() { |
3757 emit_byte(0xD9); | 3763 emit_int8((unsigned char)0xD9); |
3758 emit_byte(0xF6); | 3764 emit_int8((unsigned char)0xF6); |
3759 } | 3765 } |
3760 | 3766 |
3761 void Assembler::fdiv(int i) { | 3767 void Assembler::fdiv(int i) { |
3762 emit_farith(0xD8, 0xF0, i); | 3768 emit_farith(0xD8, 0xF0, i); |
3763 } | 3769 } |
3764 | 3770 |
3765 void Assembler::fdiv_d(Address src) { | 3771 void Assembler::fdiv_d(Address src) { |
3766 InstructionMark im(this); | 3772 InstructionMark im(this); |
3767 emit_byte(0xDC); | 3773 emit_int8((unsigned char)0xDC); |
3768 emit_operand32(rsi, src); | 3774 emit_operand32(rsi, src); |
3769 } | 3775 } |
3770 | 3776 |
3771 void Assembler::fdiv_s(Address src) { | 3777 void Assembler::fdiv_s(Address src) { |
3772 InstructionMark im(this); | 3778 InstructionMark im(this); |
3773 emit_byte(0xD8); | 3779 emit_int8((unsigned char)0xD8); |
3774 emit_operand32(rsi, src); | 3780 emit_operand32(rsi, src); |
3775 } | 3781 } |
3776 | 3782 |
3777 void Assembler::fdiva(int i) { | 3783 void Assembler::fdiva(int i) { |
3778 emit_farith(0xDC, 0xF8, i); | 3784 emit_farith(0xDC, 0xF8, i); |
3789 emit_farith(0xD8, 0xF8, i); | 3795 emit_farith(0xD8, 0xF8, i); |
3790 } | 3796 } |
3791 | 3797 |
3792 void Assembler::fdivr_d(Address src) { | 3798 void Assembler::fdivr_d(Address src) { |
3793 InstructionMark im(this); | 3799 InstructionMark im(this); |
3794 emit_byte(0xDC); | 3800 emit_int8((unsigned char)0xDC); |
3795 emit_operand32(rdi, src); | 3801 emit_operand32(rdi, src); |
3796 } | 3802 } |
3797 | 3803 |
3798 void Assembler::fdivr_s(Address src) { | 3804 void Assembler::fdivr_s(Address src) { |
3799 InstructionMark im(this); | 3805 InstructionMark im(this); |
3800 emit_byte(0xD8); | 3806 emit_int8((unsigned char)0xD8); |
3801 emit_operand32(rdi, src); | 3807 emit_operand32(rdi, src); |
3802 } | 3808 } |
3803 | 3809 |
3804 void Assembler::fdivra(int i) { | 3810 void Assembler::fdivra(int i) { |
3805 emit_farith(0xDC, 0xF0, i); | 3811 emit_farith(0xDC, 0xF0, i); |
3813 emit_farith(0xDD, 0xC0, i); | 3819 emit_farith(0xDD, 0xC0, i); |
3814 } | 3820 } |
3815 | 3821 |
3816 void Assembler::fild_d(Address adr) { | 3822 void Assembler::fild_d(Address adr) { |
3817 InstructionMark im(this); | 3823 InstructionMark im(this); |
3818 emit_byte(0xDF); | 3824 emit_int8((unsigned char)0xDF); |
3819 emit_operand32(rbp, adr); | 3825 emit_operand32(rbp, adr); |
3820 } | 3826 } |
3821 | 3827 |
3822 void Assembler::fild_s(Address adr) { | 3828 void Assembler::fild_s(Address adr) { |
3823 InstructionMark im(this); | 3829 InstructionMark im(this); |
3824 emit_byte(0xDB); | 3830 emit_int8((unsigned char)0xDB); |
3825 emit_operand32(rax, adr); | 3831 emit_operand32(rax, adr); |
3826 } | 3832 } |
3827 | 3833 |
3828 void Assembler::fincstp() { | 3834 void Assembler::fincstp() { |
3829 emit_byte(0xD9); | 3835 emit_int8((unsigned char)0xD9); |
3830 emit_byte(0xF7); | 3836 emit_int8((unsigned char)0xF7); |
3831 } | 3837 } |
3832 | 3838 |
3833 void Assembler::finit() { | 3839 void Assembler::finit() { |
3834 emit_byte(0x9B); | 3840 emit_int8((unsigned char)0x9B); |
3835 emit_byte(0xDB); | 3841 emit_int8((unsigned char)0xDB); |
3836 emit_byte(0xE3); | 3842 emit_int8((unsigned char)0xE3); |
3837 } | 3843 } |
3838 | 3844 |
3839 void Assembler::fist_s(Address adr) { | 3845 void Assembler::fist_s(Address adr) { |
3840 InstructionMark im(this); | 3846 InstructionMark im(this); |
3841 emit_byte(0xDB); | 3847 emit_int8((unsigned char)0xDB); |
3842 emit_operand32(rdx, adr); | 3848 emit_operand32(rdx, adr); |
3843 } | 3849 } |
3844 | 3850 |
3845 void Assembler::fistp_d(Address adr) { | 3851 void Assembler::fistp_d(Address adr) { |
3846 InstructionMark im(this); | 3852 InstructionMark im(this); |
3847 emit_byte(0xDF); | 3853 emit_int8((unsigned char)0xDF); |
3848 emit_operand32(rdi, adr); | 3854 emit_operand32(rdi, adr); |
3849 } | 3855 } |
3850 | 3856 |
3851 void Assembler::fistp_s(Address adr) { | 3857 void Assembler::fistp_s(Address adr) { |
3852 InstructionMark im(this); | 3858 InstructionMark im(this); |
3853 emit_byte(0xDB); | 3859 emit_int8((unsigned char)0xDB); |
3854 emit_operand32(rbx, adr); | 3860 emit_operand32(rbx, adr); |
3855 } | 3861 } |
3856 | 3862 |
3857 void Assembler::fld1() { | 3863 void Assembler::fld1() { |
3858 emit_byte(0xD9); | 3864 emit_int8((unsigned char)0xD9); |
3859 emit_byte(0xE8); | 3865 emit_int8((unsigned char)0xE8); |
3860 } | 3866 } |
3861 | 3867 |
3862 void Assembler::fld_d(Address adr) { | 3868 void Assembler::fld_d(Address adr) { |
3863 InstructionMark im(this); | 3869 InstructionMark im(this); |
3864 emit_byte(0xDD); | 3870 emit_int8((unsigned char)0xDD); |
3865 emit_operand32(rax, adr); | 3871 emit_operand32(rax, adr); |
3866 } | 3872 } |
3867 | 3873 |
3868 void Assembler::fld_s(Address adr) { | 3874 void Assembler::fld_s(Address adr) { |
3869 InstructionMark im(this); | 3875 InstructionMark im(this); |
3870 emit_byte(0xD9); | 3876 emit_int8((unsigned char)0xD9); |
3871 emit_operand32(rax, adr); | 3877 emit_operand32(rax, adr); |
3872 } | 3878 } |
3873 | 3879 |
3874 | 3880 |
3875 void Assembler::fld_s(int index) { | 3881 void Assembler::fld_s(int index) { |
3876 emit_farith(0xD9, 0xC0, index); | 3882 emit_farith(0xD9, 0xC0, index); |
3877 } | 3883 } |
3878 | 3884 |
3879 void Assembler::fld_x(Address adr) { | 3885 void Assembler::fld_x(Address adr) { |
3880 InstructionMark im(this); | 3886 InstructionMark im(this); |
3881 emit_byte(0xDB); | 3887 emit_int8((unsigned char)0xDB); |
3882 emit_operand32(rbp, adr); | 3888 emit_operand32(rbp, adr); |
3883 } | 3889 } |
3884 | 3890 |
3885 void Assembler::fldcw(Address src) { | 3891 void Assembler::fldcw(Address src) { |
3886 InstructionMark im(this); | 3892 InstructionMark im(this); |
3887 emit_byte(0xd9); | 3893 emit_int8((unsigned char)0xD9); |
3888 emit_operand32(rbp, src); | 3894 emit_operand32(rbp, src); |
3889 } | 3895 } |
3890 | 3896 |
3891 void Assembler::fldenv(Address src) { | 3897 void Assembler::fldenv(Address src) { |
3892 InstructionMark im(this); | 3898 InstructionMark im(this); |
3893 emit_byte(0xD9); | 3899 emit_int8((unsigned char)0xD9); |
3894 emit_operand32(rsp, src); | 3900 emit_operand32(rsp, src); |
3895 } | 3901 } |
3896 | 3902 |
3897 void Assembler::fldlg2() { | 3903 void Assembler::fldlg2() { |
3898 emit_byte(0xD9); | 3904 emit_int8((unsigned char)0xD9); |
3899 emit_byte(0xEC); | 3905 emit_int8((unsigned char)0xEC); |
3900 } | 3906 } |
3901 | 3907 |
3902 void Assembler::fldln2() { | 3908 void Assembler::fldln2() { |
3903 emit_byte(0xD9); | 3909 emit_int8((unsigned char)0xD9); |
3904 emit_byte(0xED); | 3910 emit_int8((unsigned char)0xED); |
3905 } | 3911 } |
3906 | 3912 |
3907 void Assembler::fldz() { | 3913 void Assembler::fldz() { |
3908 emit_byte(0xD9); | 3914 emit_int8((unsigned char)0xD9); |
3909 emit_byte(0xEE); | 3915 emit_int8((unsigned char)0xEE); |
3910 } | 3916 } |
3911 | 3917 |
3912 void Assembler::flog() { | 3918 void Assembler::flog() { |
3913 fldln2(); | 3919 fldln2(); |
3914 fxch(); | 3920 fxch(); |
3925 emit_farith(0xD8, 0xC8, i); | 3931 emit_farith(0xD8, 0xC8, i); |
3926 } | 3932 } |
3927 | 3933 |
3928 void Assembler::fmul_d(Address src) { | 3934 void Assembler::fmul_d(Address src) { |
3929 InstructionMark im(this); | 3935 InstructionMark im(this); |
3930 emit_byte(0xDC); | 3936 emit_int8((unsigned char)0xDC); |
3931 emit_operand32(rcx, src); | 3937 emit_operand32(rcx, src); |
3932 } | 3938 } |
3933 | 3939 |
3934 void Assembler::fmul_s(Address src) { | 3940 void Assembler::fmul_s(Address src) { |
3935 InstructionMark im(this); | 3941 InstructionMark im(this); |
3936 emit_byte(0xD8); | 3942 emit_int8((unsigned char)0xD8); |
3937 emit_operand32(rcx, src); | 3943 emit_operand32(rcx, src); |
3938 } | 3944 } |
3939 | 3945 |
3940 void Assembler::fmula(int i) { | 3946 void Assembler::fmula(int i) { |
3941 emit_farith(0xDC, 0xC8, i); | 3947 emit_farith(0xDC, 0xC8, i); |
3945 emit_farith(0xDE, 0xC8, i); | 3951 emit_farith(0xDE, 0xC8, i); |
3946 } | 3952 } |
3947 | 3953 |
3948 void Assembler::fnsave(Address dst) { | 3954 void Assembler::fnsave(Address dst) { |
3949 InstructionMark im(this); | 3955 InstructionMark im(this); |
3950 emit_byte(0xDD); | 3956 emit_int8((unsigned char)0xDD); |
3951 emit_operand32(rsi, dst); | 3957 emit_operand32(rsi, dst); |
3952 } | 3958 } |
3953 | 3959 |
3954 void Assembler::fnstcw(Address src) { | 3960 void Assembler::fnstcw(Address src) { |
3955 InstructionMark im(this); | 3961 InstructionMark im(this); |
3956 emit_byte(0x9B); | 3962 emit_int8((unsigned char)0x9B); |
3957 emit_byte(0xD9); | 3963 emit_int8((unsigned char)0xD9); |
3958 emit_operand32(rdi, src); | 3964 emit_operand32(rdi, src); |
3959 } | 3965 } |
3960 | 3966 |
3961 void Assembler::fnstsw_ax() { | 3967 void Assembler::fnstsw_ax() { |
3962 emit_byte(0xdF); | 3968 emit_int8((unsigned char)0xDF); |
3963 emit_byte(0xE0); | 3969 emit_int8((unsigned char)0xE0); |
3964 } | 3970 } |
3965 | 3971 |
3966 void Assembler::fprem() { | 3972 void Assembler::fprem() { |
3967 emit_byte(0xD9); | 3973 emit_int8((unsigned char)0xD9); |
3968 emit_byte(0xF8); | 3974 emit_int8((unsigned char)0xF8); |
3969 } | 3975 } |
3970 | 3976 |
3971 void Assembler::fprem1() { | 3977 void Assembler::fprem1() { |
3972 emit_byte(0xD9); | 3978 emit_int8((unsigned char)0xD9); |
3973 emit_byte(0xF5); | 3979 emit_int8((unsigned char)0xF5); |
3974 } | 3980 } |
3975 | 3981 |
3976 void Assembler::frstor(Address src) { | 3982 void Assembler::frstor(Address src) { |
3977 InstructionMark im(this); | 3983 InstructionMark im(this); |
3978 emit_byte(0xDD); | 3984 emit_int8((unsigned char)0xDD); |
3979 emit_operand32(rsp, src); | 3985 emit_operand32(rsp, src); |
3980 } | 3986 } |
3981 | 3987 |
3982 void Assembler::fsin() { | 3988 void Assembler::fsin() { |
3983 emit_byte(0xD9); | 3989 emit_int8((unsigned char)0xD9); |
3984 emit_byte(0xFE); | 3990 emit_int8((unsigned char)0xFE); |
3985 } | 3991 } |
3986 | 3992 |
3987 void Assembler::fsqrt() { | 3993 void Assembler::fsqrt() { |
3988 emit_byte(0xD9); | 3994 emit_int8((unsigned char)0xD9); |
3989 emit_byte(0xFA); | 3995 emit_int8((unsigned char)0xFA); |
3990 } | 3996 } |
3991 | 3997 |
3992 void Assembler::fst_d(Address adr) { | 3998 void Assembler::fst_d(Address adr) { |
3993 InstructionMark im(this); | 3999 InstructionMark im(this); |
3994 emit_byte(0xDD); | 4000 emit_int8((unsigned char)0xDD); |
3995 emit_operand32(rdx, adr); | 4001 emit_operand32(rdx, adr); |
3996 } | 4002 } |
3997 | 4003 |
3998 void Assembler::fst_s(Address adr) { | 4004 void Assembler::fst_s(Address adr) { |
3999 InstructionMark im(this); | 4005 InstructionMark im(this); |
4000 emit_byte(0xD9); | 4006 emit_int8((unsigned char)0xD9); |
4001 emit_operand32(rdx, adr); | 4007 emit_operand32(rdx, adr); |
4002 } | 4008 } |
4003 | 4009 |
4004 void Assembler::fstp_d(Address adr) { | 4010 void Assembler::fstp_d(Address adr) { |
4005 InstructionMark im(this); | 4011 InstructionMark im(this); |
4006 emit_byte(0xDD); | 4012 emit_int8((unsigned char)0xDD); |
4007 emit_operand32(rbx, adr); | 4013 emit_operand32(rbx, adr); |
4008 } | 4014 } |
4009 | 4015 |
4010 void Assembler::fstp_d(int index) { | 4016 void Assembler::fstp_d(int index) { |
4011 emit_farith(0xDD, 0xD8, index); | 4017 emit_farith(0xDD, 0xD8, index); |
4012 } | 4018 } |
4013 | 4019 |
4014 void Assembler::fstp_s(Address adr) { | 4020 void Assembler::fstp_s(Address adr) { |
4015 InstructionMark im(this); | 4021 InstructionMark im(this); |
4016 emit_byte(0xD9); | 4022 emit_int8((unsigned char)0xD9); |
4017 emit_operand32(rbx, adr); | 4023 emit_operand32(rbx, adr); |
4018 } | 4024 } |
4019 | 4025 |
4020 void Assembler::fstp_x(Address adr) { | 4026 void Assembler::fstp_x(Address adr) { |
4021 InstructionMark im(this); | 4027 InstructionMark im(this); |
4022 emit_byte(0xDB); | 4028 emit_int8((unsigned char)0xDB); |
4023 emit_operand32(rdi, adr); | 4029 emit_operand32(rdi, adr); |
4024 } | 4030 } |
4025 | 4031 |
4026 void Assembler::fsub(int i) { | 4032 void Assembler::fsub(int i) { |
4027 emit_farith(0xD8, 0xE0, i); | 4033 emit_farith(0xD8, 0xE0, i); |
4028 } | 4034 } |
4029 | 4035 |
4030 void Assembler::fsub_d(Address src) { | 4036 void Assembler::fsub_d(Address src) { |
4031 InstructionMark im(this); | 4037 InstructionMark im(this); |
4032 emit_byte(0xDC); | 4038 emit_int8((unsigned char)0xDC); |
4033 emit_operand32(rsp, src); | 4039 emit_operand32(rsp, src); |
4034 } | 4040 } |
4035 | 4041 |
4036 void Assembler::fsub_s(Address src) { | 4042 void Assembler::fsub_s(Address src) { |
4037 InstructionMark im(this); | 4043 InstructionMark im(this); |
4038 emit_byte(0xD8); | 4044 emit_int8((unsigned char)0xD8); |
4039 emit_operand32(rsp, src); | 4045 emit_operand32(rsp, src); |
4040 } | 4046 } |
4041 | 4047 |
4042 void Assembler::fsuba(int i) { | 4048 void Assembler::fsuba(int i) { |
4043 emit_farith(0xDC, 0xE8, i); | 4049 emit_farith(0xDC, 0xE8, i); |
4051 emit_farith(0xD8, 0xE8, i); | 4057 emit_farith(0xD8, 0xE8, i); |
4052 } | 4058 } |
4053 | 4059 |
4054 void Assembler::fsubr_d(Address src) { | 4060 void Assembler::fsubr_d(Address src) { |
4055 InstructionMark im(this); | 4061 InstructionMark im(this); |
4056 emit_byte(0xDC); | 4062 emit_int8((unsigned char)0xDC); |
4057 emit_operand32(rbp, src); | 4063 emit_operand32(rbp, src); |
4058 } | 4064 } |
4059 | 4065 |
4060 void Assembler::fsubr_s(Address src) { | 4066 void Assembler::fsubr_s(Address src) { |
4061 InstructionMark im(this); | 4067 InstructionMark im(this); |
4062 emit_byte(0xD8); | 4068 emit_int8((unsigned char)0xD8); |
4063 emit_operand32(rbp, src); | 4069 emit_operand32(rbp, src); |
4064 } | 4070 } |
4065 | 4071 |
4066 void Assembler::fsubra(int i) { | 4072 void Assembler::fsubra(int i) { |
4067 emit_farith(0xDC, 0xE0, i); | 4073 emit_farith(0xDC, 0xE0, i); |
4070 void Assembler::fsubrp(int i) { | 4076 void Assembler::fsubrp(int i) { |
4071 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | 4077 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) |
4072 } | 4078 } |
4073 | 4079 |
4074 void Assembler::ftan() { | 4080 void Assembler::ftan() { |
4075 emit_byte(0xD9); | 4081 emit_int8((unsigned char)0xD9); |
4076 emit_byte(0xF2); | 4082 emit_int8((unsigned char)0xF2); |
4077 emit_byte(0xDD); | 4083 emit_int8((unsigned char)0xDD); |
4078 emit_byte(0xD8); | 4084 emit_int8((unsigned char)0xD8); |
4079 } | 4085 } |
4080 | 4086 |
4081 void Assembler::ftst() { | 4087 void Assembler::ftst() { |
4082 emit_byte(0xD9); | 4088 emit_int8((unsigned char)0xD9); |
4083 emit_byte(0xE4); | 4089 emit_int8((unsigned char)0xE4); |
4084 } | 4090 } |
4085 | 4091 |
4086 void Assembler::fucomi(int i) { | 4092 void Assembler::fucomi(int i) { |
4087 // make sure the instruction is supported (introduced for P6, together with cmov) | 4093 // make sure the instruction is supported (introduced for P6, together with cmov) |
4088 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | 4094 guarantee(VM_Version::supports_cmov(), "illegal instruction"); |
4094 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | 4100 guarantee(VM_Version::supports_cmov(), "illegal instruction"); |
4095 emit_farith(0xDF, 0xE8, i); | 4101 emit_farith(0xDF, 0xE8, i); |
4096 } | 4102 } |
4097 | 4103 |
4098 void Assembler::fwait() { | 4104 void Assembler::fwait() { |
4099 emit_byte(0x9B); | 4105 emit_int8((unsigned char)0x9B); |
4100 } | 4106 } |
4101 | 4107 |
4102 void Assembler::fxch(int i) { | 4108 void Assembler::fxch(int i) { |
4103 emit_farith(0xD9, 0xC8, i); | 4109 emit_farith(0xD9, 0xC8, i); |
4104 } | 4110 } |
4105 | 4111 |
4106 void Assembler::fyl2x() { | 4112 void Assembler::fyl2x() { |
4107 emit_byte(0xD9); | 4113 emit_int8((unsigned char)0xD9); |
4108 emit_byte(0xF1); | 4114 emit_int8((unsigned char)0xF1); |
4109 } | 4115 } |
4110 | 4116 |
4111 void Assembler::frndint() { | 4117 void Assembler::frndint() { |
4112 emit_byte(0xD9); | 4118 emit_int8((unsigned char)0xD9); |
4113 emit_byte(0xFC); | 4119 emit_int8((unsigned char)0xFC); |
4114 } | 4120 } |
4115 | 4121 |
4116 void Assembler::f2xm1() { | 4122 void Assembler::f2xm1() { |
4117 emit_byte(0xD9); | 4123 emit_int8((unsigned char)0xD9); |
4118 emit_byte(0xF0); | 4124 emit_int8((unsigned char)0xF0); |
4119 } | 4125 } |
4120 | 4126 |
4121 void Assembler::fldl2e() { | 4127 void Assembler::fldl2e() { |
4122 emit_byte(0xD9); | 4128 emit_int8((unsigned char)0xD9); |
4123 emit_byte(0xEA); | 4129 emit_int8((unsigned char)0xEA); |
4124 } | 4130 } |
4125 | 4131 |
4126 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. | 4132 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. |
4127 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; | 4133 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; |
4128 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. | 4134 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. |
4129 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; | 4135 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; |
4130 | 4136 |
4131 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. | 4137 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. |
4132 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | 4138 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { |
4133 if (pre > 0) { | 4139 if (pre > 0) { |
4134 emit_byte(simd_pre[pre]); | 4140 emit_int8(simd_pre[pre]); |
4135 } | 4141 } |
4136 if (rex_w) { | 4142 if (rex_w) { |
4137 prefixq(adr, xreg); | 4143 prefixq(adr, xreg); |
4138 } else { | 4144 } else { |
4139 prefix(adr, xreg); | 4145 prefix(adr, xreg); |
4140 } | 4146 } |
4141 if (opc > 0) { | 4147 if (opc > 0) { |
4142 emit_byte(0x0F); | 4148 emit_int8(0x0F); |
4143 int opc2 = simd_opc[opc]; | 4149 int opc2 = simd_opc[opc]; |
4144 if (opc2 > 0) { | 4150 if (opc2 > 0) { |
4145 emit_byte(opc2); | 4151 emit_int8(opc2); |
4146 } | 4152 } |
4147 } | 4153 } |
4148 } | 4154 } |
4149 | 4155 |
4150 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | 4156 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { |
4151 if (pre > 0) { | 4157 if (pre > 0) { |
4152 emit_byte(simd_pre[pre]); | 4158 emit_int8(simd_pre[pre]); |
4153 } | 4159 } |
4154 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : | 4160 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : |
4155 prefix_and_encode(dst_enc, src_enc); | 4161 prefix_and_encode(dst_enc, src_enc); |
4156 if (opc > 0) { | 4162 if (opc > 0) { |
4157 emit_byte(0x0F); | 4163 emit_int8(0x0F); |
4158 int opc2 = simd_opc[opc]; | 4164 int opc2 = simd_opc[opc]; |
4159 if (opc2 > 0) { | 4165 if (opc2 > 0) { |
4160 emit_byte(opc2); | 4166 emit_int8(opc2); |
4161 } | 4167 } |
4162 } | 4168 } |
4163 return encode; | 4169 return encode; |
4164 } | 4170 } |
4165 | 4171 |
4169 prefix(VEX_3bytes); | 4175 prefix(VEX_3bytes); |
4170 | 4176 |
4171 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); | 4177 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); |
4172 byte1 = (~byte1) & 0xE0; | 4178 byte1 = (~byte1) & 0xE0; |
4173 byte1 |= opc; | 4179 byte1 |= opc; |
4174 a_byte(byte1); | 4180 emit_int8(byte1); |
4175 | 4181 |
4176 int byte2 = ((~nds_enc) & 0xf) << 3; | 4182 int byte2 = ((~nds_enc) & 0xf) << 3; |
4177 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre; | 4183 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre; |
4178 emit_byte(byte2); | 4184 emit_int8(byte2); |
4179 } else { | 4185 } else { |
4180 prefix(VEX_2bytes); | 4186 prefix(VEX_2bytes); |
4181 | 4187 |
4182 int byte1 = vex_r ? VEX_R : 0; | 4188 int byte1 = vex_r ? VEX_R : 0; |
4183 byte1 = (~byte1) & 0x80; | 4189 byte1 = (~byte1) & 0x80; |
4184 byte1 |= ((~nds_enc) & 0xf) << 3; | 4190 byte1 |= ((~nds_enc) & 0xf) << 3; |
4185 byte1 |= (vector256 ? 4 : 0) | pre; | 4191 byte1 |= (vector256 ? 4 : 0) | pre; |
4186 emit_byte(byte1); | 4192 emit_int8(byte1); |
4187 } | 4193 } |
4188 } | 4194 } |
4189 | 4195 |
4190 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){ | 4196 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){ |
4191 bool vex_r = (xreg_enc >= 8); | 4197 bool vex_r = (xreg_enc >= 8); |
4227 } | 4233 } |
4228 | 4234 |
4229 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { | 4235 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { |
4230 InstructionMark im(this); | 4236 InstructionMark im(this); |
4231 simd_prefix(dst, dst, src, pre); | 4237 simd_prefix(dst, dst, src, pre); |
4232 emit_byte(opcode); | 4238 emit_int8(opcode); |
4233 emit_operand(dst, src); | 4239 emit_operand(dst, src); |
4234 } | 4240 } |
4235 | 4241 |
4236 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { | 4242 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { |
4237 int encode = simd_prefix_and_encode(dst, dst, src, pre); | 4243 int encode = simd_prefix_and_encode(dst, dst, src, pre); |
4238 emit_byte(opcode); | 4244 emit_int8(opcode); |
4239 emit_byte(0xC0 | encode); | 4245 emit_int8((unsigned char)(0xC0 | encode)); |
4240 } | 4246 } |
4241 | 4247 |
4242 // Versions with no second source register (non-destructive source). | 4248 // Versions with no second source register (non-destructive source). |
4243 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { | 4249 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { |
4244 InstructionMark im(this); | 4250 InstructionMark im(this); |
4245 simd_prefix(dst, xnoreg, src, pre); | 4251 simd_prefix(dst, xnoreg, src, pre); |
4246 emit_byte(opcode); | 4252 emit_int8(opcode); |
4247 emit_operand(dst, src); | 4253 emit_operand(dst, src); |
4248 } | 4254 } |
4249 | 4255 |
4250 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { | 4256 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { |
4251 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre); | 4257 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre); |
4252 emit_byte(opcode); | 4258 emit_int8(opcode); |
4253 emit_byte(0xC0 | encode); | 4259 emit_int8((unsigned char)(0xC0 | encode)); |
4254 } | 4260 } |
4255 | 4261 |
4256 // 3-operands AVX instructions | 4262 // 3-operands AVX instructions |
4257 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, | 4263 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
4258 Address src, VexSimdPrefix pre, bool vector256) { | 4264 Address src, VexSimdPrefix pre, bool vector256) { |
4259 InstructionMark im(this); | 4265 InstructionMark im(this); |
4260 vex_prefix(dst, nds, src, pre, vector256); | 4266 vex_prefix(dst, nds, src, pre, vector256); |
4261 emit_byte(opcode); | 4267 emit_int8(opcode); |
4262 emit_operand(dst, src); | 4268 emit_operand(dst, src); |
4263 } | 4269 } |
4264 | 4270 |
4265 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, | 4271 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
4266 XMMRegister src, VexSimdPrefix pre, bool vector256) { | 4272 XMMRegister src, VexSimdPrefix pre, bool vector256) { |
4267 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256); | 4273 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256); |
4268 emit_byte(opcode); | 4274 emit_int8(opcode); |
4269 emit_byte(0xC0 | encode); | 4275 emit_int8((unsigned char)(0xC0 | encode)); |
4270 } | 4276 } |
4271 | 4277 |
4272 #ifndef _LP64 | 4278 #ifndef _LP64 |
4273 | 4279 |
4274 void Assembler::incl(Register dst) { | 4280 void Assembler::incl(Register dst) { |
4275 // Don't use it directly. Use MacroAssembler::incrementl() instead. | 4281 // Don't use it directly. Use MacroAssembler::incrementl() instead. |
4276 emit_byte(0x40 | dst->encoding()); | 4282 emit_int8(0x40 | dst->encoding()); |
4277 } | 4283 } |
4278 | 4284 |
4279 void Assembler::lea(Register dst, Address src) { | 4285 void Assembler::lea(Register dst, Address src) { |
4280 leal(dst, src); | 4286 leal(dst, src); |
4281 } | 4287 } |
4282 | 4288 |
4283 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | 4289 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
4284 InstructionMark im(this); | 4290 InstructionMark im(this); |
4285 emit_byte(0xC7); | 4291 emit_int8((unsigned char)0xC7); |
4286 emit_operand(rax, dst); | 4292 emit_operand(rax, dst); |
4287 emit_data((int)imm32, rspec, 0); | 4293 emit_data((int)imm32, rspec, 0); |
4288 } | 4294 } |
4289 | 4295 |
4290 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { | 4296 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
4291 InstructionMark im(this); | 4297 InstructionMark im(this); |
4292 int encode = prefix_and_encode(dst->encoding()); | 4298 int encode = prefix_and_encode(dst->encoding()); |
4293 emit_byte(0xB8 | encode); | 4299 emit_int8((unsigned char)(0xB8 | encode)); |
4294 emit_data((int)imm32, rspec, 0); | 4300 emit_data((int)imm32, rspec, 0); |
4295 } | 4301 } |
4296 | 4302 |
4297 void Assembler::popa() { // 32bit | 4303 void Assembler::popa() { // 32bit |
4298 emit_byte(0x61); | 4304 emit_int8(0x61); |
4299 } | 4305 } |
4300 | 4306 |
4301 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | 4307 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { |
4302 InstructionMark im(this); | 4308 InstructionMark im(this); |
4303 emit_byte(0x68); | 4309 emit_int8(0x68); |
4304 emit_data(imm32, rspec, 0); | 4310 emit_data(imm32, rspec, 0); |
4305 } | 4311 } |
4306 | 4312 |
4307 void Assembler::pusha() { // 32bit | 4313 void Assembler::pusha() { // 32bit |
4308 emit_byte(0x60); | 4314 emit_int8(0x60); |
4309 } | 4315 } |
4310 | 4316 |
4311 void Assembler::set_byte_if_not_zero(Register dst) { | 4317 void Assembler::set_byte_if_not_zero(Register dst) { |
4312 emit_byte(0x0F); | 4318 emit_int8(0x0F); |
4313 emit_byte(0x95); | 4319 emit_int8((unsigned char)0x95); |
4314 emit_byte(0xE0 | dst->encoding()); | 4320 emit_int8((unsigned char)(0xE0 | dst->encoding())); |
4315 } | 4321 } |
4316 | 4322 |
4317 void Assembler::shldl(Register dst, Register src) { | 4323 void Assembler::shldl(Register dst, Register src) { |
4318 emit_byte(0x0F); | 4324 emit_int8(0x0F); |
4319 emit_byte(0xA5); | 4325 emit_int8((unsigned char)0xA5); |
4320 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | 4326 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); |
4321 } | 4327 } |
4322 | 4328 |
4323 void Assembler::shrdl(Register dst, Register src) { | 4329 void Assembler::shrdl(Register dst, Register src) { |
4324 emit_byte(0x0F); | 4330 emit_int8(0x0F); |
4325 emit_byte(0xAD); | 4331 emit_int8((unsigned char)0xAD); |
4326 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | 4332 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); |
4327 } | 4333 } |
4328 | 4334 |
4329 #else // LP64 | 4335 #else // LP64 |
4330 | 4336 |
4331 void Assembler::set_byte_if_not_zero(Register dst) { | 4337 void Assembler::set_byte_if_not_zero(Register dst) { |
4332 int enc = prefix_and_encode(dst->encoding(), true); | 4338 int enc = prefix_and_encode(dst->encoding(), true); |
4333 emit_byte(0x0F); | 4339 emit_int8(0x0F); |
4334 emit_byte(0x95); | 4340 emit_int8((unsigned char)0x95); |
4335 emit_byte(0xE0 | enc); | 4341 emit_int8((unsigned char)(0xE0 | enc)); |
4336 } | 4342 } |
4337 | 4343 |
4338 // 64bit only pieces of the assembler | 4344 // 64bit only pieces of the assembler |
4339 // This should only be used by 64bit instructions that can use rip-relative | 4345 // This should only be used by 64bit instructions that can use rip-relative |
4340 // it cannot be used by instructions that want an immediate value. | 4346 // it cannot be used by instructions that want an immediate value. |
4668 } | 4674 } |
4669 | 4675 |
4670 void Assembler::adcq(Register dst, Address src) { | 4676 void Assembler::adcq(Register dst, Address src) { |
4671 InstructionMark im(this); | 4677 InstructionMark im(this); |
4672 prefixq(src, dst); | 4678 prefixq(src, dst); |
4673 emit_byte(0x13); | 4679 emit_int8(0x13); |
4674 emit_operand(dst, src); | 4680 emit_operand(dst, src); |
4675 } | 4681 } |
4676 | 4682 |
4677 void Assembler::adcq(Register dst, Register src) { | 4683 void Assembler::adcq(Register dst, Register src) { |
4678 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | 4684 (int) prefixq_and_encode(dst->encoding(), src->encoding()); |
4686 } | 4692 } |
4687 | 4693 |
4688 void Assembler::addq(Address dst, Register src) { | 4694 void Assembler::addq(Address dst, Register src) { |
4689 InstructionMark im(this); | 4695 InstructionMark im(this); |
4690 prefixq(dst, src); | 4696 prefixq(dst, src); |
4691 emit_byte(0x01); | 4697 emit_int8(0x01); |
4692 emit_operand(src, dst); | 4698 emit_operand(src, dst); |
4693 } | 4699 } |
4694 | 4700 |
4695 void Assembler::addq(Register dst, int32_t imm32) { | 4701 void Assembler::addq(Register dst, int32_t imm32) { |
4696 (void) prefixq_and_encode(dst->encoding()); | 4702 (void) prefixq_and_encode(dst->encoding()); |
4698 } | 4704 } |
4699 | 4705 |
4700 void Assembler::addq(Register dst, Address src) { | 4706 void Assembler::addq(Register dst, Address src) { |
4701 InstructionMark im(this); | 4707 InstructionMark im(this); |
4702 prefixq(src, dst); | 4708 prefixq(src, dst); |
4703 emit_byte(0x03); | 4709 emit_int8(0x03); |
4704 emit_operand(dst, src); | 4710 emit_operand(dst, src); |
4705 } | 4711 } |
4706 | 4712 |
4707 void Assembler::addq(Register dst, Register src) { | 4713 void Assembler::addq(Register dst, Register src) { |
4708 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | 4714 (void) prefixq_and_encode(dst->encoding(), src->encoding()); |
4710 } | 4716 } |
4711 | 4717 |
4712 void Assembler::andq(Address dst, int32_t imm32) { | 4718 void Assembler::andq(Address dst, int32_t imm32) { |
4713 InstructionMark im(this); | 4719 InstructionMark im(this); |
4714 prefixq(dst); | 4720 prefixq(dst); |
4715 emit_byte(0x81); | 4721 emit_int8((unsigned char)0x81); |
4716 emit_operand(rsp, dst, 4); | 4722 emit_operand(rsp, dst, 4); |
4717 emit_long(imm32); | 4723 emit_long(imm32); |
4718 } | 4724 } |
4719 | 4725 |
4720 void Assembler::andq(Register dst, int32_t imm32) { | 4726 void Assembler::andq(Register dst, int32_t imm32) { |
4723 } | 4729 } |
4724 | 4730 |
4725 void Assembler::andq(Register dst, Address src) { | 4731 void Assembler::andq(Register dst, Address src) { |
4726 InstructionMark im(this); | 4732 InstructionMark im(this); |
4727 prefixq(src, dst); | 4733 prefixq(src, dst); |
4728 emit_byte(0x23); | 4734 emit_int8(0x23); |
4729 emit_operand(dst, src); | 4735 emit_operand(dst, src); |
4730 } | 4736 } |
4731 | 4737 |
4732 void Assembler::andq(Register dst, Register src) { | 4738 void Assembler::andq(Register dst, Register src) { |
4733 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | 4739 (int) prefixq_and_encode(dst->encoding(), src->encoding()); |
4734 emit_arith(0x23, 0xC0, dst, src); | 4740 emit_arith(0x23, 0xC0, dst, src); |
4735 } | 4741 } |
4736 | 4742 |
4737 void Assembler::bsfq(Register dst, Register src) { | 4743 void Assembler::bsfq(Register dst, Register src) { |
4738 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 4744 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
4739 emit_byte(0x0F); | 4745 emit_int8(0x0F); |
4740 emit_byte(0xBC); | 4746 emit_int8((unsigned char)0xBC); |
4741 emit_byte(0xC0 | encode); | 4747 emit_int8((unsigned char)(0xC0 | encode)); |
4742 } | 4748 } |
4743 | 4749 |
4744 void Assembler::bsrq(Register dst, Register src) { | 4750 void Assembler::bsrq(Register dst, Register src) { |
4745 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); | 4751 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
4746 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 4752 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
4747 emit_byte(0x0F); | 4753 emit_int8(0x0F); |
4748 emit_byte(0xBD); | 4754 emit_int8((unsigned char)0xBD); |
4749 emit_byte(0xC0 | encode); | 4755 emit_int8((unsigned char)(0xC0 | encode)); |
4750 } | 4756 } |
4751 | 4757 |
4752 void Assembler::bswapq(Register reg) { | 4758 void Assembler::bswapq(Register reg) { |
4753 int encode = prefixq_and_encode(reg->encoding()); | 4759 int encode = prefixq_and_encode(reg->encoding()); |
4754 emit_byte(0x0F); | 4760 emit_int8(0x0F); |
4755 emit_byte(0xC8 | encode); | 4761 emit_int8((unsigned char)(0xC8 | encode)); |
4756 } | 4762 } |
4757 | 4763 |
4758 void Assembler::cdqq() { | 4764 void Assembler::cdqq() { |
4759 prefix(REX_W); | 4765 prefix(REX_W); |
4760 emit_byte(0x99); | 4766 emit_int8((unsigned char)0x99); |
4761 } | 4767 } |
4762 | 4768 |
4763 void Assembler::clflush(Address adr) { | 4769 void Assembler::clflush(Address adr) { |
4764 prefix(adr); | 4770 prefix(adr); |
4765 emit_byte(0x0F); | 4771 emit_int8(0x0F); |
4766 emit_byte(0xAE); | 4772 emit_int8((unsigned char)0xAE); |
4767 emit_operand(rdi, adr); | 4773 emit_operand(rdi, adr); |
4768 } | 4774 } |
4769 | 4775 |
4770 void Assembler::cmovq(Condition cc, Register dst, Register src) { | 4776 void Assembler::cmovq(Condition cc, Register dst, Register src) { |
4771 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 4777 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
4772 emit_byte(0x0F); | 4778 emit_int8(0x0F); |
4773 emit_byte(0x40 | cc); | 4779 emit_int8(0x40 | cc); |
4774 emit_byte(0xC0 | encode); | 4780 emit_int8((unsigned char)(0xC0 | encode)); |
4775 } | 4781 } |
4776 | 4782 |
4777 void Assembler::cmovq(Condition cc, Register dst, Address src) { | 4783 void Assembler::cmovq(Condition cc, Register dst, Address src) { |
4778 InstructionMark im(this); | 4784 InstructionMark im(this); |
4779 prefixq(src, dst); | 4785 prefixq(src, dst); |
4780 emit_byte(0x0F); | 4786 emit_int8(0x0F); |
4781 emit_byte(0x40 | cc); | 4787 emit_int8(0x40 | cc); |
4782 emit_operand(dst, src); | 4788 emit_operand(dst, src); |
4783 } | 4789 } |
4784 | 4790 |
4785 void Assembler::cmpq(Address dst, int32_t imm32) { | 4791 void Assembler::cmpq(Address dst, int32_t imm32) { |
4786 InstructionMark im(this); | 4792 InstructionMark im(this); |
4787 prefixq(dst); | 4793 prefixq(dst); |
4788 emit_byte(0x81); | 4794 emit_int8((unsigned char)0x81); |
4789 emit_operand(rdi, dst, 4); | 4795 emit_operand(rdi, dst, 4); |
4790 emit_long(imm32); | 4796 emit_long(imm32); |
4791 } | 4797 } |
4792 | 4798 |
4793 void Assembler::cmpq(Register dst, int32_t imm32) { | 4799 void Assembler::cmpq(Register dst, int32_t imm32) { |
4796 } | 4802 } |
4797 | 4803 |
4798 void Assembler::cmpq(Address dst, Register src) { | 4804 void Assembler::cmpq(Address dst, Register src) { |
4799 InstructionMark im(this); | 4805 InstructionMark im(this); |
4800 prefixq(dst, src); | 4806 prefixq(dst, src); |
4801 emit_byte(0x3B); | 4807 emit_int8(0x3B); |
4802 emit_operand(src, dst); | 4808 emit_operand(src, dst); |
4803 } | 4809 } |
4804 | 4810 |
4805 void Assembler::cmpq(Register dst, Register src) { | 4811 void Assembler::cmpq(Register dst, Register src) { |
4806 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | 4812 (void) prefixq_and_encode(dst->encoding(), src->encoding()); |
4808 } | 4814 } |
4809 | 4815 |
4810 void Assembler::cmpq(Register dst, Address src) { | 4816 void Assembler::cmpq(Register dst, Address src) { |
4811 InstructionMark im(this); | 4817 InstructionMark im(this); |
4812 prefixq(src, dst); | 4818 prefixq(src, dst); |
4813 emit_byte(0x3B); | 4819 emit_int8(0x3B); |
4814 emit_operand(dst, src); | 4820 emit_operand(dst, src); |
4815 } | 4821 } |
4816 | 4822 |
4817 void Assembler::cmpxchgq(Register reg, Address adr) { | 4823 void Assembler::cmpxchgq(Register reg, Address adr) { |
4818 InstructionMark im(this); | 4824 InstructionMark im(this); |
4819 prefixq(adr, reg); | 4825 prefixq(adr, reg); |
4820 emit_byte(0x0F); | 4826 emit_int8(0x0F); |
4821 emit_byte(0xB1); | 4827 emit_int8((unsigned char)0xB1); |
4822 emit_operand(reg, adr); | 4828 emit_operand(reg, adr); |
4823 } | 4829 } |
4824 | 4830 |
4825 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | 4831 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { |
4826 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 4832 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4827 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2); | 4833 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2); |
4828 emit_byte(0x2A); | 4834 emit_int8(0x2A); |
4829 emit_byte(0xC0 | encode); | 4835 emit_int8((unsigned char)(0xC0 | encode)); |
4830 } | 4836 } |
4831 | 4837 |
4832 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { | 4838 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { |
4833 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 4839 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4834 InstructionMark im(this); | 4840 InstructionMark im(this); |
4835 simd_prefix_q(dst, dst, src, VEX_SIMD_F2); | 4841 simd_prefix_q(dst, dst, src, VEX_SIMD_F2); |
4836 emit_byte(0x2A); | 4842 emit_int8(0x2A); |
4837 emit_operand(dst, src); | 4843 emit_operand(dst, src); |
4838 } | 4844 } |
4839 | 4845 |
4840 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { | 4846 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { |
4841 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 4847 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
4842 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3); | 4848 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3); |
4843 emit_byte(0x2A); | 4849 emit_int8(0x2A); |
4844 emit_byte(0xC0 | encode); | 4850 emit_int8((unsigned char)(0xC0 | encode)); |
4845 } | 4851 } |
4846 | 4852 |
4847 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { | 4853 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { |
4848 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 4854 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
4849 InstructionMark im(this); | 4855 InstructionMark im(this); |
4850 simd_prefix_q(dst, dst, src, VEX_SIMD_F3); | 4856 simd_prefix_q(dst, dst, src, VEX_SIMD_F3); |
4851 emit_byte(0x2A); | 4857 emit_int8(0x2A); |
4852 emit_operand(dst, src); | 4858 emit_operand(dst, src); |
4853 } | 4859 } |
4854 | 4860 |
4855 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { | 4861 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { |
4856 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 4862 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4857 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2); | 4863 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2); |
4858 emit_byte(0x2C); | 4864 emit_int8(0x2C); |
4859 emit_byte(0xC0 | encode); | 4865 emit_int8((unsigned char)(0xC0 | encode)); |
4860 } | 4866 } |
4861 | 4867 |
4862 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | 4868 void Assembler::cvttss2siq(Register dst, XMMRegister src) { |
4863 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 4869 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
4864 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3); | 4870 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3); |
4865 emit_byte(0x2C); | 4871 emit_int8(0x2C); |
4866 emit_byte(0xC0 | encode); | 4872 emit_int8((unsigned char)(0xC0 | encode)); |
4867 } | 4873 } |
4868 | 4874 |
4869 void Assembler::decl(Register dst) { | 4875 void Assembler::decl(Register dst) { |
4870 // Don't use it directly. Use MacroAssembler::decrementl() instead. | 4876 // Don't use it directly. Use MacroAssembler::decrementl() instead. |
4871 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | 4877 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) |
4872 int encode = prefix_and_encode(dst->encoding()); | 4878 int encode = prefix_and_encode(dst->encoding()); |
4873 emit_byte(0xFF); | 4879 emit_int8((unsigned char)0xFF); |
4874 emit_byte(0xC8 | encode); | 4880 emit_int8((unsigned char)(0xC8 | encode)); |
4875 } | 4881 } |
4876 | 4882 |
4877 void Assembler::decq(Register dst) { | 4883 void Assembler::decq(Register dst) { |
4878 // Don't use it directly. Use MacroAssembler::decrementq() instead. | 4884 // Don't use it directly. Use MacroAssembler::decrementq() instead. |
4879 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | 4885 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) |
4880 int encode = prefixq_and_encode(dst->encoding()); | 4886 int encode = prefixq_and_encode(dst->encoding()); |
4881 emit_byte(0xFF); | 4887 emit_int8((unsigned char)0xFF); |
4882 emit_byte(0xC8 | encode); | 4888 emit_int8(0xC8 | encode); |
4883 } | 4889 } |
4884 | 4890 |
4885 void Assembler::decq(Address dst) { | 4891 void Assembler::decq(Address dst) { |
4886 // Don't use it directly. Use MacroAssembler::decrementq() instead. | 4892 // Don't use it directly. Use MacroAssembler::decrementq() instead. |
4887 InstructionMark im(this); | 4893 InstructionMark im(this); |
4888 prefixq(dst); | 4894 prefixq(dst); |
4889 emit_byte(0xFF); | 4895 emit_int8((unsigned char)0xFF); |
4890 emit_operand(rcx, dst); | 4896 emit_operand(rcx, dst); |
4891 } | 4897 } |
4892 | 4898 |
4893 void Assembler::fxrstor(Address src) { | 4899 void Assembler::fxrstor(Address src) { |
4894 prefixq(src); | 4900 prefixq(src); |
4895 emit_byte(0x0F); | 4901 emit_int8(0x0F); |
4896 emit_byte(0xAE); | 4902 emit_int8((unsigned char)0xAE); |
4897 emit_operand(as_Register(1), src); | 4903 emit_operand(as_Register(1), src); |
4898 } | 4904 } |
4899 | 4905 |
4900 void Assembler::fxsave(Address dst) { | 4906 void Assembler::fxsave(Address dst) { |
4901 prefixq(dst); | 4907 prefixq(dst); |
4902 emit_byte(0x0F); | 4908 emit_int8(0x0F); |
4903 emit_byte(0xAE); | 4909 emit_int8((unsigned char)0xAE); |
4904 emit_operand(as_Register(0), dst); | 4910 emit_operand(as_Register(0), dst); |
4905 } | 4911 } |
4906 | 4912 |
4907 void Assembler::idivq(Register src) { | 4913 void Assembler::idivq(Register src) { |
4908 int encode = prefixq_and_encode(src->encoding()); | 4914 int encode = prefixq_and_encode(src->encoding()); |
4909 emit_byte(0xF7); | 4915 emit_int8((unsigned char)0xF7); |
4910 emit_byte(0xF8 | encode); | 4916 emit_int8((unsigned char)(0xF8 | encode)); |
4911 } | 4917 } |
4912 | 4918 |
4913 void Assembler::imulq(Register dst, Register src) { | 4919 void Assembler::imulq(Register dst, Register src) { |
4914 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 4920 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
4915 emit_byte(0x0F); | 4921 emit_int8(0x0F); |
4916 emit_byte(0xAF); | 4922 emit_int8((unsigned char)0xAF); |
4917 emit_byte(0xC0 | encode); | 4923 emit_int8((unsigned char)(0xC0 | encode)); |
4918 } | 4924 } |
4919 | 4925 |
4920 void Assembler::imulq(Register dst, Register src, int value) { | 4926 void Assembler::imulq(Register dst, Register src, int value) { |
4921 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 4927 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
4922 if (is8bit(value)) { | 4928 if (is8bit(value)) { |
4923 emit_byte(0x6B); | 4929 emit_int8(0x6B); |
4924 emit_byte(0xC0 | encode); | 4930 emit_int8((unsigned char)(0xC0 | encode)); |
4925 emit_byte(value & 0xFF); | 4931 emit_int8(value & 0xFF); |
4926 } else { | 4932 } else { |
4927 emit_byte(0x69); | 4933 emit_int8(0x69); |
4928 emit_byte(0xC0 | encode); | 4934 emit_int8((unsigned char)(0xC0 | encode)); |
4929 emit_long(value); | 4935 emit_long(value); |
4930 } | 4936 } |
4931 } | 4937 } |
4932 | 4938 |
4933 void Assembler::incl(Register dst) { | 4939 void Assembler::incl(Register dst) { |
4934 // Don't use it directly. Use MacroAssembler::incrementl() instead. | 4940 // Don't use it directly. Use MacroAssembler::incrementl() instead. |
4935 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | 4941 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) |
4936 int encode = prefix_and_encode(dst->encoding()); | 4942 int encode = prefix_and_encode(dst->encoding()); |
4937 emit_byte(0xFF); | 4943 emit_int8((unsigned char)0xFF); |
4938 emit_byte(0xC0 | encode); | 4944 emit_int8((unsigned char)(0xC0 | encode)); |
4939 } | 4945 } |
4940 | 4946 |
4941 void Assembler::incq(Register dst) { | 4947 void Assembler::incq(Register dst) { |
4942 // Don't use it directly. Use MacroAssembler::incrementq() instead. | 4948 // Don't use it directly. Use MacroAssembler::incrementq() instead. |
4943 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | 4949 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) |
4944 int encode = prefixq_and_encode(dst->encoding()); | 4950 int encode = prefixq_and_encode(dst->encoding()); |
4945 emit_byte(0xFF); | 4951 emit_int8((unsigned char)0xFF); |
4946 emit_byte(0xC0 | encode); | 4952 emit_int8((unsigned char)(0xC0 | encode)); |
4947 } | 4953 } |
4948 | 4954 |
4949 void Assembler::incq(Address dst) { | 4955 void Assembler::incq(Address dst) { |
4950 // Don't use it directly. Use MacroAssembler::incrementq() instead. | 4956 // Don't use it directly. Use MacroAssembler::incrementq() instead. |
4951 InstructionMark im(this); | 4957 InstructionMark im(this); |
4952 prefixq(dst); | 4958 prefixq(dst); |
4953 emit_byte(0xFF); | 4959 emit_int8((unsigned char)0xFF); |
4954 emit_operand(rax, dst); | 4960 emit_operand(rax, dst); |
4955 } | 4961 } |
4956 | 4962 |
4957 void Assembler::lea(Register dst, Address src) { | 4963 void Assembler::lea(Register dst, Address src) { |
4958 leaq(dst, src); | 4964 leaq(dst, src); |
4959 } | 4965 } |
4960 | 4966 |
4961 void Assembler::leaq(Register dst, Address src) { | 4967 void Assembler::leaq(Register dst, Address src) { |
4962 InstructionMark im(this); | 4968 InstructionMark im(this); |
4963 prefixq(src, dst); | 4969 prefixq(src, dst); |
4964 emit_byte(0x8D); | 4970 emit_int8((unsigned char)0x8D); |
4965 emit_operand(dst, src); | 4971 emit_operand(dst, src); |
4966 } | 4972 } |
4967 | 4973 |
4968 void Assembler::mov64(Register dst, int64_t imm64) { | 4974 void Assembler::mov64(Register dst, int64_t imm64) { |
4969 InstructionMark im(this); | 4975 InstructionMark im(this); |
4970 int encode = prefixq_and_encode(dst->encoding()); | 4976 int encode = prefixq_and_encode(dst->encoding()); |
4971 emit_byte(0xB8 | encode); | 4977 emit_int8((unsigned char)(0xB8 | encode)); |
4972 emit_int64(imm64); | 4978 emit_int64(imm64); |
4973 } | 4979 } |
4974 | 4980 |
4975 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | 4981 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { |
4976 InstructionMark im(this); | 4982 InstructionMark im(this); |
4977 int encode = prefixq_and_encode(dst->encoding()); | 4983 int encode = prefixq_and_encode(dst->encoding()); |
4978 emit_byte(0xB8 | encode); | 4984 emit_int8(0xB8 | encode); |
4979 emit_data64(imm64, rspec); | 4985 emit_data64(imm64, rspec); |
4980 } | 4986 } |
4981 | 4987 |
4982 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { | 4988 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
4983 InstructionMark im(this); | 4989 InstructionMark im(this); |
4984 int encode = prefix_and_encode(dst->encoding()); | 4990 int encode = prefix_and_encode(dst->encoding()); |
4985 emit_byte(0xB8 | encode); | 4991 emit_int8((unsigned char)(0xB8 | encode)); |
4986 emit_data((int)imm32, rspec, narrow_oop_operand); | 4992 emit_data((int)imm32, rspec, narrow_oop_operand); |
4987 } | 4993 } |
4988 | 4994 |
4989 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { | 4995 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
4990 InstructionMark im(this); | 4996 InstructionMark im(this); |
4991 prefix(dst); | 4997 prefix(dst); |
4992 emit_byte(0xC7); | 4998 emit_int8((unsigned char)0xC7); |
4993 emit_operand(rax, dst, 4); | 4999 emit_operand(rax, dst, 4); |
4994 emit_data((int)imm32, rspec, narrow_oop_operand); | 5000 emit_data((int)imm32, rspec, narrow_oop_operand); |
4995 } | 5001 } |
4996 | 5002 |
4997 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { | 5003 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
4998 InstructionMark im(this); | 5004 InstructionMark im(this); |
4999 int encode = prefix_and_encode(src1->encoding()); | 5005 int encode = prefix_and_encode(src1->encoding()); |
5000 emit_byte(0x81); | 5006 emit_int8((unsigned char)0x81); |
5001 emit_byte(0xF8 | encode); | 5007 emit_int8((unsigned char)(0xF8 | encode)); |
5002 emit_data((int)imm32, rspec, narrow_oop_operand); | 5008 emit_data((int)imm32, rspec, narrow_oop_operand); |
5003 } | 5009 } |
5004 | 5010 |
5005 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { | 5011 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
5006 InstructionMark im(this); | 5012 InstructionMark im(this); |
5007 prefix(src1); | 5013 prefix(src1); |
5008 emit_byte(0x81); | 5014 emit_int8((unsigned char)0x81); |
5009 emit_operand(rax, src1, 4); | 5015 emit_operand(rax, src1, 4); |
5010 emit_data((int)imm32, rspec, narrow_oop_operand); | 5016 emit_data((int)imm32, rspec, narrow_oop_operand); |
5011 } | 5017 } |
5012 | 5018 |
5013 void Assembler::lzcntq(Register dst, Register src) { | 5019 void Assembler::lzcntq(Register dst, Register src) { |
5014 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); | 5020 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
5015 emit_byte(0xF3); | 5021 emit_int8((unsigned char)0xF3); |
5016 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 5022 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
5017 emit_byte(0x0F); | 5023 emit_int8(0x0F); |
5018 emit_byte(0xBD); | 5024 emit_int8((unsigned char)0xBD); |
5019 emit_byte(0xC0 | encode); | 5025 emit_int8((unsigned char)(0xC0 | encode)); |
5020 } | 5026 } |
5021 | 5027 |
5022 void Assembler::movdq(XMMRegister dst, Register src) { | 5028 void Assembler::movdq(XMMRegister dst, Register src) { |
5023 // table D-1 says MMX/SSE2 | 5029 // table D-1 says MMX/SSE2 |
5024 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 5030 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
5025 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66); | 5031 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66); |
5026 emit_byte(0x6E); | 5032 emit_int8(0x6E); |
5027 emit_byte(0xC0 | encode); | 5033 emit_int8((unsigned char)(0xC0 | encode)); |
5028 } | 5034 } |
5029 | 5035 |
5030 void Assembler::movdq(Register dst, XMMRegister src) { | 5036 void Assembler::movdq(Register dst, XMMRegister src) { |
5031 // table D-1 says MMX/SSE2 | 5037 // table D-1 says MMX/SSE2 |
5032 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 5038 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
5033 // swap src/dst to get correct prefix | 5039 // swap src/dst to get correct prefix |
5034 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66); | 5040 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66); |
5035 emit_byte(0x7E); | 5041 emit_int8(0x7E); |
5036 emit_byte(0xC0 | encode); | 5042 emit_int8((unsigned char)(0xC0 | encode)); |
5037 } | 5043 } |
5038 | 5044 |
5039 void Assembler::movq(Register dst, Register src) { | 5045 void Assembler::movq(Register dst, Register src) { |
5040 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 5046 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
5041 emit_byte(0x8B); | 5047 emit_int8((unsigned char)0x8B); |
5042 emit_byte(0xC0 | encode); | 5048 emit_int8((unsigned char)(0xC0 | encode)); |
5043 } | 5049 } |
5044 | 5050 |
5045 void Assembler::movq(Register dst, Address src) { | 5051 void Assembler::movq(Register dst, Address src) { |
5046 InstructionMark im(this); | 5052 InstructionMark im(this); |
5047 prefixq(src, dst); | 5053 prefixq(src, dst); |
5048 emit_byte(0x8B); | 5054 emit_int8((unsigned char)0x8B); |
5049 emit_operand(dst, src); | 5055 emit_operand(dst, src); |
5050 } | 5056 } |
5051 | 5057 |
5052 void Assembler::movq(Address dst, Register src) { | 5058 void Assembler::movq(Address dst, Register src) { |
5053 InstructionMark im(this); | 5059 InstructionMark im(this); |
5054 prefixq(dst, src); | 5060 prefixq(dst, src); |
5055 emit_byte(0x89); | 5061 emit_int8((unsigned char)0x89); |
5056 emit_operand(src, dst); | 5062 emit_operand(src, dst); |
5057 } | 5063 } |
5058 | 5064 |
5059 void Assembler::movsbq(Register dst, Address src) { | 5065 void Assembler::movsbq(Register dst, Address src) { |
5060 InstructionMark im(this); | 5066 InstructionMark im(this); |
5061 prefixq(src, dst); | 5067 prefixq(src, dst); |
5062 emit_byte(0x0F); | 5068 emit_int8(0x0F); |
5063 emit_byte(0xBE); | 5069 emit_int8((unsigned char)0xBE); |
5064 emit_operand(dst, src); | 5070 emit_operand(dst, src); |
5065 } | 5071 } |
5066 | 5072 |
5067 void Assembler::movsbq(Register dst, Register src) { | 5073 void Assembler::movsbq(Register dst, Register src) { |
5068 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 5074 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
5069 emit_byte(0x0F); | 5075 emit_int8(0x0F); |
5070 emit_byte(0xBE); | 5076 emit_int8((unsigned char)0xBE); |
5071 emit_byte(0xC0 | encode); | 5077 emit_int8((unsigned char)(0xC0 | encode)); |
5072 } | 5078 } |
5073 | 5079 |
5074 void Assembler::movslq(Register dst, int32_t imm32) { | 5080 void Assembler::movslq(Register dst, int32_t imm32) { |
5075 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | 5081 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) |
5076 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | 5082 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) |
5077 // as a result we shouldn't use until tested at runtime... | 5083 // as a result we shouldn't use until tested at runtime... |
5078 ShouldNotReachHere(); | 5084 ShouldNotReachHere(); |
5079 InstructionMark im(this); | 5085 InstructionMark im(this); |
5080 int encode = prefixq_and_encode(dst->encoding()); | 5086 int encode = prefixq_and_encode(dst->encoding()); |
5081 emit_byte(0xC7 | encode); | 5087 emit_int8((unsigned char)(0xC7 | encode)); |
5082 emit_long(imm32); | 5088 emit_long(imm32); |
5083 } | 5089 } |
5084 | 5090 |
5085 void Assembler::movslq(Address dst, int32_t imm32) { | 5091 void Assembler::movslq(Address dst, int32_t imm32) { |
5086 assert(is_simm32(imm32), "lost bits"); | 5092 assert(is_simm32(imm32), "lost bits"); |
5087 InstructionMark im(this); | 5093 InstructionMark im(this); |
5088 prefixq(dst); | 5094 prefixq(dst); |
5089 emit_byte(0xC7); | 5095 emit_int8((unsigned char)0xC7); |
5090 emit_operand(rax, dst, 4); | 5096 emit_operand(rax, dst, 4); |
5091 emit_long(imm32); | 5097 emit_long(imm32); |
5092 } | 5098 } |
5093 | 5099 |
5094 void Assembler::movslq(Register dst, Address src) { | 5100 void Assembler::movslq(Register dst, Address src) { |
5095 InstructionMark im(this); | 5101 InstructionMark im(this); |
5096 prefixq(src, dst); | 5102 prefixq(src, dst); |
5097 emit_byte(0x63); | 5103 emit_int8(0x63); |
5098 emit_operand(dst, src); | 5104 emit_operand(dst, src); |
5099 } | 5105 } |
5100 | 5106 |
5101 void Assembler::movslq(Register dst, Register src) { | 5107 void Assembler::movslq(Register dst, Register src) { |
5102 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 5108 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
5103 emit_byte(0x63); | 5109 emit_int8(0x63); |
5104 emit_byte(0xC0 | encode); | 5110 emit_int8((unsigned char)(0xC0 | encode)); |
5105 } | 5111 } |
5106 | 5112 |
5107 void Assembler::movswq(Register dst, Address src) { | 5113 void Assembler::movswq(Register dst, Address src) { |
5108 InstructionMark im(this); | 5114 InstructionMark im(this); |
5109 prefixq(src, dst); | 5115 prefixq(src, dst); |
5110 emit_byte(0x0F); | 5116 emit_int8(0x0F); |
5111 emit_byte(0xBF); | 5117 emit_int8((unsigned char)0xBF); |
5112 emit_operand(dst, src); | 5118 emit_operand(dst, src); |
5113 } | 5119 } |
5114 | 5120 |
5115 void Assembler::movswq(Register dst, Register src) { | 5121 void Assembler::movswq(Register dst, Register src) { |
5116 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 5122 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
5117 emit_byte(0x0F); | 5123 emit_int8((unsigned char)0x0F); |
5118 emit_byte(0xBF); | 5124 emit_int8((unsigned char)0xBF); |
5119 emit_byte(0xC0 | encode); | 5125 emit_int8((unsigned char)(0xC0 | encode)); |
5120 } | 5126 } |
5121 | 5127 |
5122 void Assembler::movzbq(Register dst, Address src) { | 5128 void Assembler::movzbq(Register dst, Address src) { |
5123 InstructionMark im(this); | 5129 InstructionMark im(this); |
5124 prefixq(src, dst); | 5130 prefixq(src, dst); |
5125 emit_byte(0x0F); | 5131 emit_int8((unsigned char)0x0F); |
5126 emit_byte(0xB6); | 5132 emit_int8((unsigned char)0xB6); |
5127 emit_operand(dst, src); | 5133 emit_operand(dst, src); |
5128 } | 5134 } |
5129 | 5135 |
5130 void Assembler::movzbq(Register dst, Register src) { | 5136 void Assembler::movzbq(Register dst, Register src) { |
5131 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 5137 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
5132 emit_byte(0x0F); | 5138 emit_int8(0x0F); |
5133 emit_byte(0xB6); | 5139 emit_int8((unsigned char)0xB6); |
5134 emit_byte(0xC0 | encode); | 5140 emit_int8(0xC0 | encode); |
5135 } | 5141 } |
5136 | 5142 |
5137 void Assembler::movzwq(Register dst, Address src) { | 5143 void Assembler::movzwq(Register dst, Address src) { |
5138 InstructionMark im(this); | 5144 InstructionMark im(this); |
5139 prefixq(src, dst); | 5145 prefixq(src, dst); |
5140 emit_byte(0x0F); | 5146 emit_int8((unsigned char)0x0F); |
5141 emit_byte(0xB7); | 5147 emit_int8((unsigned char)0xB7); |
5142 emit_operand(dst, src); | 5148 emit_operand(dst, src); |
5143 } | 5149 } |
5144 | 5150 |
5145 void Assembler::movzwq(Register dst, Register src) { | 5151 void Assembler::movzwq(Register dst, Register src) { |
5146 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 5152 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
5147 emit_byte(0x0F); | 5153 emit_int8((unsigned char)0x0F); |
5148 emit_byte(0xB7); | 5154 emit_int8((unsigned char)0xB7); |
5149 emit_byte(0xC0 | encode); | 5155 emit_int8((unsigned char)(0xC0 | encode)); |
5150 } | 5156 } |
5151 | 5157 |
5152 void Assembler::negq(Register dst) { | 5158 void Assembler::negq(Register dst) { |
5153 int encode = prefixq_and_encode(dst->encoding()); | 5159 int encode = prefixq_and_encode(dst->encoding()); |
5154 emit_byte(0xF7); | 5160 emit_int8((unsigned char)0xF7); |
5155 emit_byte(0xD8 | encode); | 5161 emit_int8((unsigned char)(0xD8 | encode)); |
5156 } | 5162 } |
5157 | 5163 |
5158 void Assembler::notq(Register dst) { | 5164 void Assembler::notq(Register dst) { |
5159 int encode = prefixq_and_encode(dst->encoding()); | 5165 int encode = prefixq_and_encode(dst->encoding()); |
5160 emit_byte(0xF7); | 5166 emit_int8((unsigned char)0xF7); |
5161 emit_byte(0xD0 | encode); | 5167 emit_int8((unsigned char)(0xD0 | encode)); |
5162 } | 5168 } |
5163 | 5169 |
5164 void Assembler::orq(Address dst, int32_t imm32) { | 5170 void Assembler::orq(Address dst, int32_t imm32) { |
5165 InstructionMark im(this); | 5171 InstructionMark im(this); |
5166 prefixq(dst); | 5172 prefixq(dst); |
5167 emit_byte(0x81); | 5173 emit_int8((unsigned char)0x81); |
5168 emit_operand(rcx, dst, 4); | 5174 emit_operand(rcx, dst, 4); |
5169 emit_long(imm32); | 5175 emit_long(imm32); |
5170 } | 5176 } |
5171 | 5177 |
5172 void Assembler::orq(Register dst, int32_t imm32) { | 5178 void Assembler::orq(Register dst, int32_t imm32) { |
5175 } | 5181 } |
5176 | 5182 |
5177 void Assembler::orq(Register dst, Address src) { | 5183 void Assembler::orq(Register dst, Address src) { |
5178 InstructionMark im(this); | 5184 InstructionMark im(this); |
5179 prefixq(src, dst); | 5185 prefixq(src, dst); |
5180 emit_byte(0x0B); | 5186 emit_int8(0x0B); |
5181 emit_operand(dst, src); | 5187 emit_operand(dst, src); |
5182 } | 5188 } |
5183 | 5189 |
5184 void Assembler::orq(Register dst, Register src) { | 5190 void Assembler::orq(Register dst, Register src) { |
5185 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | 5191 (void) prefixq_and_encode(dst->encoding(), src->encoding()); |
5208 } | 5214 } |
5209 | 5215 |
5210 void Assembler::popcntq(Register dst, Address src) { | 5216 void Assembler::popcntq(Register dst, Address src) { |
5211 assert(VM_Version::supports_popcnt(), "must support"); | 5217 assert(VM_Version::supports_popcnt(), "must support"); |
5212 InstructionMark im(this); | 5218 InstructionMark im(this); |
5213 emit_byte(0xF3); | 5219 emit_int8((unsigned char)0xF3); |
5214 prefixq(src, dst); | 5220 prefixq(src, dst); |
5215 emit_byte(0x0F); | 5221 emit_int8((unsigned char)0x0F); |
5216 emit_byte(0xB8); | 5222 emit_int8((unsigned char)0xB8); |
5217 emit_operand(dst, src); | 5223 emit_operand(dst, src); |
5218 } | 5224 } |
5219 | 5225 |
5220 void Assembler::popcntq(Register dst, Register src) { | 5226 void Assembler::popcntq(Register dst, Register src) { |
5221 assert(VM_Version::supports_popcnt(), "must support"); | 5227 assert(VM_Version::supports_popcnt(), "must support"); |
5222 emit_byte(0xF3); | 5228 emit_int8((unsigned char)0xF3); |
5223 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 5229 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
5224 emit_byte(0x0F); | 5230 emit_int8((unsigned char)0x0F); |
5225 emit_byte(0xB8); | 5231 emit_int8((unsigned char)0xB8); |
5226 emit_byte(0xC0 | encode); | 5232 emit_int8((unsigned char)(0xC0 | encode)); |
5227 } | 5233 } |
5228 | 5234 |
5229 void Assembler::popq(Address dst) { | 5235 void Assembler::popq(Address dst) { |
5230 InstructionMark im(this); | 5236 InstructionMark im(this); |
5231 prefixq(dst); | 5237 prefixq(dst); |
5232 emit_byte(0x8F); | 5238 emit_int8((unsigned char)0x8F); |
5233 emit_operand(rax, dst); | 5239 emit_operand(rax, dst); |
5234 } | 5240 } |
5235 | 5241 |
5236 void Assembler::pusha() { // 64bit | 5242 void Assembler::pusha() { // 64bit |
5237 // we have to store original rsp. ABI says that 128 bytes | 5243 // we have to store original rsp. ABI says that 128 bytes |
5259 } | 5265 } |
5260 | 5266 |
5261 void Assembler::pushq(Address src) { | 5267 void Assembler::pushq(Address src) { |
5262 InstructionMark im(this); | 5268 InstructionMark im(this); |
5263 prefixq(src); | 5269 prefixq(src); |
5264 emit_byte(0xFF); | 5270 emit_int8((unsigned char)0xFF); |
5265 emit_operand(rsi, src); | 5271 emit_operand(rsi, src); |
5266 } | 5272 } |
5267 | 5273 |
5268 void Assembler::rclq(Register dst, int imm8) { | 5274 void Assembler::rclq(Register dst, int imm8) { |
5269 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | 5275 assert(isShiftCount(imm8 >> 1), "illegal shift count"); |
5270 int encode = prefixq_and_encode(dst->encoding()); | 5276 int encode = prefixq_and_encode(dst->encoding()); |
5271 if (imm8 == 1) { | 5277 if (imm8 == 1) { |
5272 emit_byte(0xD1); | 5278 emit_int8((unsigned char)0xD1); |
5273 emit_byte(0xD0 | encode); | 5279 emit_int8((unsigned char)(0xD0 | encode)); |
5274 } else { | 5280 } else { |
5275 emit_byte(0xC1); | 5281 emit_int8((unsigned char)0xC1); |
5276 emit_byte(0xD0 | encode); | 5282 emit_int8((unsigned char)(0xD0 | encode)); |
5277 emit_byte(imm8); | 5283 emit_int8(imm8); |
5278 } | 5284 } |
5279 } | 5285 } |
5280 void Assembler::sarq(Register dst, int imm8) { | 5286 void Assembler::sarq(Register dst, int imm8) { |
5281 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | 5287 assert(isShiftCount(imm8 >> 1), "illegal shift count"); |
5282 int encode = prefixq_and_encode(dst->encoding()); | 5288 int encode = prefixq_and_encode(dst->encoding()); |
5283 if (imm8 == 1) { | 5289 if (imm8 == 1) { |
5284 emit_byte(0xD1); | 5290 emit_int8((unsigned char)0xD1); |
5285 emit_byte(0xF8 | encode); | 5291 emit_int8((unsigned char)(0xF8 | encode)); |
5286 } else { | 5292 } else { |
5287 emit_byte(0xC1); | 5293 emit_int8((unsigned char)0xC1); |
5288 emit_byte(0xF8 | encode); | 5294 emit_int8((unsigned char)(0xF8 | encode)); |
5289 emit_byte(imm8); | 5295 emit_int8(imm8); |
5290 } | 5296 } |
5291 } | 5297 } |
5292 | 5298 |
5293 void Assembler::sarq(Register dst) { | 5299 void Assembler::sarq(Register dst) { |
5294 int encode = prefixq_and_encode(dst->encoding()); | 5300 int encode = prefixq_and_encode(dst->encoding()); |
5295 emit_byte(0xD3); | 5301 emit_int8((unsigned char)0xD3); |
5296 emit_byte(0xF8 | encode); | 5302 emit_int8((unsigned char)(0xF8 | encode)); |
5297 } | 5303 } |
5298 | 5304 |
5299 void Assembler::sbbq(Address dst, int32_t imm32) { | 5305 void Assembler::sbbq(Address dst, int32_t imm32) { |
5300 InstructionMark im(this); | 5306 InstructionMark im(this); |
5301 prefixq(dst); | 5307 prefixq(dst); |
5308 } | 5314 } |
5309 | 5315 |
5310 void Assembler::sbbq(Register dst, Address src) { | 5316 void Assembler::sbbq(Register dst, Address src) { |
5311 InstructionMark im(this); | 5317 InstructionMark im(this); |
5312 prefixq(src, dst); | 5318 prefixq(src, dst); |
5313 emit_byte(0x1B); | 5319 emit_int8(0x1B); |
5314 emit_operand(dst, src); | 5320 emit_operand(dst, src); |
5315 } | 5321 } |
5316 | 5322 |
5317 void Assembler::sbbq(Register dst, Register src) { | 5323 void Assembler::sbbq(Register dst, Register src) { |
5318 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | 5324 (void) prefixq_and_encode(dst->encoding(), src->encoding()); |
5321 | 5327 |
5322 void Assembler::shlq(Register dst, int imm8) { | 5328 void Assembler::shlq(Register dst, int imm8) { |
5323 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | 5329 assert(isShiftCount(imm8 >> 1), "illegal shift count"); |
5324 int encode = prefixq_and_encode(dst->encoding()); | 5330 int encode = prefixq_and_encode(dst->encoding()); |
5325 if (imm8 == 1) { | 5331 if (imm8 == 1) { |
5326 emit_byte(0xD1); | 5332 emit_int8((unsigned char)0xD1); |
5327 emit_byte(0xE0 | encode); | 5333 emit_int8((unsigned char)(0xE0 | encode)); |
5328 } else { | 5334 } else { |
5329 emit_byte(0xC1); | 5335 emit_int8((unsigned char)0xC1); |
5330 emit_byte(0xE0 | encode); | 5336 emit_int8((unsigned char)(0xE0 | encode)); |
5331 emit_byte(imm8); | 5337 emit_int8(imm8); |
5332 } | 5338 } |
5333 } | 5339 } |
5334 | 5340 |
5335 void Assembler::shlq(Register dst) { | 5341 void Assembler::shlq(Register dst) { |
5336 int encode = prefixq_and_encode(dst->encoding()); | 5342 int encode = prefixq_and_encode(dst->encoding()); |
5337 emit_byte(0xD3); | 5343 emit_int8((unsigned char)0xD3); |
5338 emit_byte(0xE0 | encode); | 5344 emit_int8((unsigned char)(0xE0 | encode)); |
5339 } | 5345 } |
5340 | 5346 |
5341 void Assembler::shrq(Register dst, int imm8) { | 5347 void Assembler::shrq(Register dst, int imm8) { |
5342 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | 5348 assert(isShiftCount(imm8 >> 1), "illegal shift count"); |
5343 int encode = prefixq_and_encode(dst->encoding()); | 5349 int encode = prefixq_and_encode(dst->encoding()); |
5344 emit_byte(0xC1); | 5350 emit_int8((unsigned char)0xC1); |
5345 emit_byte(0xE8 | encode); | 5351 emit_int8((unsigned char)(0xE8 | encode)); |
5346 emit_byte(imm8); | 5352 emit_int8(imm8); |
5347 } | 5353 } |
5348 | 5354 |
5349 void Assembler::shrq(Register dst) { | 5355 void Assembler::shrq(Register dst) { |
5350 int encode = prefixq_and_encode(dst->encoding()); | 5356 int encode = prefixq_and_encode(dst->encoding()); |
5351 emit_byte(0xD3); | 5357 emit_int8((unsigned char)0xD3); |
5352 emit_byte(0xE8 | encode); | 5358 emit_int8(0xE8 | encode); |
5353 } | 5359 } |
5354 | 5360 |
5355 void Assembler::subq(Address dst, int32_t imm32) { | 5361 void Assembler::subq(Address dst, int32_t imm32) { |
5356 InstructionMark im(this); | 5362 InstructionMark im(this); |
5357 prefixq(dst); | 5363 prefixq(dst); |
5359 } | 5365 } |
5360 | 5366 |
5361 void Assembler::subq(Address dst, Register src) { | 5367 void Assembler::subq(Address dst, Register src) { |
5362 InstructionMark im(this); | 5368 InstructionMark im(this); |
5363 prefixq(dst, src); | 5369 prefixq(dst, src); |
5364 emit_byte(0x29); | 5370 emit_int8(0x29); |
5365 emit_operand(src, dst); | 5371 emit_operand(src, dst); |
5366 } | 5372 } |
5367 | 5373 |
5368 void Assembler::subq(Register dst, int32_t imm32) { | 5374 void Assembler::subq(Register dst, int32_t imm32) { |
5369 (void) prefixq_and_encode(dst->encoding()); | 5375 (void) prefixq_and_encode(dst->encoding()); |
5377 } | 5383 } |
5378 | 5384 |
5379 void Assembler::subq(Register dst, Address src) { | 5385 void Assembler::subq(Register dst, Address src) { |
5380 InstructionMark im(this); | 5386 InstructionMark im(this); |
5381 prefixq(src, dst); | 5387 prefixq(src, dst); |
5382 emit_byte(0x2B); | 5388 emit_int8(0x2B); |
5383 emit_operand(dst, src); | 5389 emit_operand(dst, src); |
5384 } | 5390 } |
5385 | 5391 |
5386 void Assembler::subq(Register dst, Register src) { | 5392 void Assembler::subq(Register dst, Register src) { |
5387 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | 5393 (void) prefixq_and_encode(dst->encoding(), src->encoding()); |
5393 // doesn't support sign-extension of | 5399 // doesn't support sign-extension of |
5394 // 8bit operands | 5400 // 8bit operands |
5395 int encode = dst->encoding(); | 5401 int encode = dst->encoding(); |
5396 if (encode == 0) { | 5402 if (encode == 0) { |
5397 prefix(REX_W); | 5403 prefix(REX_W); |
5398 emit_byte(0xA9); | 5404 emit_int8((unsigned char)0xA9); |
5399 } else { | 5405 } else { |
5400 encode = prefixq_and_encode(encode); | 5406 encode = prefixq_and_encode(encode); |
5401 emit_byte(0xF7); | 5407 emit_int8((unsigned char)0xF7); |
5402 emit_byte(0xC0 | encode); | 5408 emit_int8((unsigned char)(0xC0 | encode)); |
5403 } | 5409 } |
5404 emit_long(imm32); | 5410 emit_long(imm32); |
5405 } | 5411 } |
5406 | 5412 |
5407 void Assembler::testq(Register dst, Register src) { | 5413 void Assembler::testq(Register dst, Register src) { |
5410 } | 5416 } |
5411 | 5417 |
5412 void Assembler::xaddq(Address dst, Register src) { | 5418 void Assembler::xaddq(Address dst, Register src) { |
5413 InstructionMark im(this); | 5419 InstructionMark im(this); |
5414 prefixq(dst, src); | 5420 prefixq(dst, src); |
5415 emit_byte(0x0F); | 5421 emit_int8(0x0F); |
5416 emit_byte(0xC1); | 5422 emit_int8((unsigned char)0xC1); |
5417 emit_operand(src, dst); | 5423 emit_operand(src, dst); |
5418 } | 5424 } |
5419 | 5425 |
5420 void Assembler::xchgq(Register dst, Address src) { | 5426 void Assembler::xchgq(Register dst, Address src) { |
5421 InstructionMark im(this); | 5427 InstructionMark im(this); |
5422 prefixq(src, dst); | 5428 prefixq(src, dst); |
5423 emit_byte(0x87); | 5429 emit_int8((unsigned char)0x87); |
5424 emit_operand(dst, src); | 5430 emit_operand(dst, src); |
5425 } | 5431 } |
5426 | 5432 |
5427 void Assembler::xchgq(Register dst, Register src) { | 5433 void Assembler::xchgq(Register dst, Register src) { |
5428 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | 5434 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
5429 emit_byte(0x87); | 5435 emit_int8((unsigned char)0x87); |
5430 emit_byte(0xc0 | encode); | 5436 emit_int8((unsigned char)(0xc0 | encode)); |
5431 } | 5437 } |
5432 | 5438 |
5433 void Assembler::xorq(Register dst, Register src) { | 5439 void Assembler::xorq(Register dst, Register src) { |
5434 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | 5440 (void) prefixq_and_encode(dst->encoding(), src->encoding()); |
5435 emit_arith(0x33, 0xC0, dst, src); | 5441 emit_arith(0x33, 0xC0, dst, src); |
5436 } | 5442 } |
5437 | 5443 |
5438 void Assembler::xorq(Register dst, Address src) { | 5444 void Assembler::xorq(Register dst, Address src) { |
5439 InstructionMark im(this); | 5445 InstructionMark im(this); |
5440 prefixq(src, dst); | 5446 prefixq(src, dst); |
5441 emit_byte(0x33); | 5447 emit_int8(0x33); |
5442 emit_operand(dst, src); | 5448 emit_operand(dst, src); |
5443 } | 5449 } |
5444 | 5450 |
5445 #endif // !LP64 | 5451 #endif // !LP64 |