truffle: src/cpu/sparc/vm/sparc.ad comparison

comparison src/cpu/sparc/vm/sparc.ad @ 18041:52b4284cb496

Merge with jdk8u20-b26

author	Gilles Duboscq <duboscq@ssw.jku.at>
date	Wed, 15 Oct 2014 16:02:50 +0200
parents	89152779163c 0bf37f737702
children	7848fc12602b

comparison

equal deleted inserted replaced

-:45d7b2c7029d
+:52b4284cb496
 //----------SOURCE BLOCK-------------------------------------------------------
 // This is a block of C++ code which provides values, functions, and
 // definitions necessary in the rest of the architecture description
 source_hpp %{
+// Header information of the source block.
+// Method declarations/definitions which are used outside
+// the ad-scope can conveniently be defined here.
+//
+// To keep related declarations/definitions/uses close together,
+// we switch between source %{ }% and source_hpp %{ }% freely as needed.
 // Must be visible to the DFA in dfa_sparc.cpp
 extern bool can_branch_register( Node *bol, Node *cmp );
 extern bool use_block_zeroing(Node* count);
 // Macros to extract hi & lo halves from a long pair.
 // G0 is not part of any long pair, so assert on that.
 // Prevents accidentally using G1 instead of G0.
 #define LONG_HI_REG(x) (x)
 #define LONG_LO_REG(x) (x)
+class CallStubImpl {
+//--------------------------------------------------------------
+//---<  Used for optimization in Compile::Shorten_branches  >---
+//--------------------------------------------------------------
+public:
+// Size of call trampoline stub.
+static uint size_call_trampoline() {
+return 0; // no call trampolines on this platform
+}
+// number of relocations needed by a call trampoline stub
+static uint reloc_call_trampoline() {
+return 0; // no call trampolines on this platform
+}
+};
+class HandlerImpl {
+public:
+static int emit_exception_handler(CodeBuffer &cbuf);
+static int emit_deopt_handler(CodeBuffer& cbuf);
+static uint size_exception_handler() {
+if (TraceJumps) {
+return (400); // just a guess
+}
+return ( NativeJump::instruction_size ); // sethi;jmp;nop
+}
+static uint size_deopt_handler() {
+if (TraceJumps) {
+return (400); // just a guess
+}
+return ( 4+  NativeJump::instruction_size ); // save;sethi;jmp;restore
+}
+};
 %}
 source %{
 #define __ _masm.
 }
 return offset;
 }
 }
+bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
+void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
+ShouldNotReachHere();
+}
 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
 Compile* C = ra_->C;
 Compile::ConstantTable& constant_table = C->constant_table();
 MacroAssembler _masm(&cbuf);
 if( VerifyThread ) {
 st->print_cr("Verify_Thread"); st->print("\t");
 }
-size_t framesize = C->frame_slots() << LogBytesPerInt;
+size_t framesize = C->frame_size_in_bytes();
+int bangsize = C->bang_size_in_bytes();
 // Calls to C2R adapters often do not accept exceptional returns.
 // We require that their callers must bang for them.  But be careful, because
 // some VM calls (such as call site linkage) can use several kilobytes of
 // stack.  But the stack safety zone should account for that.
 // See bugs 4446381, 4468289, 4497237.
-if (C->need_stack_bang(framesize)) {
+if (C->need_stack_bang(bangsize)) {
-st->print_cr("! stack bang"); st->print("\t");
+st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
 }
 if (Assembler::is_simm13(-framesize)) {
 st->print   ("SAVE   R_SP,-%d,R_SP",framesize);
 } else {
 __ nop();
 }
 __ verify_thread();
-size_t framesize = C->frame_slots() << LogBytesPerInt;
+size_t framesize = C->frame_size_in_bytes();
 assert(framesize >= 16*wordSize, "must have room for reg. save area");
 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
+int bangsize = C->bang_size_in_bytes();
 // Calls to C2R adapters often do not accept exceptional returns.
 // We require that their callers must bang for them.  But be careful, because
 // some VM calls (such as call site linkage) can use several kilobytes of
 // stack.  But the stack safety zone should account for that.
 // See bugs 4446381, 4468289, 4497237.
-if (C->need_stack_bang(framesize)) {
+if (C->need_stack_bang(bangsize)) {
-__ generate_stack_overflow_check(framesize);
+__ generate_stack_overflow_check(bangsize);
 }
 if (Assembler::is_simm13(-framesize)) {
 __ save(SP, -framesize, SP);
 } else {
 //=============================================================================
 #ifndef PRODUCT
 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
 Compile* C = ra_->C;
-if( do_polling() && ra_->C->is_method_compilation() ) {
+if(do_polling() && ra_->C->is_method_compilation()) {
 st->print("SETHI  #PollAddr,L0\t! Load Polling address\n\t");
 #ifdef _LP64
 st->print("LDX    [L0],G0\t!Poll for Safepointing\n\t");
 #else
 st->print("LDUW   [L0],G0\t!Poll for Safepointing\n\t");
 #endif
 }
-if( do_polling() )
+if(do_polling()) {
+if (UseCBCond && !ra_->C->is_method_compilation()) {
+st->print("NOP\n\t");
+}
 st->print("RET\n\t");
+}
 st->print("RESTORE");
 }
 #endif
 Compile* C = ra_->C;
 __ verify_thread();
 // If this does safepoint polling, then do it here
-if( do_polling() && ra_->C->is_method_compilation() ) {
+if(do_polling() && ra_->C->is_method_compilation()) {
 AddressLiteral polling_page(os::get_polling_page());
 __ sethi(polling_page, L0);
 __ relocate(relocInfo::poll_return_type);
-__ ld_ptr( L0, 0, G0 );
+__ ld_ptr(L0, 0, G0);
 }
 // If this is a return, then stuff the restore in the delay slot
-if( do_polling() ) {
+if(do_polling()) {
+if (UseCBCond && !ra_->C->is_method_compilation()) {
+// Insert extra padding for the case when the epilogue is preceded by
+// a cbcond jump, which can't be followed by a CTI instruction
+__ nop();
+}
 __ ret();
 __ delayed()->restore();
 } else {
 __ restore();
 }
 }
 //=============================================================================
-uint size_exception_handler() {
-if (TraceJumps) {
-return (400); // just a guess
-}
-return ( NativeJump::instruction_size ); // sethi;jmp;nop
-}
-uint size_deopt_handler() {
-if (TraceJumps) {
-return (400); // just a guess
-}
-return ( 4+  NativeJump::instruction_size ); // save;sethi;jmp;restore
-}
 // Emit exception handler code.
-int emit_exception_handler(CodeBuffer& cbuf) {
+int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
 Register temp_reg = G3;
 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
 MacroAssembler _masm(&cbuf);
 address base =
 __ end_a_stub();
 return offset;
 }
-int emit_deopt_handler(CodeBuffer& cbuf) {
+int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
 // Can't use any of the current frame's registers as we may have deopted
 // at a poll and everything (including G3) can be live.
 Register temp_reg = L0;
 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
 MacroAssembler _masm(&cbuf);
 // SPARC doesn't support misaligned vectors store/load.
 const bool Matcher::misaligned_vectors_ok() {
 return false;
 }
+// Current (2013) SPARC platforms need to read original key
+// to construct decryption expanded key
+const bool Matcher::pass_original_key_for_aes() {
+return true;
+}
 // USII supports fxtof through the whole range of number, USIII doesn't
 const bool Matcher::convL2FSupported(void) {
 return VM_Version::has_fast_fxtof();
 }
 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
 const int Matcher::float_cmove_cost() {
 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
 }
+// Does the CPU require late expand (see block.cpp for description of late expand)?
+const bool Matcher::require_postalloc_expand = false;
 // Should the Matcher clone shifts on addressing modes, expecting them to
 // be subsumed into complex addressing expressions or compute them into
 // registers?  True for Intel but false for most RISCs
 const bool Matcher::clone_shift_expressions = false;
 }
 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
 return L7_REGP_mask();
 }
-const RegMask Matcher::mathExactI_result_proj_mask() {
-return G1_REGI_mask();
-}
-const RegMask Matcher::mathExactL_result_proj_mask() {
-return G1_REGL_mask();
-}
-const RegMask Matcher::mathExactI_flags_proj_mask() {
-return INT_FLAGS_mask();
-}
 %}
 // The intptr_t operand types, defined by textual substitution.
 %}
 enc_class call_epilog %{
 if( VerifyStackAtCalls ) {
 MacroAssembler _masm(&cbuf);
-int framesize = ra_->C->frame_slots() << LogBytesPerInt;
+int framesize = ra_->C->frame_size_in_bytes();
 Register temp_reg = G3;
 __ add(SP, framesize, temp_reg);
 __ cmp(temp_reg, FP);
 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
 }
 // Body of function which returns an OptoRegs array locating
 // arguments either in registers or in stack slots for callin
 // C.
 c_calling_convention %{
 // This is obviously always outgoing
-(void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
+(void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
 %}
 // Location of native (C/C++) and interpreter return values.  This is specified to
 // be the  same as Java.  In the 32-bit VM, long values are actually returned from
 // native calls in O0:O1 and returned to the interpreter in I0:I1.  The copying
 op_attrib op_cost(1);          // Required cost attribute
 //----------Instruction Attributes---------------------------------------------
 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
 ins_attrib ins_size(32);           // Required size attribute (in bits)
-ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
+// avoid_back_to_back attribute is an expression that must return
+// one of the following values defined in MachNode:
+// AVOID_NONE   - instruction can be placed anywhere
+// AVOID_BEFORE - instruction cannot be placed after an
+//                instruction with MachNode::AVOID_AFTER
+// AVOID_AFTER  - the next instruction cannot be the one
+//                with MachNode::AVOID_BEFORE
+// AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
+//                          the same time
+ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
 ins_attrib ins_short_branch(0);    // Required flag: is this instruction a
 // non-matching short branch variant of some
 // long branch?
 //----------OPERANDS-----------------------------------------------------------
 match(Set dst (EncodeP src));
 format %{ "encode_heap_oop $src, $dst" %}
 ins_encode %{
 __ encode_heap_oop($src$$Register, $dst$$Register);
 %}
+ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
 ins_pipe(ialu_reg);
 %}
 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
 //----------MemBar Instructions-----------------------------------------------
 // Memory barrier flavors
 instruct membar_acquire() %{
 match(MemBarAcquire);
+match(LoadFence);
 ins_cost(4*MEMORY_REF_COST);
 size(0);
 format %{ "MEMBAR-acquire" %}
 ins_encode( enc_membar_acquire );
 ins_pipe(empty);
 %}
 instruct membar_release() %{
 match(MemBarRelease);
+match(StoreFence);
 ins_cost(4*MEMORY_REF_COST);
 size(0);
 format %{ "MEMBAR-release" %}
 ins_encode( enc_membar_release );
 ins_encode %{
 Label* L = $labl$$label;
 __ ba(*L);
 __ delayed()->nop();
 %}
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(br);
 %}
 // Direct Branch, short with no delay slot
 instruct branch_short(label labl) %{
 effect(USE labl);
 size(4);
 ins_cost(BRANCH_COST);
 format %{ "BA     $labl\t! short branch" %}
 ins_encode %{
 Label* L = $labl$$label;
 assert(__ use_cbcond(*L), "back to back cbcond");
 __ ba_short(*L);
 %}
 ins_short_branch(1);
-ins_avoid_back_to_back(1);
+ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
 ins_pipe(cbcond_reg_imm);
 %}
 // Conditional Direct Branch
 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "BP$cmp   $icc,$labl" %}
 // Prim = bits 24-22, Secnd = bits 31-30
 ins_encode( enc_bp( labl, cmp, icc ) );
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(br_cc);
 %}
 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
 match(If cmp icc);
 ins_cost(BRANCH_COST);
 format %{ "BP$cmp  $icc,$labl" %}
 // Prim = bits 24-22, Secnd = bits 31-30
 ins_encode( enc_bp( labl, cmp, icc ) );
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(br_cc);
 %}
 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
 match(If cmp pcc);
 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
 __ delayed()->nop();
 %}
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(br_cc);
 %}
 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
 match(If cmp fcc);
 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
 __ delayed()->nop();
 %}
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(br_fcc);
 %}
 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
 match(CountedLoopEnd cmp icc);
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "BP$cmp   $icc,$labl\t! Loop end" %}
 // Prim = bits 24-22, Secnd = bits 31-30
 ins_encode( enc_bp( labl, cmp, icc ) );
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(br_cc);
 %}
 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
 match(CountedLoopEnd cmp icc);
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "BP$cmp  $icc,$labl\t! Loop end" %}
 // Prim = bits 24-22, Secnd = bits 31-30
 ins_encode( enc_bp( labl, cmp, icc ) );
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(br_cc);
 %}
 // Compare and branch instructions
 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
 Label* L = $labl$$label;
 assert(__ use_cbcond(*L), "back to back cbcond");
 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
 %}
 ins_short_branch(1);
-ins_avoid_back_to_back(1);
+ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
 ins_pipe(cbcond_reg_reg);
 %}
 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
 match(If cmp (CmpI op1 op2));
 Label* L = $labl$$label;
 assert(__ use_cbcond(*L), "back to back cbcond");
 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
 %}
 ins_short_branch(1);
-ins_avoid_back_to_back(1);
+ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
 ins_pipe(cbcond_reg_imm);
 %}
 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
 match(If cmp (CmpU op1 op2));
 Label* L = $labl$$label;
 assert(__ use_cbcond(*L), "back to back cbcond");
 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
 %}
 ins_short_branch(1);
-ins_avoid_back_to_back(1);
+ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
 ins_pipe(cbcond_reg_reg);
 %}
 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
 match(If cmp (CmpU op1 op2));
 Label* L = $labl$$label;
 assert(__ use_cbcond(*L), "back to back cbcond");
 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
 %}
 ins_short_branch(1);
-ins_avoid_back_to_back(1);
+ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
 ins_pipe(cbcond_reg_imm);
 %}
 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
 match(If cmp (CmpL op1 op2));
 Label* L = $labl$$label;
 assert(__ use_cbcond(*L), "back to back cbcond");
 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
 %}
 ins_short_branch(1);
-ins_avoid_back_to_back(1);
+ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
 ins_pipe(cbcond_reg_reg);
 %}
 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
 match(If cmp (CmpL op1 op2));
 Label* L = $labl$$label;
 assert(__ use_cbcond(*L), "back to back cbcond");
 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
 %}
 ins_short_branch(1);
-ins_avoid_back_to_back(1);
+ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
 ins_pipe(cbcond_reg_imm);
 %}
 // Compare Pointers and branch
 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
 Label* L = $labl$$label;
 assert(__ use_cbcond(*L), "back to back cbcond");
 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
 %}
 ins_short_branch(1);
-ins_avoid_back_to_back(1);
+ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
 ins_pipe(cbcond_reg_reg);
 %}
 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
 match(If cmp (CmpP op1 null));
 Label* L = $labl$$label;
 assert(__ use_cbcond(*L), "back to back cbcond");
 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
 %}
 ins_short_branch(1);
-ins_avoid_back_to_back(1);
+ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
 ins_pipe(cbcond_reg_reg);
 %}
 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
 match(If cmp (CmpN op1 op2));
 Label* L = $labl$$label;
 assert(__ use_cbcond(*L), "back to back cbcond");
 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
 %}
 ins_short_branch(1);
-ins_avoid_back_to_back(1);
+ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
 ins_pipe(cbcond_reg_reg);
 %}
 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
 match(If cmp (CmpN op1 null));
 Label* L = $labl$$label;
 assert(__ use_cbcond(*L), "back to back cbcond");
 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
 %}
 ins_short_branch(1);
-ins_avoid_back_to_back(1);
+ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
 ins_pipe(cbcond_reg_reg);
 %}
 // Loop back branch
 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
 Label* L = $labl$$label;
 assert(__ use_cbcond(*L), "back to back cbcond");
 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
 %}
 ins_short_branch(1);
-ins_avoid_back_to_back(1);
+ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
 ins_pipe(cbcond_reg_reg);
 %}
 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
 match(CountedLoopEnd cmp (CmpI op1 op2));
 Label* L = $labl$$label;
 assert(__ use_cbcond(*L), "back to back cbcond");
 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
 %}
 ins_short_branch(1);
-ins_avoid_back_to_back(1);
+ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
 ins_pipe(cbcond_reg_imm);
 %}
 // Branch-on-register tests all 64 bits.  We assume that values
 // in 64-bit registers always remains zero or sign extended
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "BR$cmp   $op1,$labl" %}
 ins_encode( enc_bpr( labl, cmp, op1 ) );
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(br_reg);
 %}
 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
 match(If cmp (CmpP op1 null));
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "BR$cmp   $op1,$labl" %}
 ins_encode( enc_bpr( labl, cmp, op1 ) );
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(br_reg);
 %}
 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
 match(If cmp (CmpL op1 zero));
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "BR$cmp   $op1,$labl" %}
 ins_encode( enc_bpr( labl, cmp, op1 ) );
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(br_reg);
 %}
 // ============================================================================
 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
 __ delayed()->nop();
 %}
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(br_cc);
 %}
 // Manifest a CmpL3 result in an integer register.  Very painful.
 // This is the test to avoid.
 size(8);
 ins_cost(CALL_COST);
 format %{ "CALL,static  ; NOP ==> " %}
 ins_encode( Java_Static_Call( meth ), call_epilog );
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(simple_call);
 %}
 // Call Java Static Instruction (method handle version)
 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
 effect(USE meth, KILL l7);
 ins_cost(CALL_COST);
 format %{ "CALL,runtime" %}
 ins_encode( Java_To_Runtime( meth ),
 call_epilog, adjust_long_from_native_call );
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(simple_call);
 %}
 // Call runtime without safepoint - same as CallRuntime
 instruct CallLeafDirect(method meth, l7RegP l7) %{
 ins_cost(CALL_COST);
 format %{ "CALL,runtime leaf" %}
 ins_encode( Java_To_Runtime( meth ),
 call_epilog,
 adjust_long_from_native_call );
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(simple_call);
 %}
 // Call runtime without safepoint - same as CallLeaf
 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
 ins_cost(CALL_COST);
 format %{ "CALL,runtime leaf nofp" %}
 ins_encode( Java_To_Runtime( meth ),
 call_epilog,
 adjust_long_from_native_call );
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(simple_call);
 %}
 // Tail Call; Jump from runtime stub to Java code.
 // Also known as an 'interprocedural jump'.
 match(TailCall jump_target method_oop );
 ins_cost(CALL_COST);
 format %{ "Jmp     $jump_target  ; NOP \t! $method_oop holds method oop" %}
 ins_encode(form_jmpl(jump_target));
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(tail_call);
 %}
 // Return Instruction
 "Jmp     $jump_target  ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
 ins_encode(form_jmpl_set_exception_pc(jump_target));
 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(tail_call);
 %}
 // Create exception oop: created by stack-crawling runtime code.
 // Created exception is now available to this handler, and is setup
 ins_cost(CALL_COST);
 // use the following format syntax
 format %{ "Jmp    rethrow_stub" %}
 ins_encode(enc_rethrow);
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(tail_call);
 %}
 // Die now
 match(Set index (PartialSubtypeCheck sub super));
 effect( KILL pcc, KILL o7 );
 ins_cost(DEFAULT_COST*10);
 format %{ "CALL   PartialSubtypeCheck\n\tNOP" %}
 ins_encode( enc_PartialSubtypeCheck() );
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(partial_subtype_check_pipe);
 %}
 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
 effect( KILL idx, KILL o7 );
 ins_cost(DEFAULT_COST*10);
 format %{ "CALL   PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
 ins_encode( enc_PartialSubtypeCheck() );
+ins_avoid_back_to_back(AVOID_BEFORE);
 ins_pipe(partial_subtype_check_pipe);
 %}
 // ============================================================================

Mercurial > hg > truffle

comparison src/cpu/sparc/vm/sparc.ad @ 18041:52b4284cb496