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comparison src/cpu/x86/vm/x86_32.ad @ 12972:59e8ad757e19

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8026844: Various Math functions needs intrinsification Reviewed-by: kvn, twisti
author rbackman
date Fri, 18 Oct 2013 10:41:56 +0200
parents 268e7a2178d7
children 7e8bd81ce93e 2b8e28fdf503
comparison
equal deleted inserted replaced
12971:3a04e444da6d 12972:59e8ad757e19
1536 1536
1537 const RegMask Matcher::mathExactI_result_proj_mask() { 1537 const RegMask Matcher::mathExactI_result_proj_mask() {
1538 return EAX_REG_mask(); 1538 return EAX_REG_mask();
1539 } 1539 }
1540 1540
1541 const RegMask Matcher::mathExactL_result_proj_mask() {
1542 ShouldNotReachHere();
1543 return RegMask();
1544 }
1545
1541 const RegMask Matcher::mathExactI_flags_proj_mask() { 1546 const RegMask Matcher::mathExactI_flags_proj_mask() {
1542 return INT_FLAGS_mask(); 1547 return INT_FLAGS_mask();
1543 } 1548 }
1544 1549
1545 // Returns true if the high 32 bits of the value is known to be zero. 1550 // Returns true if the high 32 bits of the value is known to be zero.
7517 %} 7522 %}
7518 7523
7519 //----------Arithmetic Instructions-------------------------------------------- 7524 //----------Arithmetic Instructions--------------------------------------------
7520 //----------Addition Instructions---------------------------------------------- 7525 //----------Addition Instructions----------------------------------------------
7521 7526
7522 instruct addExactI_rReg(eAXRegI dst, rRegI src, eFlagsReg cr) 7527 instruct addExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7523 %{ 7528 %{
7524 match(AddExactI dst src); 7529 match(AddExactI dst src);
7525 effect(DEF cr); 7530 effect(DEF cr);
7526 7531
7527 format %{ "ADD $dst, $src\t# addExact int" %} 7532 format %{ "ADD $dst, $src\t# addExact int" %}
7529 __ addl($dst$$Register, $src$$Register); 7534 __ addl($dst$$Register, $src$$Register);
7530 %} 7535 %}
7531 ins_pipe(ialu_reg_reg); 7536 ins_pipe(ialu_reg_reg);
7532 %} 7537 %}
7533 7538
7534 instruct addExactI_rReg_imm(eAXRegI dst, immI src, eFlagsReg cr) 7539 instruct addExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7535 %{ 7540 %{
7536 match(AddExactI dst src); 7541 match(AddExactI dst src);
7537 effect(DEF cr); 7542 effect(DEF cr);
7538 7543
7539 format %{ "ADD $dst, $src\t# addExact int" %} 7544 format %{ "ADD $dst, $src\t# addExact int" %}
7540 ins_encode %{ 7545 ins_encode %{
7541 __ addl($dst$$Register, $src$$constant); 7546 __ addl($dst$$Register, $src$$constant);
7542 %} 7547 %}
7543 ins_pipe(ialu_reg_reg); 7548 ins_pipe(ialu_reg_reg);
7544 %} 7549 %}
7550
7551 instruct addExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7552 %{
7553 match(AddExactI dst (LoadI src));
7554 effect(DEF cr);
7555
7556 ins_cost(125);
7557 format %{ "ADD $dst,$src\t# addExact int" %}
7558 ins_encode %{
7559 __ addl($dst$$Register, $src$$Address);
7560 %}
7561 ins_pipe( ialu_reg_mem );
7562 %}
7563
7545 7564
7546 // Integer Addition Instructions 7565 // Integer Addition Instructions
7547 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ 7566 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7548 match(Set dst (AddI dst src)); 7567 match(Set dst (AddI dst src));
7549 effect(KILL cr); 7568 effect(KILL cr);
7849 %} 7868 %}
7850 ins_pipe( pipe_cmpxchg ); 7869 ins_pipe( pipe_cmpxchg );
7851 %} 7870 %}
7852 7871
7853 //----------Subtraction Instructions------------------------------------------- 7872 //----------Subtraction Instructions-------------------------------------------
7873
7874 instruct subExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7875 %{
7876 match(SubExactI dst src);
7877 effect(DEF cr);
7878
7879 format %{ "SUB $dst, $src\t# subExact int" %}
7880 ins_encode %{
7881 __ subl($dst$$Register, $src$$Register);
7882 %}
7883 ins_pipe(ialu_reg_reg);
7884 %}
7885
7886 instruct subExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7887 %{
7888 match(SubExactI dst src);
7889 effect(DEF cr);
7890
7891 format %{ "SUB $dst, $src\t# subExact int" %}
7892 ins_encode %{
7893 __ subl($dst$$Register, $src$$constant);
7894 %}
7895 ins_pipe(ialu_reg_reg);
7896 %}
7897
7898 instruct subExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7899 %{
7900 match(SubExactI dst (LoadI src));
7901 effect(DEF cr);
7902
7903 ins_cost(125);
7904 format %{ "SUB $dst,$src\t# subExact int" %}
7905 ins_encode %{
7906 __ subl($dst$$Register, $src$$Address);
7907 %}
7908 ins_pipe( ialu_reg_mem );
7909 %}
7910
7854 // Integer Subtraction Instructions 7911 // Integer Subtraction Instructions
7855 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ 7912 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7856 match(Set dst (SubI dst src)); 7913 match(Set dst (SubI dst src));
7857 effect(KILL cr); 7914 effect(KILL cr);
7858 7915
7917 opcode(0xF7,0x03); // Opcode F7 /3 7974 opcode(0xF7,0x03); // Opcode F7 /3
7918 ins_encode( OpcP, RegOpc( dst ) ); 7975 ins_encode( OpcP, RegOpc( dst ) );
7919 ins_pipe( ialu_reg ); 7976 ins_pipe( ialu_reg );
7920 %} 7977 %}
7921 7978
7979 instruct negExactI_eReg(eAXRegI dst, eFlagsReg cr) %{
7980 match(NegExactI dst);
7981 effect(DEF cr);
7982
7983 format %{ "NEG $dst\t# negExact int"%}
7984 ins_encode %{
7985 __ negl($dst$$Register);
7986 %}
7987 ins_pipe(ialu_reg);
7988 %}
7922 7989
7923 //----------Multiplication/Division Instructions------------------------------- 7990 //----------Multiplication/Division Instructions-------------------------------
7924 // Integer Multiplication Instructions 7991 // Integer Multiplication Instructions
7925 // Multiply Register 7992 // Multiply Register
7926 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ 7993 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8128 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" 8195 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8129 "ADD EDX,$tmp" %} 8196 "ADD EDX,$tmp" %}
8130 ins_encode( long_multiply_con( dst, src, tmp ) ); 8197 ins_encode( long_multiply_con( dst, src, tmp ) );
8131 ins_pipe( pipe_slow ); 8198 ins_pipe( pipe_slow );
8132 %} 8199 %}
8200
8201 instruct mulExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
8202 %{
8203 match(MulExactI dst src);
8204 effect(DEF cr);
8205
8206 ins_cost(300);
8207 format %{ "IMUL $dst, $src\t# mulExact int" %}
8208 ins_encode %{
8209 __ imull($dst$$Register, $src$$Register);
8210 %}
8211 ins_pipe(ialu_reg_reg_alu0);
8212 %}
8213
8214 instruct mulExactI_eReg_imm(eAXRegI dst, rRegI src, immI imm, eFlagsReg cr)
8215 %{
8216 match(MulExactI src imm);
8217 effect(DEF cr);
8218
8219 ins_cost(300);
8220 format %{ "IMUL $dst, $src, $imm\t# mulExact int" %}
8221 ins_encode %{
8222 __ imull($dst$$Register, $src$$Register, $imm$$constant);
8223 %}
8224 ins_pipe(ialu_reg_reg_alu0);
8225 %}
8226
8227 instruct mulExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
8228 %{
8229 match(MulExactI dst (LoadI src));
8230 effect(DEF cr);
8231
8232 ins_cost(350);
8233 format %{ "IMUL $dst, $src\t# mulExact int" %}
8234 ins_encode %{
8235 __ imull($dst$$Register, $src$$Address);
8236 %}
8237 ins_pipe(ialu_reg_mem_alu0);
8238 %}
8239
8133 8240
8134 // Integer DIV with Register 8241 // Integer DIV with Register
8135 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ 8242 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8136 match(Set rax (DivI rax div)); 8243 match(Set rax (DivI rax div));
8137 effect(KILL rdx, KILL cr); 8244 effect(KILL rdx, KILL cr);