Mercurial > hg > truffle
comparison src/cpu/x86/vm/x86_64.ad @ 642:660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
Summary: Use zero based compressed oops if java heap is below 32gb and unscaled compressed oops if java heap is below 4gb.
Reviewed-by: never, twisti, jcoomes, coleenp
author | kvn |
---|---|
date | Thu, 12 Mar 2009 10:37:46 -0700 |
parents | 337400e7a5dd |
children | c771b7f43bbf |
comparison
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inserted
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641:6af0a709d52b | 642:660978a2a31a |
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324 RBX, RBX_H, | 324 RBX, RBX_H, |
325 R8, R8_H, | 325 R8, R8_H, |
326 R9, R9_H, | 326 R9, R9_H, |
327 R10, R10_H, | 327 R10, R10_H, |
328 R11, R11_H, | 328 R11, R11_H, |
329 R12, R12_H, | |
330 R13, R13_H, | 329 R13, R13_H, |
331 R14, R14_H); | 330 R14, R14_H); |
332 | 331 |
333 reg_class ptr_no_rbp_reg(RDX, RDX_H, | 332 reg_class ptr_no_rbp_reg(RDX, RDX_H, |
334 RAX, RAX_H, | 333 RAX, RAX_H, |
338 RBX, RBX_H, | 337 RBX, RBX_H, |
339 R8, R8_H, | 338 R8, R8_H, |
340 R9, R9_H, | 339 R9, R9_H, |
341 R10, R10_H, | 340 R10, R10_H, |
342 R11, R11_H, | 341 R11, R11_H, |
343 R12, R12_H, | |
344 R13, R13_H, | 342 R13, R13_H, |
345 R14, R14_H); | 343 R14, R14_H); |
346 | 344 |
347 // Class for all pointer registers except RAX, RBX and RSP | 345 // Class for all pointer registers except RAX, RBX and RSP |
348 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H, | 346 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H, |
352 RCX, RCX_H, | 350 RCX, RCX_H, |
353 R8, R8_H, | 351 R8, R8_H, |
354 R9, R9_H, | 352 R9, R9_H, |
355 R10, R10_H, | 353 R10, R10_H, |
356 R11, R11_H, | 354 R11, R11_H, |
357 R12, R12_H, | |
358 R13, R13_H, | 355 R13, R13_H, |
359 R14, R14_H); | 356 R14, R14_H); |
360 | 357 |
361 // Singleton class for RAX pointer register | 358 // Singleton class for RAX pointer register |
362 reg_class ptr_rax_reg(RAX, RAX_H); | 359 reg_class ptr_rax_reg(RAX, RAX_H); |
441 // Singleton class for RCX long register | 438 // Singleton class for RCX long register |
442 reg_class long_rcx_reg(RCX, RCX_H); | 439 reg_class long_rcx_reg(RCX, RCX_H); |
443 | 440 |
444 // Singleton class for RDX long register | 441 // Singleton class for RDX long register |
445 reg_class long_rdx_reg(RDX, RDX_H); | 442 reg_class long_rdx_reg(RDX, RDX_H); |
446 | |
447 // Singleton class for R12 long register | |
448 reg_class long_r12_reg(R12, R12_H); | |
449 | 443 |
450 // Class for all int registers (except RSP) | 444 // Class for all int registers (except RSP) |
451 reg_class int_reg(RAX, | 445 reg_class int_reg(RAX, |
452 RDX, | 446 RDX, |
453 RBP, | 447 RBP, |
1840 #ifndef PRODUCT | 1834 #ifndef PRODUCT |
1841 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const | 1835 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const |
1842 { | 1836 { |
1843 if (UseCompressedOops) { | 1837 if (UseCompressedOops) { |
1844 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t", oopDesc::klass_offset_in_bytes()); | 1838 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t", oopDesc::klass_offset_in_bytes()); |
1845 st->print_cr("leaq rscratch1, [r12_heapbase, r, Address::times_8, 0]"); | 1839 if (Universe::narrow_oop_shift() != 0) { |
1840 st->print_cr("leaq rscratch1, [r12_heapbase, r, Address::times_8, 0]"); | |
1841 } | |
1846 st->print_cr("cmpq rax, rscratch1\t # Inline cache check"); | 1842 st->print_cr("cmpq rax, rscratch1\t # Inline cache check"); |
1847 } else { | 1843 } else { |
1848 st->print_cr("cmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t" | 1844 st->print_cr("cmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t" |
1849 "# Inline cache check", oopDesc::klass_offset_in_bytes()); | 1845 "# Inline cache check", oopDesc::klass_offset_in_bytes()); |
1850 } | 1846 } |
1889 } | 1885 } |
1890 | 1886 |
1891 uint MachUEPNode::size(PhaseRegAlloc* ra_) const | 1887 uint MachUEPNode::size(PhaseRegAlloc* ra_) const |
1892 { | 1888 { |
1893 if (UseCompressedOops) { | 1889 if (UseCompressedOops) { |
1894 return OptoBreakpoint ? 19 : 20; | 1890 if (Universe::narrow_oop_shift() == 0) { |
1891 return OptoBreakpoint ? 15 : 16; | |
1892 } else { | |
1893 return OptoBreakpoint ? 19 : 20; | |
1894 } | |
1895 } else { | 1895 } else { |
1896 return OptoBreakpoint ? 11 : 12; | 1896 return OptoBreakpoint ? 11 : 12; |
1897 } | 1897 } |
1898 } | 1898 } |
1899 | 1899 |
2591 sizeof(oopDesc) + | 2591 sizeof(oopDesc) + |
2592 Klass::secondary_supers_offset_in_bytes())); | 2592 Klass::secondary_supers_offset_in_bytes())); |
2593 __ movl(Rrcx, Address(Rrdi, arrayOopDesc::length_offset_in_bytes())); | 2593 __ movl(Rrcx, Address(Rrdi, arrayOopDesc::length_offset_in_bytes())); |
2594 __ addptr(Rrdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); | 2594 __ addptr(Rrdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); |
2595 if (UseCompressedOops) { | 2595 if (UseCompressedOops) { |
2596 __ push(Rrax); | |
2596 __ encode_heap_oop(Rrax); | 2597 __ encode_heap_oop(Rrax); |
2597 __ repne_scanl(); | 2598 __ repne_scanl(); |
2598 __ jcc(Assembler::notEqual, cmiss); | 2599 __ pop(Rrax); |
2599 __ decode_heap_oop(Rrax); | 2600 __ jccb(Assembler::notEqual, miss); |
2600 __ movptr(Address(Rrsi, | 2601 __ movptr(Address(Rrsi, |
2601 sizeof(oopDesc) + | 2602 sizeof(oopDesc) + |
2602 Klass::secondary_super_cache_offset_in_bytes()), | 2603 Klass::secondary_super_cache_offset_in_bytes()), |
2603 Rrax); | 2604 Rrax); |
2604 __ jmp(hit); | 2605 __ jmp(hit); |
2605 __ bind(cmiss); | |
2606 __ decode_heap_oop(Rrax); | |
2607 __ jmp(miss); | |
2608 } else { | 2606 } else { |
2609 __ repne_scan(); | 2607 __ repne_scan(); |
2610 __ jcc(Assembler::notEqual, miss); | 2608 __ jccb(Assembler::notEqual, miss); |
2611 __ movptr(Address(Rrsi, | 2609 __ movptr(Address(Rrsi, |
2612 sizeof(oopDesc) + | 2610 sizeof(oopDesc) + |
2613 Klass::secondary_super_cache_offset_in_bytes()), | 2611 Klass::secondary_super_cache_offset_in_bytes()), |
2614 Rrax); | 2612 Rrax); |
2615 } | 2613 } |
4904 | 4902 |
4905 format %{ %} | 4903 format %{ %} |
4906 interface(REG_INTER); | 4904 interface(REG_INTER); |
4907 %} | 4905 %} |
4908 | 4906 |
4909 | |
4910 operand r12RegL() %{ | |
4911 constraint(ALLOC_IN_RC(long_r12_reg)); | |
4912 match(RegL); | |
4913 | |
4914 format %{ %} | |
4915 interface(REG_INTER); | |
4916 %} | |
4917 | |
4918 operand rRegN() %{ | 4907 operand rRegN() %{ |
4919 constraint(ALLOC_IN_RC(int_reg)); | 4908 constraint(ALLOC_IN_RC(int_reg)); |
4920 match(RegN); | 4909 match(RegN); |
4921 | 4910 |
4922 format %{ %} | 4911 format %{ %} |
5287 scale($scale); | 5276 scale($scale); |
5288 disp($off); | 5277 disp($off); |
5289 %} | 5278 %} |
5290 %} | 5279 %} |
5291 | 5280 |
5292 // Indirect Narrow Oop Plus Offset Operand | |
5293 operand indNarrowOopOffset(rRegN src, immL32 off) %{ | |
5294 constraint(ALLOC_IN_RC(ptr_reg)); | |
5295 match(AddP (DecodeN src) off); | |
5296 | |
5297 op_cost(10); | |
5298 format %{"[R12 + $src << 3 + $off] (compressed oop addressing)" %} | |
5299 interface(MEMORY_INTER) %{ | |
5300 base(0xc); // R12 | |
5301 index($src); | |
5302 scale(0x3); | |
5303 disp($off); | |
5304 %} | |
5305 %} | |
5306 | |
5307 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand | 5281 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
5308 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) | 5282 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) |
5309 %{ | 5283 %{ |
5310 constraint(ALLOC_IN_RC(ptr_reg)); | 5284 constraint(ALLOC_IN_RC(ptr_reg)); |
5311 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); | 5285 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
5318 index($idx); | 5292 index($idx); |
5319 scale($scale); | 5293 scale($scale); |
5320 disp($off); | 5294 disp($off); |
5321 %} | 5295 %} |
5322 %} | 5296 %} |
5297 | |
5298 // Indirect Narrow Oop Plus Offset Operand | |
5299 // Note: x86 architecture doesn't support "scale * index + offset" without a base | |
5300 // we can't free r12 even with Universe::narrow_oop_base() == NULL. | |
5301 operand indCompressedOopOffset(rRegN reg, immL32 off) %{ | |
5302 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0)); | |
5303 constraint(ALLOC_IN_RC(ptr_reg)); | |
5304 match(AddP (DecodeN reg) off); | |
5305 | |
5306 op_cost(10); | |
5307 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %} | |
5308 interface(MEMORY_INTER) %{ | |
5309 base(0xc); // R12 | |
5310 index($reg); | |
5311 scale(0x3); | |
5312 disp($off); | |
5313 %} | |
5314 %} | |
5315 | |
5316 // Indirect Memory Operand | |
5317 operand indirectNarrow(rRegN reg) | |
5318 %{ | |
5319 predicate(Universe::narrow_oop_shift() == 0); | |
5320 constraint(ALLOC_IN_RC(ptr_reg)); | |
5321 match(DecodeN reg); | |
5322 | |
5323 format %{ "[$reg]" %} | |
5324 interface(MEMORY_INTER) %{ | |
5325 base($reg); | |
5326 index(0x4); | |
5327 scale(0x0); | |
5328 disp(0x0); | |
5329 %} | |
5330 %} | |
5331 | |
5332 // Indirect Memory Plus Short Offset Operand | |
5333 operand indOffset8Narrow(rRegN reg, immL8 off) | |
5334 %{ | |
5335 predicate(Universe::narrow_oop_shift() == 0); | |
5336 constraint(ALLOC_IN_RC(ptr_reg)); | |
5337 match(AddP (DecodeN reg) off); | |
5338 | |
5339 format %{ "[$reg + $off (8-bit)]" %} | |
5340 interface(MEMORY_INTER) %{ | |
5341 base($reg); | |
5342 index(0x4); | |
5343 scale(0x0); | |
5344 disp($off); | |
5345 %} | |
5346 %} | |
5347 | |
5348 // Indirect Memory Plus Long Offset Operand | |
5349 operand indOffset32Narrow(rRegN reg, immL32 off) | |
5350 %{ | |
5351 predicate(Universe::narrow_oop_shift() == 0); | |
5352 constraint(ALLOC_IN_RC(ptr_reg)); | |
5353 match(AddP (DecodeN reg) off); | |
5354 | |
5355 format %{ "[$reg + $off (32-bit)]" %} | |
5356 interface(MEMORY_INTER) %{ | |
5357 base($reg); | |
5358 index(0x4); | |
5359 scale(0x0); | |
5360 disp($off); | |
5361 %} | |
5362 %} | |
5363 | |
5364 // Indirect Memory Plus Index Register Plus Offset Operand | |
5365 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off) | |
5366 %{ | |
5367 predicate(Universe::narrow_oop_shift() == 0); | |
5368 constraint(ALLOC_IN_RC(ptr_reg)); | |
5369 match(AddP (AddP (DecodeN reg) lreg) off); | |
5370 | |
5371 op_cost(10); | |
5372 format %{"[$reg + $off + $lreg]" %} | |
5373 interface(MEMORY_INTER) %{ | |
5374 base($reg); | |
5375 index($lreg); | |
5376 scale(0x0); | |
5377 disp($off); | |
5378 %} | |
5379 %} | |
5380 | |
5381 // Indirect Memory Plus Index Register Plus Offset Operand | |
5382 operand indIndexNarrow(rRegN reg, rRegL lreg) | |
5383 %{ | |
5384 predicate(Universe::narrow_oop_shift() == 0); | |
5385 constraint(ALLOC_IN_RC(ptr_reg)); | |
5386 match(AddP (DecodeN reg) lreg); | |
5387 | |
5388 op_cost(10); | |
5389 format %{"[$reg + $lreg]" %} | |
5390 interface(MEMORY_INTER) %{ | |
5391 base($reg); | |
5392 index($lreg); | |
5393 scale(0x0); | |
5394 disp(0x0); | |
5395 %} | |
5396 %} | |
5397 | |
5398 // Indirect Memory Times Scale Plus Index Register | |
5399 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale) | |
5400 %{ | |
5401 predicate(Universe::narrow_oop_shift() == 0); | |
5402 constraint(ALLOC_IN_RC(ptr_reg)); | |
5403 match(AddP (DecodeN reg) (LShiftL lreg scale)); | |
5404 | |
5405 op_cost(10); | |
5406 format %{"[$reg + $lreg << $scale]" %} | |
5407 interface(MEMORY_INTER) %{ | |
5408 base($reg); | |
5409 index($lreg); | |
5410 scale($scale); | |
5411 disp(0x0); | |
5412 %} | |
5413 %} | |
5414 | |
5415 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
5416 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale) | |
5417 %{ | |
5418 predicate(Universe::narrow_oop_shift() == 0); | |
5419 constraint(ALLOC_IN_RC(ptr_reg)); | |
5420 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off); | |
5421 | |
5422 op_cost(10); | |
5423 format %{"[$reg + $off + $lreg << $scale]" %} | |
5424 interface(MEMORY_INTER) %{ | |
5425 base($reg); | |
5426 index($lreg); | |
5427 scale($scale); | |
5428 disp($off); | |
5429 %} | |
5430 %} | |
5431 | |
5432 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand | |
5433 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale) | |
5434 %{ | |
5435 constraint(ALLOC_IN_RC(ptr_reg)); | |
5436 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); | |
5437 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off); | |
5438 | |
5439 op_cost(10); | |
5440 format %{"[$reg + $off + $idx << $scale]" %} | |
5441 interface(MEMORY_INTER) %{ | |
5442 base($reg); | |
5443 index($idx); | |
5444 scale($scale); | |
5445 disp($off); | |
5446 %} | |
5447 %} | |
5448 | |
5323 | 5449 |
5324 //----------Special Memory Operands-------------------------------------------- | 5450 //----------Special Memory Operands-------------------------------------------- |
5325 // Stack Slot Operand - This operand is used for loading and storing temporary | 5451 // Stack Slot Operand - This operand is used for loading and storing temporary |
5326 // values on the stack where a match requires a value to | 5452 // values on the stack where a match requires a value to |
5327 // flow through memory. | 5453 // flow through memory. |
5486 // multiple operand types with the same basic encoding and format. The classic | 5612 // multiple operand types with the same basic encoding and format. The classic |
5487 // case of this is memory operands. | 5613 // case of this is memory operands. |
5488 | 5614 |
5489 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, | 5615 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, |
5490 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, | 5616 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
5491 indNarrowOopOffset); | 5617 indCompressedOopOffset, |
5618 indirectNarrow, indOffset8Narrow, indOffset32Narrow, | |
5619 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, | |
5620 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow); | |
5492 | 5621 |
5493 //----------PIPELINE----------------------------------------------------------- | 5622 //----------PIPELINE----------------------------------------------------------- |
5494 // Rules which define the behavior of the target architectures pipeline. | 5623 // Rules which define the behavior of the target architectures pipeline. |
5495 pipeline %{ | 5624 pipeline %{ |
5496 | 5625 |
6232 match(Set dst (LoadN mem)); | 6361 match(Set dst (LoadN mem)); |
6233 | 6362 |
6234 ins_cost(125); // XXX | 6363 ins_cost(125); // XXX |
6235 format %{ "movl $dst, $mem\t# compressed ptr" %} | 6364 format %{ "movl $dst, $mem\t# compressed ptr" %} |
6236 ins_encode %{ | 6365 ins_encode %{ |
6237 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); | 6366 __ movl($dst$$Register, $mem$$Address); |
6238 Register dst = as_Register($dst$$reg); | |
6239 __ movl(dst, addr); | |
6240 %} | 6367 %} |
6241 ins_pipe(ialu_reg_mem); // XXX | 6368 ins_pipe(ialu_reg_mem); // XXX |
6242 %} | 6369 %} |
6243 | 6370 |
6244 | 6371 |
6260 match(Set dst (LoadNKlass mem)); | 6387 match(Set dst (LoadNKlass mem)); |
6261 | 6388 |
6262 ins_cost(125); // XXX | 6389 ins_cost(125); // XXX |
6263 format %{ "movl $dst, $mem\t# compressed klass ptr" %} | 6390 format %{ "movl $dst, $mem\t# compressed klass ptr" %} |
6264 ins_encode %{ | 6391 ins_encode %{ |
6265 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); | 6392 __ movl($dst$$Register, $mem$$Address); |
6266 Register dst = as_Register($dst$$reg); | |
6267 __ movl(dst, addr); | |
6268 %} | 6393 %} |
6269 ins_pipe(ialu_reg_mem); // XXX | 6394 ins_pipe(ialu_reg_mem); // XXX |
6270 %} | 6395 %} |
6271 | 6396 |
6272 // Load Float | 6397 // Load Float |
6416 opcode(0x8D); | 6541 opcode(0x8D); |
6417 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | 6542 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
6418 ins_pipe(ialu_reg_reg_fat); | 6543 ins_pipe(ialu_reg_reg_fat); |
6419 %} | 6544 %} |
6420 | 6545 |
6546 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) | |
6547 %{ | |
6548 match(Set dst mem); | |
6549 | |
6550 ins_cost(110); | |
6551 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %} | |
6552 opcode(0x8D); | |
6553 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6554 ins_pipe(ialu_reg_reg_fat); | |
6555 %} | |
6556 | |
6557 // Load Effective Address which uses Narrow (32-bits) oop | |
6558 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem) | |
6559 %{ | |
6560 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0)); | |
6561 match(Set dst mem); | |
6562 | |
6563 ins_cost(110); | |
6564 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %} | |
6565 opcode(0x8D); | |
6566 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6567 ins_pipe(ialu_reg_reg_fat); | |
6568 %} | |
6569 | |
6570 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem) | |
6571 %{ | |
6572 predicate(Universe::narrow_oop_shift() == 0); | |
6573 match(Set dst mem); | |
6574 | |
6575 ins_cost(110); // XXX | |
6576 format %{ "leaq $dst, $mem\t# ptr off8narrow" %} | |
6577 opcode(0x8D); | |
6578 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6579 ins_pipe(ialu_reg_reg_fat); | |
6580 %} | |
6581 | |
6582 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem) | |
6583 %{ | |
6584 predicate(Universe::narrow_oop_shift() == 0); | |
6585 match(Set dst mem); | |
6586 | |
6587 ins_cost(110); | |
6588 format %{ "leaq $dst, $mem\t# ptr off32narrow" %} | |
6589 opcode(0x8D); | |
6590 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6591 ins_pipe(ialu_reg_reg_fat); | |
6592 %} | |
6593 | |
6594 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem) | |
6595 %{ | |
6596 predicate(Universe::narrow_oop_shift() == 0); | |
6597 match(Set dst mem); | |
6598 | |
6599 ins_cost(110); | |
6600 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %} | |
6601 opcode(0x8D); | |
6602 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6603 ins_pipe(ialu_reg_reg_fat); | |
6604 %} | |
6605 | |
6606 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem) | |
6607 %{ | |
6608 predicate(Universe::narrow_oop_shift() == 0); | |
6609 match(Set dst mem); | |
6610 | |
6611 ins_cost(110); | |
6612 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %} | |
6613 opcode(0x8D); | |
6614 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6615 ins_pipe(ialu_reg_reg_fat); | |
6616 %} | |
6617 | |
6618 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem) | |
6619 %{ | |
6620 predicate(Universe::narrow_oop_shift() == 0); | |
6621 match(Set dst mem); | |
6622 | |
6623 ins_cost(110); | |
6624 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %} | |
6625 opcode(0x8D); | |
6626 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6627 ins_pipe(ialu_reg_reg_fat); | |
6628 %} | |
6629 | |
6630 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem) | |
6631 %{ | |
6632 predicate(Universe::narrow_oop_shift() == 0); | |
6633 match(Set dst mem); | |
6634 | |
6635 ins_cost(110); | |
6636 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %} | |
6637 opcode(0x8D); | |
6638 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6639 ins_pipe(ialu_reg_reg_fat); | |
6640 %} | |
6641 | |
6421 instruct loadConI(rRegI dst, immI src) | 6642 instruct loadConI(rRegI dst, immI src) |
6422 %{ | 6643 %{ |
6423 match(Set dst src); | 6644 match(Set dst src); |
6424 | 6645 |
6425 format %{ "movl $dst, $src\t# int" %} | 6646 format %{ "movl $dst, $src\t# int" %} |
6526 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ | 6747 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ |
6527 match(Set dst src); | 6748 match(Set dst src); |
6528 effect(KILL cr); | 6749 effect(KILL cr); |
6529 format %{ "xorq $dst, $src\t# compressed NULL ptr" %} | 6750 format %{ "xorq $dst, $src\t# compressed NULL ptr" %} |
6530 ins_encode %{ | 6751 ins_encode %{ |
6531 Register dst = $dst$$Register; | 6752 __ xorq($dst$$Register, $dst$$Register); |
6532 __ xorq(dst, dst); | |
6533 %} | 6753 %} |
6534 ins_pipe(ialu_reg); | 6754 ins_pipe(ialu_reg); |
6535 %} | 6755 %} |
6536 | 6756 |
6537 instruct loadConN(rRegN dst, immN src) %{ | 6757 instruct loadConN(rRegN dst, immN src) %{ |
6539 | 6759 |
6540 ins_cost(125); | 6760 ins_cost(125); |
6541 format %{ "movl $dst, $src\t# compressed ptr" %} | 6761 format %{ "movl $dst, $src\t# compressed ptr" %} |
6542 ins_encode %{ | 6762 ins_encode %{ |
6543 address con = (address)$src$$constant; | 6763 address con = (address)$src$$constant; |
6544 Register dst = $dst$$Register; | |
6545 if (con == NULL) { | 6764 if (con == NULL) { |
6546 ShouldNotReachHere(); | 6765 ShouldNotReachHere(); |
6547 } else { | 6766 } else { |
6548 __ set_narrow_oop(dst, (jobject)$src$$constant); | 6767 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant); |
6549 } | 6768 } |
6550 %} | 6769 %} |
6551 ins_pipe(ialu_reg_fat); // XXX | 6770 ins_pipe(ialu_reg_fat); // XXX |
6552 %} | 6771 %} |
6553 | 6772 |
6792 opcode(0x89); | 7011 opcode(0x89); |
6793 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | 7012 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); |
6794 ins_pipe(ialu_mem_reg); | 7013 ins_pipe(ialu_mem_reg); |
6795 %} | 7014 %} |
6796 | 7015 |
7016 instruct storeImmP0(memory mem, immP0 zero) | |
7017 %{ | |
7018 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); | |
7019 match(Set mem (StoreP mem zero)); | |
7020 | |
7021 ins_cost(125); // XXX | |
7022 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %} | |
7023 ins_encode %{ | |
7024 __ movq($mem$$Address, r12); | |
7025 %} | |
7026 ins_pipe(ialu_mem_reg); | |
7027 %} | |
7028 | |
6797 // Store NULL Pointer, mark word, or other simple pointer constant. | 7029 // Store NULL Pointer, mark word, or other simple pointer constant. |
6798 instruct storeImmP(memory mem, immP31 src) | 7030 instruct storeImmP(memory mem, immP31 src) |
6799 %{ | 7031 %{ |
6800 match(Set mem (StoreP mem src)); | 7032 match(Set mem (StoreP mem src)); |
6801 | 7033 |
6802 ins_cost(125); // XXX | 7034 ins_cost(150); // XXX |
6803 format %{ "movq $mem, $src\t# ptr" %} | 7035 format %{ "movq $mem, $src\t# ptr" %} |
6804 opcode(0xC7); /* C7 /0 */ | 7036 opcode(0xC7); /* C7 /0 */ |
6805 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | 7037 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); |
6806 ins_pipe(ialu_mem_imm); | 7038 ins_pipe(ialu_mem_imm); |
6807 %} | 7039 %} |
6812 match(Set mem (StoreN mem src)); | 7044 match(Set mem (StoreN mem src)); |
6813 | 7045 |
6814 ins_cost(125); // XXX | 7046 ins_cost(125); // XXX |
6815 format %{ "movl $mem, $src\t# compressed ptr" %} | 7047 format %{ "movl $mem, $src\t# compressed ptr" %} |
6816 ins_encode %{ | 7048 ins_encode %{ |
6817 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); | 7049 __ movl($mem$$Address, $src$$Register); |
6818 Register src = as_Register($src$$reg); | |
6819 __ movl(addr, src); | |
6820 %} | 7050 %} |
6821 ins_pipe(ialu_mem_reg); | 7051 ins_pipe(ialu_mem_reg); |
6822 %} | 7052 %} |
6823 | 7053 |
7054 instruct storeImmN0(memory mem, immN0 zero) | |
7055 %{ | |
7056 predicate(Universe::narrow_oop_base() == NULL); | |
7057 match(Set mem (StoreN mem zero)); | |
7058 | |
7059 ins_cost(125); // XXX | |
7060 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %} | |
7061 ins_encode %{ | |
7062 __ movl($mem$$Address, r12); | |
7063 %} | |
7064 ins_pipe(ialu_mem_reg); | |
7065 %} | |
7066 | |
7067 instruct storeImmN(memory mem, immN src) | |
7068 %{ | |
7069 match(Set mem (StoreN mem src)); | |
7070 | |
7071 ins_cost(150); // XXX | |
7072 format %{ "movl $mem, $src\t# compressed ptr" %} | |
7073 ins_encode %{ | |
7074 address con = (address)$src$$constant; | |
7075 if (con == NULL) { | |
7076 __ movl($mem$$Address, (int32_t)0); | |
7077 } else { | |
7078 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant); | |
7079 } | |
7080 %} | |
7081 ins_pipe(ialu_mem_imm); | |
7082 %} | |
7083 | |
6824 // Store Integer Immediate | 7084 // Store Integer Immediate |
7085 instruct storeImmI0(memory mem, immI0 zero) | |
7086 %{ | |
7087 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); | |
7088 match(Set mem (StoreI mem zero)); | |
7089 | |
7090 ins_cost(125); // XXX | |
7091 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %} | |
7092 ins_encode %{ | |
7093 __ movl($mem$$Address, r12); | |
7094 %} | |
7095 ins_pipe(ialu_mem_reg); | |
7096 %} | |
7097 | |
6825 instruct storeImmI(memory mem, immI src) | 7098 instruct storeImmI(memory mem, immI src) |
6826 %{ | 7099 %{ |
6827 match(Set mem (StoreI mem src)); | 7100 match(Set mem (StoreI mem src)); |
6828 | 7101 |
6829 ins_cost(150); | 7102 ins_cost(150); |
6832 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | 7105 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); |
6833 ins_pipe(ialu_mem_imm); | 7106 ins_pipe(ialu_mem_imm); |
6834 %} | 7107 %} |
6835 | 7108 |
6836 // Store Long Immediate | 7109 // Store Long Immediate |
7110 instruct storeImmL0(memory mem, immL0 zero) | |
7111 %{ | |
7112 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); | |
7113 match(Set mem (StoreL mem zero)); | |
7114 | |
7115 ins_cost(125); // XXX | |
7116 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %} | |
7117 ins_encode %{ | |
7118 __ movq($mem$$Address, r12); | |
7119 %} | |
7120 ins_pipe(ialu_mem_reg); | |
7121 %} | |
7122 | |
6837 instruct storeImmL(memory mem, immL32 src) | 7123 instruct storeImmL(memory mem, immL32 src) |
6838 %{ | 7124 %{ |
6839 match(Set mem (StoreL mem src)); | 7125 match(Set mem (StoreL mem src)); |
6840 | 7126 |
6841 ins_cost(150); | 7127 ins_cost(150); |
6844 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | 7130 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); |
6845 ins_pipe(ialu_mem_imm); | 7131 ins_pipe(ialu_mem_imm); |
6846 %} | 7132 %} |
6847 | 7133 |
6848 // Store Short/Char Immediate | 7134 // Store Short/Char Immediate |
7135 instruct storeImmC0(memory mem, immI0 zero) | |
7136 %{ | |
7137 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); | |
7138 match(Set mem (StoreC mem zero)); | |
7139 | |
7140 ins_cost(125); // XXX | |
7141 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %} | |
7142 ins_encode %{ | |
7143 __ movw($mem$$Address, r12); | |
7144 %} | |
7145 ins_pipe(ialu_mem_reg); | |
7146 %} | |
7147 | |
6849 instruct storeImmI16(memory mem, immI16 src) | 7148 instruct storeImmI16(memory mem, immI16 src) |
6850 %{ | 7149 %{ |
6851 predicate(UseStoreImmI16); | 7150 predicate(UseStoreImmI16); |
6852 match(Set mem (StoreC mem src)); | 7151 match(Set mem (StoreC mem src)); |
6853 | 7152 |
6857 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); | 7156 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); |
6858 ins_pipe(ialu_mem_imm); | 7157 ins_pipe(ialu_mem_imm); |
6859 %} | 7158 %} |
6860 | 7159 |
6861 // Store Byte Immediate | 7160 // Store Byte Immediate |
7161 instruct storeImmB0(memory mem, immI0 zero) | |
7162 %{ | |
7163 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); | |
7164 match(Set mem (StoreB mem zero)); | |
7165 | |
7166 ins_cost(125); // XXX | |
7167 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %} | |
7168 ins_encode %{ | |
7169 __ movb($mem$$Address, r12); | |
7170 %} | |
7171 ins_pipe(ialu_mem_reg); | |
7172 %} | |
7173 | |
6862 instruct storeImmB(memory mem, immI8 src) | 7174 instruct storeImmB(memory mem, immI8 src) |
6863 %{ | 7175 %{ |
6864 match(Set mem (StoreB mem src)); | 7176 match(Set mem (StoreB mem src)); |
6865 | 7177 |
6866 ins_cost(150); // XXX | 7178 ins_cost(150); // XXX |
6896 ins_encode( movq_st(mem, src)); | 7208 ins_encode( movq_st(mem, src)); |
6897 ins_pipe( pipe_slow ); | 7209 ins_pipe( pipe_slow ); |
6898 %} | 7210 %} |
6899 | 7211 |
6900 // Store CMS card-mark Immediate | 7212 // Store CMS card-mark Immediate |
7213 instruct storeImmCM0_reg(memory mem, immI0 zero) | |
7214 %{ | |
7215 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); | |
7216 match(Set mem (StoreCM mem zero)); | |
7217 | |
7218 ins_cost(125); // XXX | |
7219 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %} | |
7220 ins_encode %{ | |
7221 __ movb($mem$$Address, r12); | |
7222 %} | |
7223 ins_pipe(ialu_mem_reg); | |
7224 %} | |
7225 | |
6901 instruct storeImmCM0(memory mem, immI0 src) | 7226 instruct storeImmCM0(memory mem, immI0 src) |
6902 %{ | 7227 %{ |
6903 match(Set mem (StoreCM mem src)); | 7228 match(Set mem (StoreCM mem src)); |
6904 | 7229 |
6905 ins_cost(150); // XXX | 7230 ins_cost(150); // XXX |
6929 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem)); | 7254 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem)); |
6930 ins_pipe(pipe_slow); // XXX | 7255 ins_pipe(pipe_slow); // XXX |
6931 %} | 7256 %} |
6932 | 7257 |
6933 // Store immediate Float value (it is faster than store from XMM register) | 7258 // Store immediate Float value (it is faster than store from XMM register) |
7259 instruct storeF0(memory mem, immF0 zero) | |
7260 %{ | |
7261 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); | |
7262 match(Set mem (StoreF mem zero)); | |
7263 | |
7264 ins_cost(25); // XXX | |
7265 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %} | |
7266 ins_encode %{ | |
7267 __ movl($mem$$Address, r12); | |
7268 %} | |
7269 ins_pipe(ialu_mem_reg); | |
7270 %} | |
7271 | |
6934 instruct storeF_imm(memory mem, immF src) | 7272 instruct storeF_imm(memory mem, immF src) |
6935 %{ | 7273 %{ |
6936 match(Set mem (StoreF mem src)); | 7274 match(Set mem (StoreF mem src)); |
6937 | 7275 |
6938 ins_cost(50); | 7276 ins_cost(50); |
6955 %} | 7293 %} |
6956 | 7294 |
6957 // Store immediate double 0.0 (it is faster than store from XMM register) | 7295 // Store immediate double 0.0 (it is faster than store from XMM register) |
6958 instruct storeD0_imm(memory mem, immD0 src) | 7296 instruct storeD0_imm(memory mem, immD0 src) |
6959 %{ | 7297 %{ |
7298 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); | |
6960 match(Set mem (StoreD mem src)); | 7299 match(Set mem (StoreD mem src)); |
6961 | 7300 |
6962 ins_cost(50); | 7301 ins_cost(50); |
6963 format %{ "movq $mem, $src\t# double 0." %} | 7302 format %{ "movq $mem, $src\t# double 0." %} |
6964 opcode(0xC7); /* C7 /0 */ | 7303 opcode(0xC7); /* C7 /0 */ |
6965 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | 7304 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); |
6966 ins_pipe(ialu_mem_imm); | 7305 ins_pipe(ialu_mem_imm); |
7306 %} | |
7307 | |
7308 instruct storeD0(memory mem, immD0 zero) | |
7309 %{ | |
7310 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); | |
7311 match(Set mem (StoreD mem zero)); | |
7312 | |
7313 ins_cost(25); // XXX | |
7314 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %} | |
7315 ins_encode %{ | |
7316 __ movq($mem$$Address, r12); | |
7317 %} | |
7318 ins_pipe(ialu_mem_reg); | |
6967 %} | 7319 %} |
6968 | 7320 |
6969 instruct storeSSI(stackSlotI dst, rRegI src) | 7321 instruct storeSSI(stackSlotI dst, rRegI src) |
6970 %{ | 7322 %{ |
6971 match(Set dst src); | 7323 match(Set dst src); |
7190 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); | 7542 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
7191 match(Set dst (EncodeP src)); | 7543 match(Set dst (EncodeP src)); |
7192 effect(KILL cr); | 7544 effect(KILL cr); |
7193 format %{ "encode_heap_oop_not_null $dst,$src" %} | 7545 format %{ "encode_heap_oop_not_null $dst,$src" %} |
7194 ins_encode %{ | 7546 ins_encode %{ |
7195 Register s = $src$$Register; | 7547 __ encode_heap_oop_not_null($dst$$Register, $src$$Register); |
7196 Register d = $dst$$Register; | |
7197 __ encode_heap_oop_not_null(d, s); | |
7198 %} | 7548 %} |
7199 ins_pipe(ialu_reg_long); | 7549 ins_pipe(ialu_reg_long); |
7200 %} | 7550 %} |
7201 | 7551 |
7202 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ | 7552 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ |
7222 match(Set dst (DecodeN src)); | 7572 match(Set dst (DecodeN src)); |
7223 format %{ "decode_heap_oop_not_null $dst,$src" %} | 7573 format %{ "decode_heap_oop_not_null $dst,$src" %} |
7224 ins_encode %{ | 7574 ins_encode %{ |
7225 Register s = $src$$Register; | 7575 Register s = $src$$Register; |
7226 Register d = $dst$$Register; | 7576 Register d = $dst$$Register; |
7227 __ decode_heap_oop_not_null(d, s); | 7577 if (s != d) { |
7578 __ decode_heap_oop_not_null(d, s); | |
7579 } else { | |
7580 __ decode_heap_oop_not_null(d); | |
7581 } | |
7228 %} | 7582 %} |
7229 ins_pipe(ialu_reg_long); | 7583 ins_pipe(ialu_reg_long); |
7230 %} | 7584 %} |
7231 | 7585 |
7232 | 7586 |
11387 ins_pipe(ialu_cr_reg_imm); | 11741 ins_pipe(ialu_cr_reg_imm); |
11388 %} | 11742 %} |
11389 | 11743 |
11390 // This will generate a signed flags result. This should be OK since | 11744 // This will generate a signed flags result. This should be OK since |
11391 // any compare to a zero should be eq/neq. | 11745 // any compare to a zero should be eq/neq. |
11392 instruct testP_reg_mem(rFlagsReg cr, memory op, immP0 zero) | 11746 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
11393 %{ | 11747 %{ |
11748 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); | |
11394 match(Set cr (CmpP (LoadP op) zero)); | 11749 match(Set cr (CmpP (LoadP op) zero)); |
11395 | 11750 |
11396 ins_cost(500); // XXX | 11751 ins_cost(500); // XXX |
11397 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} | 11752 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} |
11398 opcode(0xF7); /* Opcode F7 /0 */ | 11753 opcode(0xF7); /* Opcode F7 /0 */ |
11399 ins_encode(REX_mem_wide(op), | 11754 ins_encode(REX_mem_wide(op), |
11400 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); | 11755 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); |
11401 ins_pipe(ialu_cr_reg_imm); | 11756 ins_pipe(ialu_cr_reg_imm); |
11402 %} | 11757 %} |
11403 | 11758 |
11759 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) | |
11760 %{ | |
11761 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); | |
11762 match(Set cr (CmpP (LoadP mem) zero)); | |
11763 | |
11764 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} | |
11765 ins_encode %{ | |
11766 __ cmpq(r12, $mem$$Address); | |
11767 %} | |
11768 ins_pipe(ialu_cr_reg_mem); | |
11769 %} | |
11404 | 11770 |
11405 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) | 11771 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) |
11406 %{ | 11772 %{ |
11407 match(Set cr (CmpN op1 op2)); | 11773 match(Set cr (CmpN op1 op2)); |
11408 | 11774 |
11409 format %{ "cmpl $op1, $op2\t# compressed ptr" %} | 11775 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
11410 ins_encode %{ __ cmpl(as_Register($op1$$reg), as_Register($op2$$reg)); %} | 11776 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %} |
11411 ins_pipe(ialu_cr_reg_reg); | 11777 ins_pipe(ialu_cr_reg_reg); |
11412 %} | 11778 %} |
11413 | 11779 |
11414 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) | 11780 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) |
11415 %{ | 11781 %{ |
11416 match(Set cr (CmpN src (LoadN mem))); | 11782 match(Set cr (CmpN src (LoadN mem))); |
11417 | 11783 |
11418 ins_cost(500); // XXX | 11784 format %{ "cmpl $src, $mem\t# compressed ptr" %} |
11419 format %{ "cmpl $src, mem\t# compressed ptr" %} | |
11420 ins_encode %{ | 11785 ins_encode %{ |
11421 Address adr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); | 11786 __ cmpl($src$$Register, $mem$$Address); |
11422 __ cmpl(as_Register($src$$reg), adr); | 11787 %} |
11788 ins_pipe(ialu_cr_reg_mem); | |
11789 %} | |
11790 | |
11791 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{ | |
11792 match(Set cr (CmpN op1 op2)); | |
11793 | |
11794 format %{ "cmpl $op1, $op2\t# compressed ptr" %} | |
11795 ins_encode %{ | |
11796 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant); | |
11797 %} | |
11798 ins_pipe(ialu_cr_reg_imm); | |
11799 %} | |
11800 | |
11801 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src) | |
11802 %{ | |
11803 match(Set cr (CmpN src (LoadN mem))); | |
11804 | |
11805 format %{ "cmpl $mem, $src\t# compressed ptr" %} | |
11806 ins_encode %{ | |
11807 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant); | |
11423 %} | 11808 %} |
11424 ins_pipe(ialu_cr_reg_mem); | 11809 ins_pipe(ialu_cr_reg_mem); |
11425 %} | 11810 %} |
11426 | 11811 |
11427 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ | 11812 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ |
11430 format %{ "testl $src, $src\t# compressed ptr" %} | 11815 format %{ "testl $src, $src\t# compressed ptr" %} |
11431 ins_encode %{ __ testl($src$$Register, $src$$Register); %} | 11816 ins_encode %{ __ testl($src$$Register, $src$$Register); %} |
11432 ins_pipe(ialu_cr_reg_imm); | 11817 ins_pipe(ialu_cr_reg_imm); |
11433 %} | 11818 %} |
11434 | 11819 |
11435 instruct testN_reg_mem(rFlagsReg cr, memory mem, immN0 zero) | 11820 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero) |
11436 %{ | 11821 %{ |
11822 predicate(Universe::narrow_oop_base() != NULL); | |
11437 match(Set cr (CmpN (LoadN mem) zero)); | 11823 match(Set cr (CmpN (LoadN mem) zero)); |
11438 | 11824 |
11439 ins_cost(500); // XXX | 11825 ins_cost(500); // XXX |
11440 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} | 11826 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} |
11441 ins_encode %{ | 11827 ins_encode %{ |
11442 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); | 11828 __ cmpl($mem$$Address, (int)0xFFFFFFFF); |
11443 __ cmpl(addr, (int)0xFFFFFFFF); | 11829 %} |
11830 ins_pipe(ialu_cr_reg_mem); | |
11831 %} | |
11832 | |
11833 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero) | |
11834 %{ | |
11835 predicate(Universe::narrow_oop_base() == NULL); | |
11836 match(Set cr (CmpN (LoadN mem) zero)); | |
11837 | |
11838 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %} | |
11839 ins_encode %{ | |
11840 __ cmpl(r12, $mem$$Address); | |
11444 %} | 11841 %} |
11445 ins_pipe(ialu_cr_reg_mem); | 11842 ins_pipe(ialu_cr_reg_mem); |
11446 %} | 11843 %} |
11447 | 11844 |
11448 // Yanked all unsigned pointer compare operations. | 11845 // Yanked all unsigned pointer compare operations. |
11470 | 11867 |
11471 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) | 11868 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) |
11472 %{ | 11869 %{ |
11473 match(Set cr (CmpL op1 (LoadL op2))); | 11870 match(Set cr (CmpL op1 (LoadL op2))); |
11474 | 11871 |
11475 ins_cost(500); // XXX | |
11476 format %{ "cmpq $op1, $op2" %} | 11872 format %{ "cmpq $op1, $op2" %} |
11477 opcode(0x3B); /* Opcode 3B /r */ | 11873 opcode(0x3B); /* Opcode 3B /r */ |
11478 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | 11874 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); |
11479 ins_pipe(ialu_cr_reg_mem); | 11875 ins_pipe(ialu_cr_reg_mem); |
11480 %} | 11876 %} |
11754 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | 12150 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, |
11755 immP0 zero, | 12151 immP0 zero, |
11756 rdi_RegP result) | 12152 rdi_RegP result) |
11757 %{ | 12153 %{ |
11758 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | 12154 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); |
11759 predicate(!UseCompressedOops); // decoding oop kills condition codes | |
11760 effect(KILL rcx, KILL result); | 12155 effect(KILL rcx, KILL result); |
11761 | 12156 |
11762 ins_cost(1000); | 12157 ins_cost(1000); |
11763 format %{ "cmpq rax, rsi\n\t" | 12158 format %{ "cmpq rax, rsi\n\t" |
11764 "jeq,s miss\t# Actually a hit; we are done.\n\t" | 12159 "jeq,s miss\t# Actually a hit; we are done.\n\t" |