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comparison src/cpu/ppc/vm/assembler_ppc.inline.hpp @ 14445:67fa91961822

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8029940: PPC64 (part 122): C2 compiler port Reviewed-by: kvn
author goetz
date Wed, 11 Dec 2013 00:06:11 +0100
parents ec28f9c041ff
children e5e8aa897002
comparison
equal deleted inserted replaced
14444:492e67693373 14445:67fa91961822
222 inline void Assembler::clrlsldi( Register a, Register s, int clrl6, int shl6) { Assembler::rldic( a, s, shl6, clrl6-shl6); } 222 inline void Assembler::clrlsldi( Register a, Register s, int clrl6, int shl6) { Assembler::rldic( a, s, shl6, clrl6-shl6); }
223 inline void Assembler::clrlsldi_(Register a, Register s, int clrl6, int shl6) { Assembler::rldic_(a, s, shl6, clrl6-shl6); } 223 inline void Assembler::clrlsldi_(Register a, Register s, int clrl6, int shl6) { Assembler::rldic_(a, s, shl6, clrl6-shl6); }
224 inline void Assembler::extrdi( Register a, Register s, int n, int b){ Assembler::rldicl(a, s, b+n, 64-n); } 224 inline void Assembler::extrdi( Register a, Register s, int n, int b){ Assembler::rldicl(a, s, b+n, 64-n); }
225 // testbit with condition register. 225 // testbit with condition register.
226 inline void Assembler::testbitdi(ConditionRegister cr, Register a, Register s, int ui6) { 226 inline void Assembler::testbitdi(ConditionRegister cr, Register a, Register s, int ui6) {
227 Assembler::rldicr(a, s, 63-ui6, 0); 227 if (cr == CCR0) {
228 Assembler::cmpdi(cr, a, 0); 228 Assembler::rldicr_(a, s, 63-ui6, 0);
229 } else {
230 Assembler::rldicr(a, s, 63-ui6, 0);
231 Assembler::cmpdi(cr, a, 0);
232 }
229 } 233 }
230 234
231 // rotate instructions 235 // rotate instructions
232 inline void Assembler::rotldi( Register a, Register s, int n) { Assembler::rldicl(a, s, n, 0); } 236 inline void Assembler::rotldi( Register a, Register s, int n) { Assembler::rldicl(a, s, n, 0); }
233 inline void Assembler::rotrdi( Register a, Register s, int n) { Assembler::rldicl(a, s, 64-n, 0); } 237 inline void Assembler::rotrdi( Register a, Register s, int n) { Assembler::rldicl(a, s, 64-n, 0); }
421 inline void Assembler::crnor( int d, int s1, int s2) { emit_int32(CRNOR_OPCODE | bt(d) | ba(s1) | bb(s2)); } 425 inline void Assembler::crnor( int d, int s1, int s2) { emit_int32(CRNOR_OPCODE | bt(d) | ba(s1) | bb(s2)); }
422 inline void Assembler::creqv( int d, int s1, int s2) { emit_int32(CREQV_OPCODE | bt(d) | ba(s1) | bb(s2)); } 426 inline void Assembler::creqv( int d, int s1, int s2) { emit_int32(CREQV_OPCODE | bt(d) | ba(s1) | bb(s2)); }
423 inline void Assembler::crandc(int d, int s1, int s2) { emit_int32(CRANDC_OPCODE | bt(d) | ba(s1) | bb(s2)); } 427 inline void Assembler::crandc(int d, int s1, int s2) { emit_int32(CRANDC_OPCODE | bt(d) | ba(s1) | bb(s2)); }
424 inline void Assembler::crorc( int d, int s1, int s2) { emit_int32(CRORC_OPCODE | bt(d) | ba(s1) | bb(s2)); } 428 inline void Assembler::crorc( int d, int s1, int s2) { emit_int32(CRORC_OPCODE | bt(d) | ba(s1) | bb(s2)); }
425 429
430 // Conditional move (>= Power7)
431 inline void Assembler::isel(Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b) {
432 if (b == noreg) {
433 b = d; // Can be omitted if old value should be kept in "else" case.
434 }
435 Register first = a;
436 Register second = b;
437 if (inv) {
438 first = b;
439 second = a; // exchange
440 }
441 assert(first != R0, "r0 not allowed");
442 isel(d, first, second, bi0(cr, cc));
443 }
444 inline void Assembler::isel_0(Register d, ConditionRegister cr, Condition cc, Register b) {
445 if (b == noreg) {
446 b = d; // Can be omitted if old value should be kept in "else" case.
447 }
448 isel(d, R0, b, bi0(cr, cc));
449 }
450
426 // PPC 2, section 3.2.1 Instruction Cache Instructions 451 // PPC 2, section 3.2.1 Instruction Cache Instructions
427 inline void Assembler::icbi( Register s1, Register s2) { emit_int32( ICBI_OPCODE | ra0mem(s1) | rb(s2) ); } 452 inline void Assembler::icbi( Register s1, Register s2) { emit_int32( ICBI_OPCODE | ra0mem(s1) | rb(s2) ); }
428 // PPC 2, section 3.2.2 Data Cache Instructions 453 // PPC 2, section 3.2.2 Data Cache Instructions
429 //inline void Assembler::dcba( Register s1, Register s2) { emit_int32( DCBA_OPCODE | ra0mem(s1) | rb(s2) ); } 454 //inline void Assembler::dcba( Register s1, Register s2) { emit_int32( DCBA_OPCODE | ra0mem(s1) | rb(s2) ); }
430 inline void Assembler::dcbz( Register s1, Register s2) { emit_int32( DCBZ_OPCODE | ra0mem(s1) | rb(s2) ); } 455 inline void Assembler::dcbz( Register s1, Register s2) { emit_int32( DCBZ_OPCODE | ra0mem(s1) | rb(s2) ); }
443 inline void Assembler::sync() { Assembler::sync(0); } 468 inline void Assembler::sync() { Assembler::sync(0); }
444 inline void Assembler::lwsync() { Assembler::sync(1); } 469 inline void Assembler::lwsync() { Assembler::sync(1); }
445 inline void Assembler::ptesync() { Assembler::sync(2); } 470 inline void Assembler::ptesync() { Assembler::sync(2); }
446 inline void Assembler::eieio() { emit_int32( EIEIO_OPCODE); } 471 inline void Assembler::eieio() { emit_int32( EIEIO_OPCODE); }
447 inline void Assembler::isync() { emit_int32( ISYNC_OPCODE); } 472 inline void Assembler::isync() { emit_int32( ISYNC_OPCODE); }
448 473 inline void Assembler::elemental_membar(int e) { assert(0 < e && e < 16, "invalid encoding"); emit_int32( SYNC_OPCODE | e1215(e)); }
449 inline void Assembler::release() { Assembler::lwsync(); }
450 inline void Assembler::acquire() { Assembler::lwsync(); }
451 inline void Assembler::fence() { Assembler::sync(); }
452 474
453 // atomics 475 // atomics
454 // Use ra0mem to disallow R0 as base. 476 // Use ra0mem to disallow R0 as base.
455 inline void Assembler::lwarx_unchecked(Register d, Register a, Register b, int eh1) { emit_int32( LWARX_OPCODE | rt(d) | ra0mem(a) | rb(b) | eh(eh1)); } 477 inline void Assembler::lwarx_unchecked(Register d, Register a, Register b, int eh1) { emit_int32( LWARX_OPCODE | rt(d) | ra0mem(a) | rb(b) | eh(eh1)); }
456 inline void Assembler::ldarx_unchecked(Register d, Register a, Register b, int eh1) { emit_int32( LDARX_OPCODE | rt(d) | ra0mem(a) | rb(b) | eh(eh1)); } 478 inline void Assembler::ldarx_unchecked(Register d, Register a, Register b, int eh1) { emit_int32( LDARX_OPCODE | rt(d) | ra0mem(a) | rb(b) | eh(eh1)); }
765 inline void Assembler::stvx( VectorRegister d, Register s2) { emit_int32( STVX_OPCODE | vrt(d) | rb(s2)); } 787 inline void Assembler::stvx( VectorRegister d, Register s2) { emit_int32( STVX_OPCODE | vrt(d) | rb(s2)); }
766 inline void Assembler::stvxl( VectorRegister d, Register s2) { emit_int32( STVXL_OPCODE | vrt(d) | rb(s2)); } 788 inline void Assembler::stvxl( VectorRegister d, Register s2) { emit_int32( STVXL_OPCODE | vrt(d) | rb(s2)); }
767 inline void Assembler::lvsl( VectorRegister d, Register s2) { emit_int32( LVSL_OPCODE | vrt(d) | rb(s2)); } 789 inline void Assembler::lvsl( VectorRegister d, Register s2) { emit_int32( LVSL_OPCODE | vrt(d) | rb(s2)); }
768 inline void Assembler::lvsr( VectorRegister d, Register s2) { emit_int32( LVSR_OPCODE | vrt(d) | rb(s2)); } 790 inline void Assembler::lvsr( VectorRegister d, Register s2) { emit_int32( LVSR_OPCODE | vrt(d) | rb(s2)); }
769 791
770
771 inline void Assembler::load_const(Register d, void* x, Register tmp) { 792 inline void Assembler::load_const(Register d, void* x, Register tmp) {
772 load_const(d, (long)x, tmp); 793 load_const(d, (long)x, tmp);
773 } 794 }
774 795
775 // Load a 64 bit constant encoded by a `Label'. This works for bound 796 // Load a 64 bit constant encoded by a `Label'. This works for bound