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comparison src/cpu/sparc/vm/interp_masm_sparc.cpp @ 727:6b2273dd6fa9

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6822110: Add AddressLiteral class on SPARC Summary: The Address class on SPARC currently handles both, addresses and address literals, what makes the Address class more complicated than it has to be. Reviewed-by: never, kvn
author twisti
date Tue, 21 Apr 2009 11:16:30 -0700
parents c517646eef23
children 6918603297f7
comparison
equal deleted inserted replaced
725:928912ce8438 727:6b2273dd6fa9
1 /* 1 /*
2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved. 2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 * 4 *
5 * This code is free software; you can redistribute it and/or modify it 5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as 6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
33 33
34 // Implementation of InterpreterMacroAssembler 34 // Implementation of InterpreterMacroAssembler
35 35
36 // This file specializes the assember with interpreter-specific macros 36 // This file specializes the assember with interpreter-specific macros
37 37
38 const Address InterpreterMacroAssembler::l_tmp( FP, 0, (frame::interpreter_frame_l_scratch_fp_offset * wordSize ) + STACK_BIAS); 38 const Address InterpreterMacroAssembler::l_tmp(FP, (frame::interpreter_frame_l_scratch_fp_offset * wordSize) + STACK_BIAS);
39 const Address InterpreterMacroAssembler::d_tmp( FP, 0, (frame::interpreter_frame_d_scratch_fp_offset * wordSize) + STACK_BIAS); 39 const Address InterpreterMacroAssembler::d_tmp(FP, (frame::interpreter_frame_d_scratch_fp_offset * wordSize) + STACK_BIAS);
40 40
41 #else // CC_INTERP 41 #else // CC_INTERP
42 #ifndef STATE 42 #ifndef STATE
43 #define STATE(field_name) Lstate, in_bytes(byte_offset_of(BytecodeInterpreter, field_name)) 43 #define STATE(field_name) Lstate, in_bytes(byte_offset_of(BytecodeInterpreter, field_name))
44 #endif // STATE 44 #endif // STATE
76 add(Lbyte_code, Interpreter::distance_from_dispatch_table(state), Lbyte_code); 76 add(Lbyte_code, Interpreter::distance_from_dispatch_table(state), Lbyte_code);
77 // add offset to correct dispatch table 77 // add offset to correct dispatch table
78 sll(Lbyte_code, LogBytesPerWord, Lbyte_code); // multiply by wordSize 78 sll(Lbyte_code, LogBytesPerWord, Lbyte_code); // multiply by wordSize
79 ld_ptr(IdispatchTables, Lbyte_code, IdispatchAddress);// get entry addr 79 ld_ptr(IdispatchTables, Lbyte_code, IdispatchAddress);// get entry addr
80 #else 80 #else
81 ldub( Lbcp, bcp_incr, Lbyte_code); // load next bytecode 81 ldub( Lbcp, bcp_incr, Lbyte_code); // load next bytecode
82 // dispatch table to use 82 // dispatch table to use
83 Address tbl(G3_scratch, (address)Interpreter::dispatch_table(state)); 83 AddressLiteral tbl(Interpreter::dispatch_table(state));
84 84 sll(Lbyte_code, LogBytesPerWord, Lbyte_code); // multiply by wordSize
85 sethi(tbl); 85 set(tbl, G3_scratch); // compute addr of table
86 sll(Lbyte_code, LogBytesPerWord, Lbyte_code); // multiply by wordSize 86 ld_ptr(G3_scratch, Lbyte_code, IdispatchAddress); // get entry addr
87 add(tbl, tbl.base(), 0);
88 ld_ptr( G3_scratch, Lbyte_code, IdispatchAddress); // get entry addr
89 #endif 87 #endif
90 } 88 }
91 89
92 90
93 // Dispatch code executed in the epilog of a bytecode which does not do it's 91 // Dispatch code executed in the epilog of a bytecode which does not do it's
163 void InterpreterMacroAssembler::check_and_handle_popframe(Register scratch_reg) { 161 void InterpreterMacroAssembler::check_and_handle_popframe(Register scratch_reg) {
164 if (JvmtiExport::can_pop_frame()) { 162 if (JvmtiExport::can_pop_frame()) {
165 Label L; 163 Label L;
166 164
167 // Check the "pending popframe condition" flag in the current thread 165 // Check the "pending popframe condition" flag in the current thread
168 Address popframe_condition_addr(G2_thread, 0, in_bytes(JavaThread::popframe_condition_offset())); 166 ld(G2_thread, JavaThread::popframe_condition_offset(), scratch_reg);
169 ld(popframe_condition_addr, scratch_reg);
170 167
171 // Initiate popframe handling only if it is not already being processed. If the flag 168 // Initiate popframe handling only if it is not already being processed. If the flag
172 // has the popframe_processing bit set, it means that this code is called *during* popframe 169 // has the popframe_processing bit set, it means that this code is called *during* popframe
173 // handling - we don't want to reenter. 170 // handling - we don't want to reenter.
174 btst(JavaThread::popframe_pending_bit, scratch_reg); 171 btst(JavaThread::popframe_pending_bit, scratch_reg);
190 } 187 }
191 188
192 189
193 void InterpreterMacroAssembler::load_earlyret_value(TosState state) { 190 void InterpreterMacroAssembler::load_earlyret_value(TosState state) {
194 Register thr_state = G4_scratch; 191 Register thr_state = G4_scratch;
195 ld_ptr(Address(G2_thread, 0, in_bytes(JavaThread::jvmti_thread_state_offset())), 192 ld_ptr(G2_thread, JavaThread::jvmti_thread_state_offset(), thr_state);
196 thr_state); 193 const Address tos_addr(thr_state, JvmtiThreadState::earlyret_tos_offset());
197 const Address tos_addr(thr_state, 0, in_bytes(JvmtiThreadState::earlyret_tos_offset())); 194 const Address oop_addr(thr_state, JvmtiThreadState::earlyret_oop_offset());
198 const Address oop_addr(thr_state, 0, in_bytes(JvmtiThreadState::earlyret_oop_offset())); 195 const Address val_addr(thr_state, JvmtiThreadState::earlyret_value_offset());
199 const Address val_addr(thr_state, 0, in_bytes(JvmtiThreadState::earlyret_value_offset()));
200 switch (state) { 196 switch (state) {
201 case ltos: ld_long(val_addr, Otos_l); break; 197 case ltos: ld_long(val_addr, Otos_l); break;
202 case atos: ld_ptr(oop_addr, Otos_l); 198 case atos: ld_ptr(oop_addr, Otos_l);
203 st_ptr(G0, oop_addr); break; 199 st_ptr(G0, oop_addr); break;
204 case btos: // fall through 200 case btos: // fall through
220 216
221 void InterpreterMacroAssembler::check_and_handle_earlyret(Register scratch_reg) { 217 void InterpreterMacroAssembler::check_and_handle_earlyret(Register scratch_reg) {
222 if (JvmtiExport::can_force_early_return()) { 218 if (JvmtiExport::can_force_early_return()) {
223 Label L; 219 Label L;
224 Register thr_state = G3_scratch; 220 Register thr_state = G3_scratch;
225 ld_ptr(Address(G2_thread, 0, in_bytes(JavaThread::jvmti_thread_state_offset())), 221 ld_ptr(G2_thread, JavaThread::jvmti_thread_state_offset(), thr_state);
226 thr_state);
227 tst(thr_state); 222 tst(thr_state);
228 br(zero, false, pt, L); // if (thread->jvmti_thread_state() == NULL) exit; 223 br(zero, false, pt, L); // if (thread->jvmti_thread_state() == NULL) exit;
229 delayed()->nop(); 224 delayed()->nop();
230 225
231 // Initiate earlyret handling only if it is not already being processed. 226 // Initiate earlyret handling only if it is not already being processed.
232 // If the flag has the earlyret_processing bit set, it means that this code 227 // If the flag has the earlyret_processing bit set, it means that this code
233 // is called *during* earlyret handling - we don't want to reenter. 228 // is called *during* earlyret handling - we don't want to reenter.
234 ld(Address(thr_state, 0, in_bytes(JvmtiThreadState::earlyret_state_offset())), 229 ld(thr_state, JvmtiThreadState::earlyret_state_offset(), G4_scratch);
235 G4_scratch);
236 cmp(G4_scratch, JvmtiThreadState::earlyret_pending); 230 cmp(G4_scratch, JvmtiThreadState::earlyret_pending);
237 br(Assembler::notEqual, false, pt, L); 231 br(Assembler::notEqual, false, pt, L);
238 delayed()->nop(); 232 delayed()->nop();
239 233
240 // Call Interpreter::remove_activation_early_entry() to get the address of the 234 // Call Interpreter::remove_activation_early_entry() to get the address of the
241 // same-named entrypoint in the generated interpreter code 235 // same-named entrypoint in the generated interpreter code
242 Address tos_addr(thr_state, 0, in_bytes(JvmtiThreadState::earlyret_tos_offset())); 236 ld(thr_state, JvmtiThreadState::earlyret_tos_offset(), Otos_l1);
243 ld(tos_addr, Otos_l1);
244 call_VM_leaf(noreg, CAST_FROM_FN_PTR(address, Interpreter::remove_activation_early_entry), Otos_l1); 237 call_VM_leaf(noreg, CAST_FROM_FN_PTR(address, Interpreter::remove_activation_early_entry), Otos_l1);
245 238
246 // Jump to Interpreter::_remove_activation_early_entry 239 // Jump to Interpreter::_remove_activation_early_entry
247 jmpl(O0, G0, G0); 240 jmpl(O0, G0, G0);
248 delayed()->nop(); 241 delayed()->nop();
292 sll(Lbyte_code, LogBytesPerWord, Lbyte_code); // multiply by wordSize 285 sll(Lbyte_code, LogBytesPerWord, Lbyte_code); // multiply by wordSize
293 ld_ptr(IdispatchTables, Lbyte_code, G3_scratch); // get entry addr 286 ld_ptr(IdispatchTables, Lbyte_code, G3_scratch); // get entry addr
294 } else { 287 } else {
295 #endif 288 #endif
296 // dispatch table to use 289 // dispatch table to use
297 Address tbl(G3_scratch, (address)table); 290 AddressLiteral tbl(table);
298
299 sll(Lbyte_code, LogBytesPerWord, Lbyte_code); // multiply by wordSize 291 sll(Lbyte_code, LogBytesPerWord, Lbyte_code); // multiply by wordSize
300 load_address(tbl); // compute addr of table 292 set(tbl, G3_scratch); // compute addr of table
301 ld_ptr(G3_scratch, Lbyte_code, G3_scratch); // get entry addr 293 ld_ptr(G3_scratch, Lbyte_code, G3_scratch); // get entry addr
302 #ifdef FAST_DISPATCH 294 #ifdef FAST_DISPATCH
303 } 295 }
304 #endif 296 #endif
305 jmp( G3_scratch, 0 ); 297 jmp( G3_scratch, 0 );
599 // Reset Lesp. 591 // Reset Lesp.
600 sub( Lmonitors, wordSize, Lesp ); 592 sub( Lmonitors, wordSize, Lesp );
601 593
602 // Reset SP by subtracting more space from Lesp. 594 // Reset SP by subtracting more space from Lesp.
603 Label done; 595 Label done;
604
605 const Address max_stack (Lmethod, 0, in_bytes(methodOopDesc::max_stack_offset()));
606 const Address access_flags(Lmethod, 0, in_bytes(methodOopDesc::access_flags_offset()));
607
608 verify_oop(Lmethod); 596 verify_oop(Lmethod);
609 597 assert(G4_scratch != Gframe_size, "Only you can prevent register aliasing!");
610
611 assert( G4_scratch != Gframe_size,
612 "Only you can prevent register aliasing!");
613 598
614 // A native does not need to do this, since its callee does not change SP. 599 // A native does not need to do this, since its callee does not change SP.
615 ld(access_flags, Gframe_size); 600 ld(Lmethod, methodOopDesc::access_flags_offset(), Gframe_size); // Load access flags.
616 btst(JVM_ACC_NATIVE, Gframe_size); 601 btst(JVM_ACC_NATIVE, Gframe_size);
617 br(Assembler::notZero, false, Assembler::pt, done); 602 br(Assembler::notZero, false, Assembler::pt, done);
618 delayed()->nop(); 603 delayed()->nop();
619 604
620 //
621 // Compute max expression stack+register save area 605 // Compute max expression stack+register save area
622 // 606 lduh(Lmethod, in_bytes(methodOopDesc::max_stack_offset()), Gframe_size); // Load max stack.
623 lduh( max_stack, Gframe_size );
624 if (TaggedStackInterpreter) sll ( Gframe_size, 1, Gframe_size); // max_stack * 2 for TAGS 607 if (TaggedStackInterpreter) sll ( Gframe_size, 1, Gframe_size); // max_stack * 2 for TAGS
625 add( Gframe_size, frame::memory_parameter_word_sp_offset, Gframe_size ); 608 add( Gframe_size, frame::memory_parameter_word_sp_offset, Gframe_size );
626 609
627 // 610 //
628 // now set up a stack frame with the size computed above 611 // now set up a stack frame with the size computed above
719 // compiled code in threads for which the event is enabled. Check here for 702 // compiled code in threads for which the event is enabled. Check here for
720 // interp_only_mode if these events CAN be enabled. 703 // interp_only_mode if these events CAN be enabled.
721 verify_thread(); 704 verify_thread();
722 Label skip_compiled_code; 705 Label skip_compiled_code;
723 706
724 const Address interp_only (G2_thread, 0, in_bytes(JavaThread::interp_only_mode_offset())); 707 const Address interp_only(G2_thread, JavaThread::interp_only_mode_offset());
725
726 ld(interp_only, scratch); 708 ld(interp_only, scratch);
727 tst(scratch); 709 tst(scratch);
728 br(Assembler::notZero, true, Assembler::pn, skip_compiled_code); 710 br(Assembler::notZero, true, Assembler::pn, skip_compiled_code);
729 delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), target); 711 delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), target);
730 bind(skip_compiled_code); 712 bind(skip_compiled_code);
914 896
915 void InterpreterMacroAssembler::throw_if_not_2( address throw_entry_point, 897 void InterpreterMacroAssembler::throw_if_not_2( address throw_entry_point,
916 Register Rscratch, 898 Register Rscratch,
917 Label& ok ) { 899 Label& ok ) {
918 assert(throw_entry_point != NULL, "entry point must be generated by now"); 900 assert(throw_entry_point != NULL, "entry point must be generated by now");
919 Address dest(Rscratch, throw_entry_point); 901 AddressLiteral dest(throw_entry_point);
920 jump_to(dest); 902 jump_to(dest, Rscratch);
921 delayed()->nop(); 903 delayed()->nop();
922 bind(ok); 904 bind(ok);
923 } 905 }
924 906
925 907
1033 bool throw_monitor_exception, 1015 bool throw_monitor_exception,
1034 bool install_monitor_exception) { 1016 bool install_monitor_exception) {
1035 Label unlocked, unlock, no_unlock; 1017 Label unlocked, unlock, no_unlock;
1036 1018
1037 // get the value of _do_not_unlock_if_synchronized into G1_scratch 1019 // get the value of _do_not_unlock_if_synchronized into G1_scratch
1038 const Address do_not_unlock_if_synchronized(G2_thread, 0, 1020 const Address do_not_unlock_if_synchronized(G2_thread,
1039 in_bytes(JavaThread::do_not_unlock_if_synchronized_offset())); 1021 JavaThread::do_not_unlock_if_synchronized_offset());
1040 ldbool(do_not_unlock_if_synchronized, G1_scratch); 1022 ldbool(do_not_unlock_if_synchronized, G1_scratch);
1041 stbool(G0, do_not_unlock_if_synchronized); // reset the flag 1023 stbool(G0, do_not_unlock_if_synchronized); // reset the flag
1042 1024
1043 // check if synchronized method 1025 // check if synchronized method
1044 const Address access_flags(Lmethod, 0, in_bytes(methodOopDesc::access_flags_offset())); 1026 const Address access_flags(Lmethod, methodOopDesc::access_flags_offset());
1045 interp_verify_oop(Otos_i, state, __FILE__, __LINE__); 1027 interp_verify_oop(Otos_i, state, __FILE__, __LINE__);
1046 push(state); // save tos 1028 push(state); // save tos
1047 ld(access_flags, G3_scratch); 1029 ld(access_flags, G3_scratch); // Load access flags.
1048 btst(JVM_ACC_SYNCHRONIZED, G3_scratch); 1030 btst(JVM_ACC_SYNCHRONIZED, G3_scratch);
1049 br( zero, false, pt, unlocked); 1031 br(zero, false, pt, unlocked);
1050 delayed()->nop(); 1032 delayed()->nop();
1051 1033
1052 // Don't unlock anything if the _do_not_unlock_if_synchronized flag 1034 // Don't unlock anything if the _do_not_unlock_if_synchronized flag
1053 // is set. 1035 // is set.
1054 tstbool(G1_scratch); 1036 tstbool(G1_scratch);
1234 } 1216 }
1235 else { 1217 else {
1236 Register obj_reg = Object; 1218 Register obj_reg = Object;
1237 Register mark_reg = G4_scratch; 1219 Register mark_reg = G4_scratch;
1238 Register temp_reg = G1_scratch; 1220 Register temp_reg = G1_scratch;
1239 Address lock_addr = Address(lock_reg, 0, BasicObjectLock::lock_offset_in_bytes()); 1221 Address lock_addr(lock_reg, BasicObjectLock::lock_offset_in_bytes());
1240 Address mark_addr = Address(obj_reg, 0, oopDesc::mark_offset_in_bytes()); 1222 Address mark_addr(obj_reg, oopDesc::mark_offset_in_bytes());
1241 Label done; 1223 Label done;
1242 1224
1243 Label slow_case; 1225 Label slow_case;
1244 1226
1245 assert_different_registers(lock_reg, obj_reg, mark_reg, temp_reg); 1227 assert_different_registers(lock_reg, obj_reg, mark_reg, temp_reg);
1313 call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorexit), lock_reg); 1295 call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorexit), lock_reg);
1314 } else { 1296 } else {
1315 Register obj_reg = G3_scratch; 1297 Register obj_reg = G3_scratch;
1316 Register mark_reg = G4_scratch; 1298 Register mark_reg = G4_scratch;
1317 Register displaced_header_reg = G1_scratch; 1299 Register displaced_header_reg = G1_scratch;
1318 Address lock_addr = Address(lock_reg, 0, BasicObjectLock::lock_offset_in_bytes()); 1300 Address lockobj_addr(lock_reg, BasicObjectLock::obj_offset_in_bytes());
1319 Address lockobj_addr = Address(lock_reg, 0, BasicObjectLock::obj_offset_in_bytes()); 1301 Address mark_addr(obj_reg, oopDesc::mark_offset_in_bytes());
1320 Address mark_addr = Address(obj_reg, 0, oopDesc::mark_offset_in_bytes());
1321 Label done; 1302 Label done;
1322 1303
1323 if (UseBiasedLocking) { 1304 if (UseBiasedLocking) {
1324 // load the object out of the BasicObjectLock 1305 // load the object out of the BasicObjectLock
1325 ld_ptr(lockobj_addr, obj_reg); 1306 ld_ptr(lockobj_addr, obj_reg);
1326 biased_locking_exit(mark_addr, mark_reg, done, true); 1307 biased_locking_exit(mark_addr, mark_reg, done, true);
1327 st_ptr(G0, lockobj_addr); // free entry 1308 st_ptr(G0, lockobj_addr); // free entry
1328 } 1309 }
1329 1310
1330 // Test first if we are in the fast recursive case 1311 // Test first if we are in the fast recursive case
1331 ld_ptr(lock_addr, displaced_header_reg, BasicLock::displaced_header_offset_in_bytes()); 1312 Address lock_addr(lock_reg, BasicObjectLock::lock_offset_in_bytes() + BasicLock::displaced_header_offset_in_bytes());
1313 ld_ptr(lock_addr, displaced_header_reg);
1332 br_null(displaced_header_reg, true, Assembler::pn, done); 1314 br_null(displaced_header_reg, true, Assembler::pn, done);
1333 delayed()->st_ptr(G0, lockobj_addr); // free entry 1315 delayed()->st_ptr(G0, lockobj_addr); // free entry
1334 1316
1335 // See if it is still a light weight lock, if so we just unlock 1317 // See if it is still a light weight lock, if so we just unlock
1336 // the object and we are done 1318 // the object and we are done
1382 void InterpreterMacroAssembler::set_method_data_pointer_for_bcp() { 1364 void InterpreterMacroAssembler::set_method_data_pointer_for_bcp() {
1383 assert(ProfileInterpreter, "must be profiling interpreter"); 1365 assert(ProfileInterpreter, "must be profiling interpreter");
1384 Label zero_continue; 1366 Label zero_continue;
1385 1367
1386 // Test MDO to avoid the call if it is NULL. 1368 // Test MDO to avoid the call if it is NULL.
1387 ld_ptr(Lmethod, in_bytes(methodOopDesc::method_data_offset()), ImethodDataPtr); 1369 ld_ptr(Lmethod, methodOopDesc::method_data_offset(), ImethodDataPtr);
1388 test_method_data_pointer(zero_continue); 1370 test_method_data_pointer(zero_continue);
1389 call_VM_leaf(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::bcp_to_di), Lmethod, Lbcp); 1371 call_VM_leaf(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::bcp_to_di), Lmethod, Lbcp);
1390 set_method_data_pointer_offset(O0); 1372 set_method_data_pointer_offset(O0);
1391 bind(zero_continue); 1373 bind(zero_continue);
1392 } 1374 }
1411 test_method_data_pointer(verify_continue); 1393 test_method_data_pointer(verify_continue);
1412 1394
1413 // If the mdp is valid, it will point to a DataLayout header which is 1395 // If the mdp is valid, it will point to a DataLayout header which is
1414 // consistent with the bcp. The converse is highly probable also. 1396 // consistent with the bcp. The converse is highly probable also.
1415 lduh(ImethodDataPtr, in_bytes(DataLayout::bci_offset()), G3_scratch); 1397 lduh(ImethodDataPtr, in_bytes(DataLayout::bci_offset()), G3_scratch);
1416 ld_ptr(Address(Lmethod, 0, in_bytes(methodOopDesc::const_offset())), O5); 1398 ld_ptr(Lmethod, methodOopDesc::const_offset(), O5);
1417 add(G3_scratch, in_bytes(constMethodOopDesc::codes_offset()), G3_scratch); 1399 add(G3_scratch, in_bytes(constMethodOopDesc::codes_offset()), G3_scratch);
1418 add(G3_scratch, O5, G3_scratch); 1400 add(G3_scratch, O5, G3_scratch);
1419 cmp(Lbcp, G3_scratch); 1401 cmp(Lbcp, G3_scratch);
1420 brx(Assembler::equal, false, Assembler::pt, verify_continue); 1402 brx(Assembler::equal, false, Assembler::pt, verify_continue);
1421 1403
1422 Register temp_reg = O5; 1404 Register temp_reg = O5;
1423 delayed()->mov(ImethodDataPtr, temp_reg); 1405 delayed()->mov(ImethodDataPtr, temp_reg);
1424 // %%% should use call_VM_leaf here? 1406 // %%% should use call_VM_leaf here?
1425 //call_VM_leaf(noreg, ..., Lmethod, Lbcp, ImethodDataPtr); 1407 //call_VM_leaf(noreg, ..., Lmethod, Lbcp, ImethodDataPtr);
1426 save_frame_and_mov(sizeof(jdouble) / wordSize, Lmethod, O0, Lbcp, O1); 1408 save_frame_and_mov(sizeof(jdouble) / wordSize, Lmethod, O0, Lbcp, O1);
1427 Address d_save(FP, 0, -sizeof(jdouble) + STACK_BIAS); 1409 Address d_save(FP, -sizeof(jdouble) + STACK_BIAS);
1428 stf(FloatRegisterImpl::D, Ftos_d, d_save); 1410 stf(FloatRegisterImpl::D, Ftos_d, d_save);
1429 mov(temp_reg->after_save(), O2); 1411 mov(temp_reg->after_save(), O2);
1430 save_thread(L7_thread_cache); 1412 save_thread(L7_thread_cache);
1431 call(CAST_FROM_FN_PTR(address, InterpreterRuntime::verify_mdp), relocInfo::none); 1413 call(CAST_FROM_FN_PTR(address, InterpreterRuntime::verify_mdp), relocInfo::none);
1432 delayed()->nop(); 1414 delayed()->nop();
1454 tst(ImethodDataPtr); 1436 tst(ImethodDataPtr);
1455 br(Assembler::notZero, false, Assembler::pn, done); 1437 br(Assembler::notZero, false, Assembler::pn, done);
1456 #endif 1438 #endif
1457 1439
1458 // Test to see if we should create a method data oop 1440 // Test to see if we should create a method data oop
1459 Address profile_limit(Rtmp, (address)&InvocationCounter::InterpreterProfileLimit); 1441 AddressLiteral profile_limit((address) &InvocationCounter::InterpreterProfileLimit);
1460 #ifdef _LP64 1442 #ifdef _LP64
1461 delayed()->nop(); 1443 delayed()->nop();
1462 sethi(profile_limit); 1444 sethi(profile_limit, Rtmp);
1463 #else 1445 #else
1464 delayed()->sethi(profile_limit); 1446 delayed()->sethi(profile_limit, Rtmp);
1465 #endif 1447 #endif
1466 ld(profile_limit, Rtmp); 1448 ld(Rtmp, profile_limit.low10(), Rtmp);
1467 cmp(invocation_count, Rtmp); 1449 cmp(invocation_count, Rtmp);
1468 br(Assembler::lessUnsigned, false, Assembler::pn, profile_continue); 1450 br(Assembler::lessUnsigned, false, Assembler::pn, profile_continue);
1469 delayed()->nop(); 1451 delayed()->nop();
1470 1452
1471 // Build it now. 1453 // Build it now.
1519 1501
1520 void InterpreterMacroAssembler::increment_mdp_data_at(int constant, 1502 void InterpreterMacroAssembler::increment_mdp_data_at(int constant,
1521 Register bumped_count, 1503 Register bumped_count,
1522 bool decrement) { 1504 bool decrement) {
1523 // Locate the counter at a fixed offset from the mdp: 1505 // Locate the counter at a fixed offset from the mdp:
1524 Address counter(ImethodDataPtr, 0, constant); 1506 Address counter(ImethodDataPtr, constant);
1525 increment_mdp_data_at(counter, bumped_count, decrement); 1507 increment_mdp_data_at(counter, bumped_count, decrement);
1526 } 1508 }
1527 1509
1528 // Increment the value at some non-fixed (reg + constant) offset from 1510 // Increment the value at some non-fixed (reg + constant) offset from
1529 // the method data pointer. 1511 // the method data pointer.
1533 Register bumped_count, 1515 Register bumped_count,
1534 Register scratch2, 1516 Register scratch2,
1535 bool decrement) { 1517 bool decrement) {
1536 // Add the constant to reg to get the offset. 1518 // Add the constant to reg to get the offset.
1537 add(ImethodDataPtr, reg, scratch2); 1519 add(ImethodDataPtr, reg, scratch2);
1538 Address counter(scratch2, 0, constant); 1520 Address counter(scratch2, constant);
1539 increment_mdp_data_at(counter, bumped_count, decrement); 1521 increment_mdp_data_at(counter, bumped_count, decrement);
1540 } 1522 }
1541 1523
1542 // Set a flag value at the current method data pointer position. 1524 // Set a flag value at the current method data pointer position.
1543 // Updates a single byte of the header, to avoid races with other header bits. 1525 // Updates a single byte of the header, to avoid races with other header bits.
2199 return ((-rounded_vm_local_words * wordSize) - delta ) + STACK_BIAS; 2181 return ((-rounded_vm_local_words * wordSize) - delta ) + STACK_BIAS;
2200 } 2182 }
2201 2183
2202 2184
2203 Address InterpreterMacroAssembler::top_most_monitor() { 2185 Address InterpreterMacroAssembler::top_most_monitor() {
2204 return Address(FP, 0, top_most_monitor_byte_offset()); 2186 return Address(FP, top_most_monitor_byte_offset());
2205 } 2187 }
2206 2188
2207 2189
2208 void InterpreterMacroAssembler::compute_stack_base( Register Rdest ) { 2190 void InterpreterMacroAssembler::compute_stack_base( Register Rdest ) {
2209 add( Lesp, wordSize, Rdest ); 2191 add( Lesp, wordSize, Rdest );
2212 #endif /* CC_INTERP */ 2194 #endif /* CC_INTERP */
2213 2195
2214 void InterpreterMacroAssembler::increment_invocation_counter( Register Rtmp, Register Rtmp2 ) { 2196 void InterpreterMacroAssembler::increment_invocation_counter( Register Rtmp, Register Rtmp2 ) {
2215 assert(UseCompiler, "incrementing must be useful"); 2197 assert(UseCompiler, "incrementing must be useful");
2216 #ifdef CC_INTERP 2198 #ifdef CC_INTERP
2217 Address inv_counter(G5_method, 0, in_bytes(methodOopDesc::invocation_counter_offset() 2199 Address inv_counter(G5_method, methodOopDesc::invocation_counter_offset() +
2218 + InvocationCounter::counter_offset())); 2200 InvocationCounter::counter_offset());
2219 Address be_counter(G5_method, 0, in_bytes(methodOopDesc::backedge_counter_offset() 2201 Address be_counter (G5_method, methodOopDesc::backedge_counter_offset() +
2220 + InvocationCounter::counter_offset())); 2202 InvocationCounter::counter_offset());
2221 #else 2203 #else
2222 Address inv_counter(Lmethod, 0, in_bytes(methodOopDesc::invocation_counter_offset() 2204 Address inv_counter(Lmethod, methodOopDesc::invocation_counter_offset() +
2223 + InvocationCounter::counter_offset())); 2205 InvocationCounter::counter_offset());
2224 Address be_counter(Lmethod, 0, in_bytes(methodOopDesc::backedge_counter_offset() 2206 Address be_counter (Lmethod, methodOopDesc::backedge_counter_offset() +
2225 + InvocationCounter::counter_offset())); 2207 InvocationCounter::counter_offset());
2226 #endif /* CC_INTERP */ 2208 #endif /* CC_INTERP */
2227 int delta = InvocationCounter::count_increment; 2209 int delta = InvocationCounter::count_increment;
2228 2210
2229 // Load each counter in a register 2211 // Load each counter in a register
2230 ld( inv_counter, Rtmp ); 2212 ld( inv_counter, Rtmp );
2248 } 2230 }
2249 2231
2250 void InterpreterMacroAssembler::increment_backedge_counter( Register Rtmp, Register Rtmp2 ) { 2232 void InterpreterMacroAssembler::increment_backedge_counter( Register Rtmp, Register Rtmp2 ) {
2251 assert(UseCompiler, "incrementing must be useful"); 2233 assert(UseCompiler, "incrementing must be useful");
2252 #ifdef CC_INTERP 2234 #ifdef CC_INTERP
2253 Address be_counter(G5_method, 0, in_bytes(methodOopDesc::backedge_counter_offset() 2235 Address be_counter (G5_method, methodOopDesc::backedge_counter_offset() +
2254 + InvocationCounter::counter_offset())); 2236 InvocationCounter::counter_offset());
2255 Address inv_counter(G5_method, 0, in_bytes(methodOopDesc::invocation_counter_offset() 2237 Address inv_counter(G5_method, methodOopDesc::invocation_counter_offset() +
2256 + InvocationCounter::counter_offset())); 2238 InvocationCounter::counter_offset());
2257 #else 2239 #else
2258 Address be_counter(Lmethod, 0, in_bytes(methodOopDesc::backedge_counter_offset() 2240 Address be_counter (Lmethod, methodOopDesc::backedge_counter_offset() +
2259 + InvocationCounter::counter_offset())); 2241 InvocationCounter::counter_offset());
2260 Address inv_counter(Lmethod, 0, in_bytes(methodOopDesc::invocation_counter_offset() 2242 Address inv_counter(Lmethod, methodOopDesc::invocation_counter_offset() +
2261 + InvocationCounter::counter_offset())); 2243 InvocationCounter::counter_offset());
2262 #endif /* CC_INTERP */ 2244 #endif /* CC_INTERP */
2263 int delta = InvocationCounter::count_increment; 2245 int delta = InvocationCounter::count_increment;
2264 // Load each counter in a register 2246 // Load each counter in a register
2265 ld( be_counter, Rtmp ); 2247 ld( be_counter, Rtmp );
2266 ld( inv_counter, Rtmp2 ); 2248 ld( inv_counter, Rtmp2 );
2287 Label did_not_overflow; 2269 Label did_not_overflow;
2288 Label overflow_with_error; 2270 Label overflow_with_error;
2289 assert_different_registers(backedge_count, Rtmp, branch_bcp); 2271 assert_different_registers(backedge_count, Rtmp, branch_bcp);
2290 assert(UseOnStackReplacement,"Must UseOnStackReplacement to test_backedge_count_for_osr"); 2272 assert(UseOnStackReplacement,"Must UseOnStackReplacement to test_backedge_count_for_osr");
2291 2273
2292 Address limit(Rtmp, address(&InvocationCounter::InterpreterBackwardBranchLimit)); 2274 AddressLiteral limit(&InvocationCounter::InterpreterBackwardBranchLimit);
2293 load_contents(limit, Rtmp); 2275 load_contents(limit, Rtmp);
2294 cmp(backedge_count, Rtmp); 2276 cmp(backedge_count, Rtmp);
2295 br(Assembler::lessUnsigned, false, Assembler::pt, did_not_overflow); 2277 br(Assembler::lessUnsigned, false, Assembler::pt, did_not_overflow);
2296 delayed()->nop(); 2278 delayed()->nop();
2297 2279
2433 // depth. If it is possible to enter interp_only_mode we add 2415 // depth. If it is possible to enter interp_only_mode we add
2434 // the code to check if the event should be sent. 2416 // the code to check if the event should be sent.
2435 if (JvmtiExport::can_post_interpreter_events()) { 2417 if (JvmtiExport::can_post_interpreter_events()) {
2436 Label L; 2418 Label L;
2437 Register temp_reg = O5; 2419 Register temp_reg = O5;
2438 2420 const Address interp_only(G2_thread, JavaThread::interp_only_mode_offset());
2439 const Address interp_only (G2_thread, 0, in_bytes(JavaThread::interp_only_mode_offset()));
2440
2441 ld(interp_only, temp_reg); 2421 ld(interp_only, temp_reg);
2442 tst(temp_reg); 2422 tst(temp_reg);
2443 br(zero, false, pt, L); 2423 br(zero, false, pt, L);
2444 delayed()->nop(); 2424 delayed()->nop();
2445 call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::post_method_entry)); 2425 call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::post_method_entry));
2487 // depth. If it is possible to enter interp_only_mode we add 2467 // depth. If it is possible to enter interp_only_mode we add
2488 // the code to check if the event should be sent. 2468 // the code to check if the event should be sent.
2489 if (mode == NotifyJVMTI && JvmtiExport::can_post_interpreter_events()) { 2469 if (mode == NotifyJVMTI && JvmtiExport::can_post_interpreter_events()) {
2490 Label L; 2470 Label L;
2491 Register temp_reg = O5; 2471 Register temp_reg = O5;
2492 2472 const Address interp_only(G2_thread, JavaThread::interp_only_mode_offset());
2493 const Address interp_only (G2_thread, 0, in_bytes(JavaThread::interp_only_mode_offset()));
2494
2495 ld(interp_only, temp_reg); 2473 ld(interp_only, temp_reg);
2496 tst(temp_reg); 2474 tst(temp_reg);
2497 br(zero, false, pt, L); 2475 br(zero, false, pt, L);
2498 delayed()->nop(); 2476 delayed()->nop();
2499 2477