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6822110: Add AddressLiteral class on SPARC Summary: The Address class on SPARC currently handles both, addresses and address literals, what makes the Address class more complicated than it has to be. Reviewed-by: never, kvn
author twisti
date Tue, 21 Apr 2009 11:16:30 -0700
parents fbde8ec322d0
children fb4c18a2ec66
comparison
equal deleted inserted replaced
725:928912ce8438 727:6b2273dd6fa9
978 // Calls to the runtime or native may not be reachable from compiled code, 978 // Calls to the runtime or native may not be reachable from compiled code,
979 // so we generate the far call sequence on 64 bit sparc. 979 // so we generate the far call sequence on 64 bit sparc.
980 // This code sequence is relocatable to any address, even on LP64. 980 // This code sequence is relocatable to any address, even on LP64.
981 if ( force_far_call ) { 981 if ( force_far_call ) {
982 __ relocate(rtype); 982 __ relocate(rtype);
983 Address dest(O7, (address)entry_point); 983 AddressLiteral dest(entry_point);
984 __ jumpl_to(dest, O7); 984 __ jumpl_to(dest, O7, O7);
985 } 985 }
986 else 986 else
987 #endif 987 #endif
988 { 988 {
989 __ call((address)entry_point, rtype); 989 __ call((address)entry_point, rtype);
1029 //============================================================================= 1029 //=============================================================================
1030 // REQUIRED FUNCTIONALITY for encoding 1030 // REQUIRED FUNCTIONALITY for encoding
1031 void emit_lo(CodeBuffer &cbuf, int val) { } 1031 void emit_lo(CodeBuffer &cbuf, int val) { }
1032 void emit_hi(CodeBuffer &cbuf, int val) { } 1032 void emit_hi(CodeBuffer &cbuf, int val) { }
1033 1033
1034 void emit_ptr(CodeBuffer &cbuf, intptr_t val, Register reg, bool ForceRelocatable) {
1035 MacroAssembler _masm(&cbuf);
1036 if (ForceRelocatable) {
1037 Address addr(reg, (address)val);
1038 __ sethi(addr, ForceRelocatable);
1039 __ add(addr, reg);
1040 } else {
1041 __ set(val, reg);
1042 }
1043 }
1044
1045 1034
1046 //============================================================================= 1035 //=============================================================================
1047 1036
1048 #ifndef PRODUCT 1037 #ifndef PRODUCT
1049 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1038 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1147 1136
1148 __ verify_thread(); 1137 __ verify_thread();
1149 1138
1150 // If this does safepoint polling, then do it here 1139 // If this does safepoint polling, then do it here
1151 if( do_polling() && ra_->C->is_method_compilation() ) { 1140 if( do_polling() && ra_->C->is_method_compilation() ) {
1152 Address polling_page(L0, (address)os::get_polling_page()); 1141 AddressLiteral polling_page(os::get_polling_page());
1153 __ sethi(polling_page, false); 1142 __ sethi(polling_page, L0);
1154 __ relocate(relocInfo::poll_return_type); 1143 __ relocate(relocInfo::poll_return_type);
1155 __ ld_ptr( L0, 0, G0 ); 1144 __ ld_ptr( L0, 0, G0 );
1156 } 1145 }
1157 1146
1158 // If this is a return, then stuff the restore in the delay slot 1147 // If this is a return, then stuff the restore in the delay slot
1574 __ relocate(static_stub_Relocation::spec(mark)); 1563 __ relocate(static_stub_Relocation::spec(mark));
1575 1564
1576 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); 1565 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1577 1566
1578 __ set_inst_mark(); 1567 __ set_inst_mark();
1579 Address a(G3, (address)-1); 1568 AddressLiteral addrlit(-1);
1580 __ JUMP(a, 0); 1569 __ JUMP(addrlit, G3, 0);
1581 1570
1582 __ delayed()->nop(); 1571 __ delayed()->nop();
1583 1572
1584 // Update current stubs pointer and restore code_end. 1573 // Update current stubs pointer and restore code_end.
1585 __ end_a_stub(); 1574 __ end_a_stub();
1660 } 1649 }
1661 1650
1662 // Emit exception handler code. 1651 // Emit exception handler code.
1663 int emit_exception_handler(CodeBuffer& cbuf) { 1652 int emit_exception_handler(CodeBuffer& cbuf) {
1664 Register temp_reg = G3; 1653 Register temp_reg = G3;
1665 Address exception_blob(temp_reg, OptoRuntime::exception_blob()->instructions_begin()); 1654 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin());
1666 MacroAssembler _masm(&cbuf); 1655 MacroAssembler _masm(&cbuf);
1667 1656
1668 address base = 1657 address base =
1669 __ start_a_stub(size_exception_handler()); 1658 __ start_a_stub(size_exception_handler());
1670 if (base == NULL) return 0; // CodeBuffer::expand failed 1659 if (base == NULL) return 0; // CodeBuffer::expand failed
1671 1660
1672 int offset = __ offset(); 1661 int offset = __ offset();
1673 1662
1674 __ JUMP(exception_blob, 0); // sethi;jmp 1663 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1675 __ delayed()->nop(); 1664 __ delayed()->nop();
1676 1665
1677 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1666 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1678 1667
1679 __ end_a_stub(); 1668 __ end_a_stub();
1683 1672
1684 int emit_deopt_handler(CodeBuffer& cbuf) { 1673 int emit_deopt_handler(CodeBuffer& cbuf) {
1685 // Can't use any of the current frame's registers as we may have deopted 1674 // Can't use any of the current frame's registers as we may have deopted
1686 // at a poll and everything (including G3) can be live. 1675 // at a poll and everything (including G3) can be live.
1687 Register temp_reg = L0; 1676 Register temp_reg = L0;
1688 Address deopt_blob(temp_reg, SharedRuntime::deopt_blob()->unpack()); 1677 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1689 MacroAssembler _masm(&cbuf); 1678 MacroAssembler _masm(&cbuf);
1690 1679
1691 address base = 1680 address base =
1692 __ start_a_stub(size_deopt_handler()); 1681 __ start_a_stub(size_deopt_handler());
1693 if (base == NULL) return 0; // CodeBuffer::expand failed 1682 if (base == NULL) return 0; // CodeBuffer::expand failed
1694 1683
1695 int offset = __ offset(); 1684 int offset = __ offset();
1696 __ save_frame(0); 1685 __ save_frame(0);
1697 __ JUMP(deopt_blob, 0); // sethi;jmp 1686 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1698 __ delayed()->restore(); 1687 __ delayed()->restore();
1699 1688
1700 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1689 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1701 1690
1702 __ end_a_stub(); 1691 __ end_a_stub();
2259 Register table_reg = O7; 2248 Register table_reg = O7;
2260 2249
2261 address table_base = __ address_table_constant(_index2label); 2250 address table_base = __ address_table_constant(_index2label);
2262 RelocationHolder rspec = internal_word_Relocation::spec(table_base); 2251 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
2263 2252
2264 // Load table address 2253 // Move table address into a register.
2265 Address the_pc(table_reg, table_base, rspec); 2254 __ set(table_base, table_reg, rspec);
2266 __ load_address(the_pc);
2267 2255
2268 // Jump to base address + switch value 2256 // Jump to base address + switch value
2269 __ ld_ptr(table_reg, switch_reg, table_reg); 2257 __ ld_ptr(table_reg, switch_reg, table_reg);
2270 __ jmp(table_reg, G0); 2258 __ jmp(table_reg, G0);
2271 __ delayed()->nop(); 2259 __ delayed()->nop();
2400 2388
2401 // Utility encoding for loading a 64 bit Pointer into a register 2389 // Utility encoding for loading a 64 bit Pointer into a register
2402 // The 64 bit pointer is stored in the generated code stream 2390 // The 64 bit pointer is stored in the generated code stream
2403 enc_class SetPtr( immP src, iRegP rd ) %{ 2391 enc_class SetPtr( immP src, iRegP rd ) %{
2404 Register dest = reg_to_register_object($rd$$reg); 2392 Register dest = reg_to_register_object($rd$$reg);
2393 MacroAssembler _masm(&cbuf);
2405 // [RGV] This next line should be generated from ADLC 2394 // [RGV] This next line should be generated from ADLC
2406 if ( _opnds[1]->constant_is_oop() ) { 2395 if ( _opnds[1]->constant_is_oop() ) {
2407 intptr_t val = $src$$constant; 2396 intptr_t val = $src$$constant;
2408 MacroAssembler _masm(&cbuf);
2409 __ set_oop_constant((jobject)val, dest); 2397 __ set_oop_constant((jobject)val, dest);
2410 } else { // non-oop pointers, e.g. card mark base, heap top 2398 } else { // non-oop pointers, e.g. card mark base, heap top
2411 emit_ptr(cbuf, $src$$constant, dest, /*ForceRelocatable=*/ false); 2399 __ set($src$$constant, dest);
2412 } 2400 }
2413 %} 2401 %}
2414 2402
2415 enc_class Set13( immI13 src, iRegI rd ) %{ 2403 enc_class Set13( immI13 src, iRegI rd ) %{
2416 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2404 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2787 Register dest = reg_to_register_object($dst$$reg); 2775 Register dest = reg_to_register_object($dst$$reg);
2788 Register temp = reg_to_register_object($tmp$$reg); 2776 Register temp = reg_to_register_object($tmp$$reg);
2789 __ set64( $src$$constant, dest, temp ); 2777 __ set64( $src$$constant, dest, temp );
2790 %} 2778 %}
2791 2779
2792 enc_class LdImmF(immF src, regF dst, o7RegP tmp) %{ // Load Immediate
2793 address float_address = MacroAssembler(&cbuf).float_constant($src$$constant);
2794 RelocationHolder rspec = internal_word_Relocation::spec(float_address);
2795 #ifdef _LP64
2796 Register tmp_reg = reg_to_register_object($tmp$$reg);
2797 cbuf.relocate(cbuf.code_end(), rspec, 0);
2798 emit_ptr(cbuf, (intptr_t)float_address, tmp_reg, /*ForceRelocatable=*/ true);
2799 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, $tmp$$reg, 0 );
2800 #else // _LP64
2801 uint *code;
2802 int tmp_reg = $tmp$$reg;
2803
2804 cbuf.relocate(cbuf.code_end(), rspec, 0);
2805 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) float_address );
2806
2807 cbuf.relocate(cbuf.code_end(), rspec, 0);
2808 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, tmp_reg, (intptr_t) float_address );
2809 #endif // _LP64
2810 %}
2811
2812 enc_class LdImmD(immD src, regD dst, o7RegP tmp) %{ // Load Immediate
2813 address double_address = MacroAssembler(&cbuf).double_constant($src$$constant);
2814 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2815 #ifdef _LP64
2816 Register tmp_reg = reg_to_register_object($tmp$$reg);
2817 cbuf.relocate(cbuf.code_end(), rspec, 0);
2818 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true);
2819 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 );
2820 #else // _LP64
2821 uint *code;
2822 int tmp_reg = $tmp$$reg;
2823
2824 cbuf.relocate(cbuf.code_end(), rspec, 0);
2825 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address );
2826
2827 cbuf.relocate(cbuf.code_end(), rspec, 0);
2828 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address );
2829 #endif // _LP64
2830 %}
2831
2832 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{ 2780 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
2833 // Load a constant replicated "count" times with width "width" 2781 // Load a constant replicated "count" times with width "width"
2834 int bit_width = $width$$constant * 8; 2782 int bit_width = $width$$constant * 8;
2835 jlong elt_val = $src$$constant; 2783 jlong elt_val = $src$$constant;
2836 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits 2784 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
2838 for (int i = 0; i < $count$$constant - 1; i++) { 2786 for (int i = 0; i < $count$$constant - 1; i++) {
2839 val <<= bit_width; 2787 val <<= bit_width;
2840 val |= elt_val; 2788 val |= elt_val;
2841 } 2789 }
2842 jdouble dval = *(jdouble*)&val; // coerce to double type 2790 jdouble dval = *(jdouble*)&val; // coerce to double type
2843 address double_address = MacroAssembler(&cbuf).double_constant(dval); 2791 MacroAssembler _masm(&cbuf);
2792 address double_address = __ double_constant(dval);
2844 RelocationHolder rspec = internal_word_Relocation::spec(double_address); 2793 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2845 #ifdef _LP64 2794 AddressLiteral addrlit(double_address, rspec);
2846 Register tmp_reg = reg_to_register_object($tmp$$reg); 2795
2847 cbuf.relocate(cbuf.code_end(), rspec, 0); 2796 __ sethi(addrlit, $tmp$$Register);
2848 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true); 2797 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
2849 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 );
2850 #else // _LP64
2851 uint *code;
2852 int tmp_reg = $tmp$$reg;
2853
2854 cbuf.relocate(cbuf.code_end(), rspec, 0);
2855 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address );
2856
2857 cbuf.relocate(cbuf.code_end(), rspec, 0);
2858 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address );
2859 #endif // _LP64
2860 %}
2861
2862
2863 enc_class ShouldNotEncodeThis ( ) %{
2864 ShouldNotCallThis();
2865 %} 2798 %}
2866 2799
2867 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 2800 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2868 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ 2801 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2869 MacroAssembler _masm(&cbuf); 2802 MacroAssembler _masm(&cbuf);
2899 int value_offset = java_lang_String:: value_offset_in_bytes(); 2832 int value_offset = java_lang_String:: value_offset_in_bytes();
2900 int offset_offset = java_lang_String::offset_offset_in_bytes(); 2833 int offset_offset = java_lang_String::offset_offset_in_bytes();
2901 int count_offset = java_lang_String:: count_offset_in_bytes(); 2834 int count_offset = java_lang_String:: count_offset_in_bytes();
2902 2835
2903 // load str1 (jchar*) base address into tmp1_reg 2836 // load str1 (jchar*) base address into tmp1_reg
2904 __ load_heap_oop(Address(str1_reg, 0, value_offset), tmp1_reg); 2837 __ load_heap_oop(str1_reg, value_offset, tmp1_reg);
2905 __ ld(Address(str1_reg, 0, offset_offset), result_reg); 2838 __ ld(str1_reg, offset_offset, result_reg);
2906 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg); 2839 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
2907 __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted 2840 __ ld(str1_reg, count_offset, str1_reg); // hoisted
2908 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); 2841 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2909 __ load_heap_oop(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted 2842 __ load_heap_oop(str2_reg, value_offset, tmp2_reg); // hoisted
2910 __ add(result_reg, tmp1_reg, tmp1_reg); 2843 __ add(result_reg, tmp1_reg, tmp1_reg);
2911 2844
2912 // load str2 (jchar*) base address into tmp2_reg 2845 // load str2 (jchar*) base address into tmp2_reg
2913 // __ ld_ptr(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted 2846 // __ ld_ptr(str2_reg, value_offset, tmp2_reg); // hoisted
2914 __ ld(Address(str2_reg, 0, offset_offset), result_reg); 2847 __ ld(str2_reg, offset_offset, result_reg);
2915 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg); 2848 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
2916 __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted 2849 __ ld(str2_reg, count_offset, str2_reg); // hoisted
2917 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); 2850 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2918 __ subcc(str1_reg, str2_reg, O7); // hoisted 2851 __ subcc(str1_reg, str2_reg, O7); // hoisted
2919 __ add(result_reg, tmp2_reg, tmp2_reg); 2852 __ add(result_reg, tmp2_reg, tmp2_reg);
2920 2853
2921 // Compute the minimum of the string lengths(str1_reg) and the 2854 // Compute the minimum of the string lengths(str1_reg) and the
2922 // difference of the string lengths (stack) 2855 // difference of the string lengths (stack)
2923 2856
2924 // discard string base pointers, after loading up the lengths 2857 // discard string base pointers, after loading up the lengths
2925 // __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted 2858 // __ ld(str1_reg, count_offset, str1_reg); // hoisted
2926 // __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted 2859 // __ ld(str2_reg, count_offset, str2_reg); // hoisted
2927 2860
2928 // See if the lengths are different, and calculate min in str1_reg. 2861 // See if the lengths are different, and calculate min in str1_reg.
2929 // Stash diff in O7 in case we need it for a tie-breaker. 2862 // Stash diff in O7 in case we need it for a tie-breaker.
2930 Label Lskip; 2863 Label Lskip;
2931 // __ subcc(str1_reg, str2_reg, O7); // hoisted 2864 // __ subcc(str1_reg, str2_reg, O7); // hoisted
3018 int value_offset = java_lang_String:: value_offset_in_bytes(); 2951 int value_offset = java_lang_String:: value_offset_in_bytes();
3019 int offset_offset = java_lang_String::offset_offset_in_bytes(); 2952 int offset_offset = java_lang_String::offset_offset_in_bytes();
3020 int count_offset = java_lang_String:: count_offset_in_bytes(); 2953 int count_offset = java_lang_String:: count_offset_in_bytes();
3021 2954
3022 // load str1 (jchar*) base address into tmp1_reg 2955 // load str1 (jchar*) base address into tmp1_reg
3023 __ load_heap_oop(Address(str1_reg, 0, value_offset), tmp1_reg); 2956 __ load_heap_oop(Address(str1_reg, value_offset), tmp1_reg);
3024 __ ld(Address(str1_reg, 0, offset_offset), result_reg); 2957 __ ld(Address(str1_reg, offset_offset), result_reg);
3025 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg); 2958 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
3026 __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted 2959 __ ld(Address(str1_reg, count_offset), str1_reg); // hoisted
3027 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); 2960 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
3028 __ load_heap_oop(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted 2961 __ load_heap_oop(Address(str2_reg, value_offset), tmp2_reg); // hoisted
3029 __ add(result_reg, tmp1_reg, tmp1_reg); 2962 __ add(result_reg, tmp1_reg, tmp1_reg);
3030 2963
3031 // load str2 (jchar*) base address into tmp2_reg 2964 // load str2 (jchar*) base address into tmp2_reg
3032 // __ ld_ptr(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted 2965 // __ ld_ptr(Address(str2_reg, value_offset), tmp2_reg); // hoisted
3033 __ ld(Address(str2_reg, 0, offset_offset), result_reg); 2966 __ ld(Address(str2_reg, offset_offset), result_reg);
3034 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg); 2967 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
3035 __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted 2968 __ ld(Address(str2_reg, count_offset), str2_reg); // hoisted
3036 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); 2969 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
3037 __ cmp(str1_reg, str2_reg); // hoisted 2970 __ cmp(str1_reg, str2_reg); // hoisted
3038 __ add(result_reg, tmp2_reg, tmp2_reg); 2971 __ add(result_reg, tmp2_reg, tmp2_reg);
3039 2972
3040 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); 2973 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg);
3137 3070
3138 __ br_null(ary2_reg, true, Assembler::pn, Ldone); 3071 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3139 __ delayed()->mov(G0, result_reg); // not equal 3072 __ delayed()->mov(G0, result_reg); // not equal
3140 3073
3141 //load the lengths of arrays 3074 //load the lengths of arrays
3142 __ ld(Address(ary1_reg, 0, length_offset), tmp1_reg); 3075 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3143 __ ld(Address(ary2_reg, 0, length_offset), tmp2_reg); 3076 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3144 3077
3145 // return false if the two arrays are not equal length 3078 // return false if the two arrays are not equal length
3146 __ cmp(tmp1_reg, tmp2_reg); 3079 __ cmp(tmp1_reg, tmp2_reg);
3147 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); 3080 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3148 __ delayed()->mov(G0, result_reg); // not equal 3081 __ delayed()->mov(G0, result_reg); // not equal
3200 %} 3133 %}
3201 3134
3202 enc_class enc_rethrow() %{ 3135 enc_class enc_rethrow() %{
3203 cbuf.set_inst_mark(); 3136 cbuf.set_inst_mark();
3204 Register temp_reg = G3; 3137 Register temp_reg = G3;
3205 Address rethrow_stub(temp_reg, OptoRuntime::rethrow_stub()); 3138 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3206 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 3139 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3207 MacroAssembler _masm(&cbuf); 3140 MacroAssembler _masm(&cbuf);
3208 #ifdef ASSERT 3141 #ifdef ASSERT
3209 __ save_frame(0); 3142 __ save_frame(0);
3210 Address last_rethrow_addr(L1, (address)&last_rethrow); 3143 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3211 __ sethi(last_rethrow_addr); 3144 __ sethi(last_rethrow_addrlit, L1);
3145 Address addr(L1, last_rethrow_addrlit.low10());
3212 __ get_pc(L2); 3146 __ get_pc(L2);
3213 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 3147 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3214 __ st_ptr(L2, last_rethrow_addr); 3148 __ st_ptr(L2, addr);
3215 __ restore(); 3149 __ restore();
3216 #endif 3150 #endif
3217 __ JUMP(rethrow_stub, 0); // sethi;jmp 3151 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3218 __ delayed()->nop(); 3152 __ delayed()->nop();
3219 %} 3153 %}
3220 3154
3221 enc_class emit_mem_nop() %{ 3155 enc_class emit_mem_nop() %{
3222 // Generates the instruction LDUXA [o6,g0],#0x82,g0 3156 // Generates the instruction LDUXA [o6,g0],#0x82,g0
5491 match(Set dst (LoadB mem)); 5425 match(Set dst (LoadB mem));
5492 ins_cost(MEMORY_REF_COST); 5426 ins_cost(MEMORY_REF_COST);
5493 5427
5494 size(4); 5428 size(4);
5495 format %{ "LDSB $mem,$dst\t! byte" %} 5429 format %{ "LDSB $mem,$dst\t! byte" %}
5496 opcode(Assembler::ldsb_op3); 5430 ins_encode %{
5497 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5431 __ ldsb($mem$$Address, $dst$$Register);
5432 %}
5498 ins_pipe(iload_mask_mem); 5433 ins_pipe(iload_mask_mem);
5499 %} 5434 %}
5500 5435
5501 // Load Byte (8bit signed) into a Long Register 5436 // Load Byte (8bit signed) into a Long Register
5502 instruct loadB2L(iRegL dst, memory mem) %{ 5437 instruct loadB2L(iRegL dst, memory mem) %{
5503 match(Set dst (ConvI2L (LoadB mem))); 5438 match(Set dst (ConvI2L (LoadB mem)));
5504 ins_cost(MEMORY_REF_COST); 5439 ins_cost(MEMORY_REF_COST);
5505 5440
5506 size(4); 5441 size(4);
5507 format %{ "LDSB $mem,$dst\t! byte -> long" %} 5442 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5508 opcode(Assembler::ldsb_op3); 5443 ins_encode %{
5509 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5444 __ ldsb($mem$$Address, $dst$$Register);
5445 %}
5510 ins_pipe(iload_mask_mem); 5446 ins_pipe(iload_mask_mem);
5511 %} 5447 %}
5512 5448
5513 // Load Unsigned Byte (8bit UNsigned) into an int reg 5449 // Load Unsigned Byte (8bit UNsigned) into an int reg
5514 instruct loadUB(iRegI dst, memory mem) %{ 5450 instruct loadUB(iRegI dst, memory mem) %{
5515 match(Set dst (LoadUB mem)); 5451 match(Set dst (LoadUB mem));
5516 ins_cost(MEMORY_REF_COST); 5452 ins_cost(MEMORY_REF_COST);
5517 5453
5518 size(4); 5454 size(4);
5519 format %{ "LDUB $mem,$dst\t! ubyte" %} 5455 format %{ "LDUB $mem,$dst\t! ubyte" %}
5520 opcode(Assembler::ldub_op3); 5456 ins_encode %{
5521 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5457 __ ldub($mem$$Address, $dst$$Register);
5458 %}
5522 ins_pipe(iload_mask_mem); 5459 ins_pipe(iload_mask_mem);
5523 %} 5460 %}
5524 5461
5525 // Load Unsigned Byte (8bit UNsigned) into a Long Register 5462 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5526 instruct loadUB2L(iRegL dst, memory mem) %{ 5463 instruct loadUB2L(iRegL dst, memory mem) %{
5527 match(Set dst (ConvI2L (LoadUB mem))); 5464 match(Set dst (ConvI2L (LoadUB mem)));
5528 ins_cost(MEMORY_REF_COST); 5465 ins_cost(MEMORY_REF_COST);
5529 5466
5530 size(4); 5467 size(4);
5531 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} 5468 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5532 opcode(Assembler::ldub_op3); 5469 ins_encode %{
5533 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5470 __ ldub($mem$$Address, $dst$$Register);
5471 %}
5534 ins_pipe(iload_mask_mem); 5472 ins_pipe(iload_mask_mem);
5535 %} 5473 %}
5536 5474
5537 // Load Short (16bit signed) 5475 // Load Short (16bit signed)
5538 instruct loadS(iRegI dst, memory mem) %{ 5476 instruct loadS(iRegI dst, memory mem) %{
5539 match(Set dst (LoadS mem)); 5477 match(Set dst (LoadS mem));
5540 ins_cost(MEMORY_REF_COST); 5478 ins_cost(MEMORY_REF_COST);
5541 5479
5542 size(4); 5480 size(4);
5543 format %{ "LDSH $mem,$dst\t! short" %} 5481 format %{ "LDSH $mem,$dst\t! short" %}
5544 opcode(Assembler::ldsh_op3); 5482 ins_encode %{
5545 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5483 __ ldsh($mem$$Address, $dst$$Register);
5484 %}
5546 ins_pipe(iload_mask_mem); 5485 ins_pipe(iload_mask_mem);
5547 %} 5486 %}
5548 5487
5549 // Load Short (16bit signed) into a Long Register 5488 // Load Short (16bit signed) into a Long Register
5550 instruct loadS2L(iRegL dst, memory mem) %{ 5489 instruct loadS2L(iRegL dst, memory mem) %{
5551 match(Set dst (ConvI2L (LoadS mem))); 5490 match(Set dst (ConvI2L (LoadS mem)));
5552 ins_cost(MEMORY_REF_COST); 5491 ins_cost(MEMORY_REF_COST);
5553 5492
5554 size(4); 5493 size(4);
5555 format %{ "LDSH $mem,$dst\t! short -> long" %} 5494 format %{ "LDSH $mem,$dst\t! short -> long" %}
5556 opcode(Assembler::ldsh_op3); 5495 ins_encode %{
5557 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5496 __ ldsh($mem$$Address, $dst$$Register);
5497 %}
5558 ins_pipe(iload_mask_mem); 5498 ins_pipe(iload_mask_mem);
5559 %} 5499 %}
5560 5500
5561 // Load Unsigned Short/Char (16bit UNsigned) 5501 // Load Unsigned Short/Char (16bit UNsigned)
5562 instruct loadUS(iRegI dst, memory mem) %{ 5502 instruct loadUS(iRegI dst, memory mem) %{
5563 match(Set dst (LoadUS mem)); 5503 match(Set dst (LoadUS mem));
5564 ins_cost(MEMORY_REF_COST); 5504 ins_cost(MEMORY_REF_COST);
5565 5505
5566 size(4); 5506 size(4);
5567 format %{ "LDUH $mem,$dst\t! ushort/char" %} 5507 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5568 opcode(Assembler::lduh_op3); 5508 ins_encode %{
5569 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5509 __ lduh($mem$$Address, $dst$$Register);
5510 %}
5570 ins_pipe(iload_mask_mem); 5511 ins_pipe(iload_mask_mem);
5571 %} 5512 %}
5572 5513
5573 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register 5514 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5574 instruct loadUS2L(iRegL dst, memory mem) %{ 5515 instruct loadUS2L(iRegL dst, memory mem) %{
5575 match(Set dst (ConvI2L (LoadUS mem))); 5516 match(Set dst (ConvI2L (LoadUS mem)));
5576 ins_cost(MEMORY_REF_COST); 5517 ins_cost(MEMORY_REF_COST);
5577 5518
5578 size(4); 5519 size(4);
5579 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} 5520 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5580 opcode(Assembler::lduh_op3); 5521 ins_encode %{
5581 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5522 __ lduh($mem$$Address, $dst$$Register);
5523 %}
5582 ins_pipe(iload_mask_mem); 5524 ins_pipe(iload_mask_mem);
5583 %} 5525 %}
5584 5526
5585 // Load Integer 5527 // Load Integer
5586 instruct loadI(iRegI dst, memory mem) %{ 5528 instruct loadI(iRegI dst, memory mem) %{
5587 match(Set dst (LoadI mem)); 5529 match(Set dst (LoadI mem));
5588 ins_cost(MEMORY_REF_COST); 5530 ins_cost(MEMORY_REF_COST);
5589 5531
5590 size(4); 5532 size(4);
5591 format %{ "LDUW $mem,$dst\t! int" %} 5533 format %{ "LDUW $mem,$dst\t! int" %}
5592 opcode(Assembler::lduw_op3); 5534 ins_encode %{
5593 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5535 __ lduw($mem$$Address, $dst$$Register);
5536 %}
5594 ins_pipe(iload_mem); 5537 ins_pipe(iload_mem);
5595 %} 5538 %}
5596 5539
5597 // Load Integer into a Long Register 5540 // Load Integer into a Long Register
5598 instruct loadI2L(iRegL dst, memory mem) %{ 5541 instruct loadI2L(iRegL dst, memory mem) %{
5599 match(Set dst (ConvI2L (LoadI mem))); 5542 match(Set dst (ConvI2L (LoadI mem)));
5600 ins_cost(MEMORY_REF_COST); 5543 ins_cost(MEMORY_REF_COST);
5601 5544
5602 size(4); 5545 size(4);
5603 format %{ "LDSW $mem,$dst\t! int -> long" %} 5546 format %{ "LDSW $mem,$dst\t! int -> long" %}
5604 opcode(Assembler::ldsw_op3); 5547 ins_encode %{
5605 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5548 __ ldsw($mem$$Address, $dst$$Register);
5549 %}
5606 ins_pipe(iload_mem); 5550 ins_pipe(iload_mem);
5607 %} 5551 %}
5608 5552
5609 // Load Unsigned Integer into a Long Register 5553 // Load Unsigned Integer into a Long Register
5610 instruct loadUI2L(iRegL dst, memory mem) %{ 5554 instruct loadUI2L(iRegL dst, memory mem) %{
5611 match(Set dst (LoadUI2L mem)); 5555 match(Set dst (LoadUI2L mem));
5612 ins_cost(MEMORY_REF_COST); 5556 ins_cost(MEMORY_REF_COST);
5613 5557
5614 size(4); 5558 size(4);
5615 format %{ "LDUW $mem,$dst\t! uint -> long" %} 5559 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5616 opcode(Assembler::lduw_op3); 5560 ins_encode %{
5617 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5561 __ lduw($mem$$Address, $dst$$Register);
5562 %}
5618 ins_pipe(iload_mem); 5563 ins_pipe(iload_mem);
5619 %} 5564 %}
5620 5565
5621 // Load Long - aligned 5566 // Load Long - aligned
5622 instruct loadL(iRegL dst, memory mem ) %{ 5567 instruct loadL(iRegL dst, memory mem ) %{
5623 match(Set dst (LoadL mem)); 5568 match(Set dst (LoadL mem));
5624 ins_cost(MEMORY_REF_COST); 5569 ins_cost(MEMORY_REF_COST);
5625 5570
5626 size(4); 5571 size(4);
5627 format %{ "LDX $mem,$dst\t! long" %} 5572 format %{ "LDX $mem,$dst\t! long" %}
5628 opcode(Assembler::ldx_op3); 5573 ins_encode %{
5629 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5574 __ ldx($mem$$Address, $dst$$Register);
5575 %}
5630 ins_pipe(iload_mem); 5576 ins_pipe(iload_mem);
5631 %} 5577 %}
5632 5578
5633 // Load Long - UNaligned 5579 // Load Long - UNaligned
5634 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5580 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5719 ins_cost(MEMORY_REF_COST); 5665 ins_cost(MEMORY_REF_COST);
5720 size(4); 5666 size(4);
5721 5667
5722 #ifndef _LP64 5668 #ifndef _LP64
5723 format %{ "LDUW $mem,$dst\t! ptr" %} 5669 format %{ "LDUW $mem,$dst\t! ptr" %}
5724 opcode(Assembler::lduw_op3, 0, REGP_OP); 5670 ins_encode %{
5671 __ lduw($mem$$Address, $dst$$Register);
5672 %}
5725 #else 5673 #else
5726 format %{ "LDX $mem,$dst\t! ptr" %} 5674 format %{ "LDX $mem,$dst\t! ptr" %}
5727 opcode(Assembler::ldx_op3, 0, REGP_OP); 5675 ins_encode %{
5676 __ ldx($mem$$Address, $dst$$Register);
5677 %}
5728 #endif 5678 #endif
5729 ins_encode( form3_mem_reg( mem, dst ) );
5730 ins_pipe(iload_mem); 5679 ins_pipe(iload_mem);
5731 %} 5680 %}
5732 5681
5733 // Load Compressed Pointer 5682 // Load Compressed Pointer
5734 instruct loadN(iRegN dst, memory mem) %{ 5683 instruct loadN(iRegN dst, memory mem) %{
5735 match(Set dst (LoadN mem)); 5684 match(Set dst (LoadN mem));
5736 ins_cost(MEMORY_REF_COST); 5685 ins_cost(MEMORY_REF_COST);
5737 size(4); 5686 size(4);
5738 5687
5739 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 5688 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5740 ins_encode %{ 5689 ins_encode %{
5741 Register index = $mem$$index$$Register; 5690 __ lduw($mem$$Address, $dst$$Register);
5742 if (index != G0) { 5691 %}
5743 __ lduw($mem$$base$$Register, index, $dst$$Register); 5692 ins_pipe(iload_mem);
5744 } else {
5745 __ lduw($mem$$base$$Register, $mem$$disp, $dst$$Register);
5746 }
5747 %}
5748 ins_pipe(iload_mem);
5749 %} 5693 %}
5750 5694
5751 // Load Klass Pointer 5695 // Load Klass Pointer
5752 instruct loadKlass(iRegP dst, memory mem) %{ 5696 instruct loadKlass(iRegP dst, memory mem) %{
5753 match(Set dst (LoadKlass mem)); 5697 match(Set dst (LoadKlass mem));
5754 ins_cost(MEMORY_REF_COST); 5698 ins_cost(MEMORY_REF_COST);
5755 size(4); 5699 size(4);
5756 5700
5757 #ifndef _LP64 5701 #ifndef _LP64
5758 format %{ "LDUW $mem,$dst\t! klass ptr" %} 5702 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5759 opcode(Assembler::lduw_op3, 0, REGP_OP); 5703 ins_encode %{
5704 __ lduw($mem$$Address, $dst$$Register);
5705 %}
5760 #else 5706 #else
5761 format %{ "LDX $mem,$dst\t! klass ptr" %} 5707 format %{ "LDX $mem,$dst\t! klass ptr" %}
5762 opcode(Assembler::ldx_op3, 0, REGP_OP); 5708 ins_encode %{
5709 __ ldx($mem$$Address, $dst$$Register);
5710 %}
5763 #endif 5711 #endif
5764 ins_encode( form3_mem_reg( mem, dst ) );
5765 ins_pipe(iload_mem); 5712 ins_pipe(iload_mem);
5766 %} 5713 %}
5767 5714
5768 // Load narrow Klass Pointer 5715 // Load narrow Klass Pointer
5769 instruct loadNKlass(iRegN dst, memory mem) %{ 5716 instruct loadNKlass(iRegN dst, memory mem) %{
5770 match(Set dst (LoadNKlass mem)); 5717 match(Set dst (LoadNKlass mem));
5771 ins_cost(MEMORY_REF_COST); 5718 ins_cost(MEMORY_REF_COST);
5772 size(4); 5719 size(4);
5773 5720
5774 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 5721 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5775
5776 ins_encode %{ 5722 ins_encode %{
5777 Register base = as_Register($mem$$base); 5723 __ lduw($mem$$Address, $dst$$Register);
5778 Register index = as_Register($mem$$index);
5779 Register dst = $dst$$Register;
5780 if (index != G0) {
5781 __ lduw(base, index, dst);
5782 } else {
5783 __ lduw(base, $mem$$disp, dst);
5784 }
5785 %} 5724 %}
5786 ins_pipe(iload_mem); 5725 ins_pipe(iload_mem);
5787 %} 5726 %}
5788 5727
5789 // Load Double 5728 // Load Double
5865 instruct loadConP_poll(iRegP dst, immP_poll src) %{ 5804 instruct loadConP_poll(iRegP dst, immP_poll src) %{
5866 match(Set dst src); 5805 match(Set dst src);
5867 ins_cost(DEFAULT_COST); 5806 ins_cost(DEFAULT_COST);
5868 format %{ "SET $src,$dst\t!ptr" %} 5807 format %{ "SET $src,$dst\t!ptr" %}
5869 ins_encode %{ 5808 ins_encode %{
5870 Address polling_page(reg_to_register_object($dst$$reg), (address)os::get_polling_page()); 5809 AddressLiteral polling_page(os::get_polling_page());
5871 __ sethi(polling_page, false ); 5810 __ sethi(polling_page, reg_to_register_object($dst$$reg));
5872 %} 5811 %}
5873 ins_pipe(loadConP_poll); 5812 ins_pipe(loadConP_poll);
5874 %} 5813 %}
5875 5814
5876 instruct loadConN0(iRegN dst, immN0 src) %{ 5815 instruct loadConN0(iRegN dst, immN0 src) %{
5925 instruct loadConF(regF dst, immF src, o7RegP tmp) %{ 5864 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
5926 match(Set dst src); 5865 match(Set dst src);
5927 effect(KILL tmp); 5866 effect(KILL tmp);
5928 5867
5929 #ifdef _LP64 5868 #ifdef _LP64
5930 size(36); 5869 size(8*4);
5931 #else 5870 #else
5932 size(8); 5871 size(2*4);
5933 #endif 5872 #endif
5934 5873
5935 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t" 5874 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t"
5936 "LDF [$tmp+lo(&$src)],$dst" %} 5875 "LDF [$tmp+lo(&$src)],$dst" %}
5937 ins_encode( LdImmF(src, dst, tmp) ); 5876 ins_encode %{
5877 address float_address = __ float_constant($src$$constant);
5878 RelocationHolder rspec = internal_word_Relocation::spec(float_address);
5879 AddressLiteral addrlit(float_address, rspec);
5880
5881 __ sethi(addrlit, $tmp$$Register);
5882 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
5883 %}
5938 ins_pipe(loadConFD); 5884 ins_pipe(loadConFD);
5939 %} 5885 %}
5940 5886
5941 instruct loadConD(regD dst, immD src, o7RegP tmp) %{ 5887 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
5942 match(Set dst src); 5888 match(Set dst src);
5943 effect(KILL tmp); 5889 effect(KILL tmp);
5944 5890
5945 #ifdef _LP64 5891 #ifdef _LP64
5946 size(36); 5892 size(8*4);
5947 #else 5893 #else
5948 size(8); 5894 size(2*4);
5949 #endif 5895 #endif
5950 5896
5951 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t" 5897 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t"
5952 "LDDF [$tmp+lo(&$src)],$dst" %} 5898 "LDDF [$tmp+lo(&$src)],$dst" %}
5953 ins_encode( LdImmD(src, dst, tmp) ); 5899 ins_encode %{
5900 address double_address = __ double_constant($src$$constant);
5901 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
5902 AddressLiteral addrlit(double_address, rspec);
5903
5904 __ sethi(addrlit, $tmp$$Register);
5905 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
5906 %}
5954 ins_pipe(loadConFD); 5907 ins_pipe(loadConFD);
5955 %} 5908 %}
5956 5909
5957 // Prefetch instructions. 5910 // Prefetch instructions.
5958 // Must be safe to execute with invalid address (cannot fault). 5911 // Must be safe to execute with invalid address (cannot fault).