Mercurial > hg > truffle
comparison src/cpu/x86/vm/x86_64.ad @ 12056:740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
8016729: ObjectAlignmentInBytes=16 now forces the use of heap based compressed oops
8005933: The -Xshare:auto option is ignored for -server
Summary: Move klass metaspace above the heap and support CDS with compressed klass ptrs.
Reviewed-by: coleenp, kvn, mgerdin, tschatzl, stefank
author | hseigel |
---|---|
date | Thu, 15 Aug 2013 20:04:10 -0400 |
parents | 78603aa58b1e |
children | 7944aba7ba41 6a936747b569 |
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12055:d96f52012aaa | 12056:740e263c80c6 |
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1391 #ifndef PRODUCT | 1391 #ifndef PRODUCT |
1392 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const | 1392 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const |
1393 { | 1393 { |
1394 if (UseCompressedKlassPointers) { | 1394 if (UseCompressedKlassPointers) { |
1395 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass"); | 1395 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass"); |
1396 if (Universe::narrow_klass_shift() != 0) { | 1396 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1"); |
1397 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1"); | |
1398 } | |
1399 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check"); | 1397 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check"); |
1400 } else { | 1398 } else { |
1401 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t" | 1399 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t" |
1402 "# Inline cache check"); | 1400 "# Inline cache check"); |
1403 } | 1401 } |
4033 scale($scale); | 4031 scale($scale); |
4034 disp($off); | 4032 disp($off); |
4035 %} | 4033 %} |
4036 %} | 4034 %} |
4037 | 4035 |
4038 operand indirectNarrowKlass(rRegN reg) | |
4039 %{ | |
4040 predicate(Universe::narrow_klass_shift() == 0); | |
4041 constraint(ALLOC_IN_RC(ptr_reg)); | |
4042 match(DecodeNKlass reg); | |
4043 | |
4044 format %{ "[$reg]" %} | |
4045 interface(MEMORY_INTER) %{ | |
4046 base($reg); | |
4047 index(0x4); | |
4048 scale(0x0); | |
4049 disp(0x0); | |
4050 %} | |
4051 %} | |
4052 | |
4053 operand indOffset8NarrowKlass(rRegN reg, immL8 off) | |
4054 %{ | |
4055 predicate(Universe::narrow_klass_shift() == 0); | |
4056 constraint(ALLOC_IN_RC(ptr_reg)); | |
4057 match(AddP (DecodeNKlass reg) off); | |
4058 | |
4059 format %{ "[$reg + $off (8-bit)]" %} | |
4060 interface(MEMORY_INTER) %{ | |
4061 base($reg); | |
4062 index(0x4); | |
4063 scale(0x0); | |
4064 disp($off); | |
4065 %} | |
4066 %} | |
4067 | |
4068 operand indOffset32NarrowKlass(rRegN reg, immL32 off) | |
4069 %{ | |
4070 predicate(Universe::narrow_klass_shift() == 0); | |
4071 constraint(ALLOC_IN_RC(ptr_reg)); | |
4072 match(AddP (DecodeNKlass reg) off); | |
4073 | |
4074 format %{ "[$reg + $off (32-bit)]" %} | |
4075 interface(MEMORY_INTER) %{ | |
4076 base($reg); | |
4077 index(0x4); | |
4078 scale(0x0); | |
4079 disp($off); | |
4080 %} | |
4081 %} | |
4082 | |
4083 operand indIndexOffsetNarrowKlass(rRegN reg, rRegL lreg, immL32 off) | |
4084 %{ | |
4085 predicate(Universe::narrow_klass_shift() == 0); | |
4086 constraint(ALLOC_IN_RC(ptr_reg)); | |
4087 match(AddP (AddP (DecodeNKlass reg) lreg) off); | |
4088 | |
4089 op_cost(10); | |
4090 format %{"[$reg + $off + $lreg]" %} | |
4091 interface(MEMORY_INTER) %{ | |
4092 base($reg); | |
4093 index($lreg); | |
4094 scale(0x0); | |
4095 disp($off); | |
4096 %} | |
4097 %} | |
4098 | |
4099 operand indIndexNarrowKlass(rRegN reg, rRegL lreg) | |
4100 %{ | |
4101 predicate(Universe::narrow_klass_shift() == 0); | |
4102 constraint(ALLOC_IN_RC(ptr_reg)); | |
4103 match(AddP (DecodeNKlass reg) lreg); | |
4104 | |
4105 op_cost(10); | |
4106 format %{"[$reg + $lreg]" %} | |
4107 interface(MEMORY_INTER) %{ | |
4108 base($reg); | |
4109 index($lreg); | |
4110 scale(0x0); | |
4111 disp(0x0); | |
4112 %} | |
4113 %} | |
4114 | |
4115 operand indIndexScaleNarrowKlass(rRegN reg, rRegL lreg, immI2 scale) | |
4116 %{ | |
4117 predicate(Universe::narrow_klass_shift() == 0); | |
4118 constraint(ALLOC_IN_RC(ptr_reg)); | |
4119 match(AddP (DecodeNKlass reg) (LShiftL lreg scale)); | |
4120 | |
4121 op_cost(10); | |
4122 format %{"[$reg + $lreg << $scale]" %} | |
4123 interface(MEMORY_INTER) %{ | |
4124 base($reg); | |
4125 index($lreg); | |
4126 scale($scale); | |
4127 disp(0x0); | |
4128 %} | |
4129 %} | |
4130 | |
4131 operand indIndexScaleOffsetNarrowKlass(rRegN reg, immL32 off, rRegL lreg, immI2 scale) | |
4132 %{ | |
4133 predicate(Universe::narrow_klass_shift() == 0); | |
4134 constraint(ALLOC_IN_RC(ptr_reg)); | |
4135 match(AddP (AddP (DecodeNKlass reg) (LShiftL lreg scale)) off); | |
4136 | |
4137 op_cost(10); | |
4138 format %{"[$reg + $off + $lreg << $scale]" %} | |
4139 interface(MEMORY_INTER) %{ | |
4140 base($reg); | |
4141 index($lreg); | |
4142 scale($scale); | |
4143 disp($off); | |
4144 %} | |
4145 %} | |
4146 | |
4147 operand indCompressedKlassOffset(rRegN reg, immL32 off) %{ | |
4148 predicate(UseCompressedKlassPointers && (Universe::narrow_klass_shift() == Address::times_8)); | |
4149 constraint(ALLOC_IN_RC(ptr_reg)); | |
4150 match(AddP (DecodeNKlass reg) off); | |
4151 | |
4152 op_cost(10); | |
4153 format %{"[R12 + $reg << 3 + $off] (compressed klass addressing)" %} | |
4154 interface(MEMORY_INTER) %{ | |
4155 base(0xc); // R12 | |
4156 index($reg); | |
4157 scale(0x3); | |
4158 disp($off); | |
4159 %} | |
4160 %} | |
4161 | |
4162 operand indPosIndexScaleOffsetNarrowKlass(rRegN reg, immL32 off, rRegI idx, immI2 scale) | |
4163 %{ | |
4164 constraint(ALLOC_IN_RC(ptr_reg)); | |
4165 predicate(Universe::narrow_klass_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); | |
4166 match(AddP (AddP (DecodeNKlass reg) (LShiftL (ConvI2L idx) scale)) off); | |
4167 | |
4168 op_cost(10); | |
4169 format %{"[$reg + $off + $idx << $scale]" %} | |
4170 interface(MEMORY_INTER) %{ | |
4171 base($reg); | |
4172 index($idx); | |
4173 scale($scale); | |
4174 disp($off); | |
4175 %} | |
4176 %} | |
4177 | |
4178 //----------Special Memory Operands-------------------------------------------- | 4036 //----------Special Memory Operands-------------------------------------------- |
4179 // Stack Slot Operand - This operand is used for loading and storing temporary | 4037 // Stack Slot Operand - This operand is used for loading and storing temporary |
4180 // values on the stack where a match requires a value to | 4038 // values on the stack where a match requires a value to |
4181 // flow through memory. | 4039 // flow through memory. |
4182 operand stackSlotP(sRegP reg) | 4040 operand stackSlotP(sRegP reg) |
4343 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, | 4201 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, |
4344 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, | 4202 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
4345 indCompressedOopOffset, | 4203 indCompressedOopOffset, |
4346 indirectNarrow, indOffset8Narrow, indOffset32Narrow, | 4204 indirectNarrow, indOffset8Narrow, indOffset32Narrow, |
4347 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, | 4205 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, |
4348 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow, | 4206 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow); |
4349 indCompressedKlassOffset, | |
4350 indirectNarrowKlass, indOffset8NarrowKlass, indOffset32NarrowKlass, | |
4351 indIndexOffsetNarrowKlass, indIndexNarrowKlass, indIndexScaleNarrowKlass, | |
4352 indIndexScaleOffsetNarrowKlass, indPosIndexScaleOffsetNarrowKlass); | |
4353 | 4207 |
4354 //----------PIPELINE----------------------------------------------------------- | 4208 //----------PIPELINE----------------------------------------------------------- |
4355 // Rules which define the behavior of the target architectures pipeline. | 4209 // Rules which define the behavior of the target architectures pipeline. |
4356 pipeline %{ | 4210 pipeline %{ |
4357 | 4211 |
6663 %} | 6517 %} |
6664 | 6518 |
6665 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ | 6519 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
6666 match(Set dst (EncodePKlass src)); | 6520 match(Set dst (EncodePKlass src)); |
6667 effect(KILL cr); | 6521 effect(KILL cr); |
6668 format %{ "encode_heap_oop_not_null $dst,$src" %} | 6522 format %{ "encode_klass_not_null $dst,$src" %} |
6669 ins_encode %{ | 6523 ins_encode %{ |
6670 __ encode_klass_not_null($dst$$Register, $src$$Register); | 6524 __ encode_klass_not_null($dst$$Register, $src$$Register); |
6671 %} | 6525 %} |
6672 ins_pipe(ialu_reg_long); | 6526 ins_pipe(ialu_reg_long); |
6673 %} | 6527 %} |
6674 | 6528 |
6675 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ | 6529 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
6676 match(Set dst (DecodeNKlass src)); | 6530 match(Set dst (DecodeNKlass src)); |
6677 effect(KILL cr); | 6531 effect(KILL cr); |
6678 format %{ "decode_heap_oop_not_null $dst,$src" %} | 6532 format %{ "decode_klass_not_null $dst,$src" %} |
6679 ins_encode %{ | 6533 ins_encode %{ |
6680 Register s = $src$$Register; | 6534 Register s = $src$$Register; |
6681 Register d = $dst$$Register; | 6535 Register d = $dst$$Register; |
6682 if (s != d) { | 6536 if (s != d) { |
6683 __ decode_klass_not_null(d, s); | 6537 __ decode_klass_not_null(d, s); |