Mercurial > hg > truffle

comparison src/cpu/x86/vm/vm_version_x86.cpp @ 1622:76efbe666d6c

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
6964774: Adjust optimization flags setting Summary: Adjust performance flags settings. Reviewed-by: never, phh
author kvn
date Tue, 29 Jun 2010 10:34:00 -0700
parents c18cbe5936b8
children f55c4f82ab9d
comparison
equal deleted inserted replaced
1621:6027dddc26c6 1622:76efbe666d6c
1 /* 1 /*
2 * Copyright (c) 1997, 2009, Oracle and/or its affiliates. All rights reserved. 2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 * 4 *
5 * This code is free software; you can redistribute it and/or modify it 5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as 6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
32 int VM_Version::_cpuFeatures; 32 int VM_Version::_cpuFeatures;
33 const char* VM_Version::_features_str = ""; 33 const char* VM_Version::_features_str = "";
34 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; 34 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
35 35
36 static BufferBlob* stub_blob; 36 static BufferBlob* stub_blob;
37 static const int stub_size = 300; 37 static const int stub_size = 400;
38 38
39 extern "C" { 39 extern "C" {
40 typedef void (*getPsrInfo_stub_t)(void*); 40 typedef void (*getPsrInfo_stub_t)(void*);
41 } 41 }
42 static getPsrInfo_stub_t getPsrInfo_stub = NULL; 42 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
54 // Values for when we don't have a CPUID instruction. 54 // Values for when we don't have a CPUID instruction.
55 const int CPU_FAMILY_SHIFT = 8; 55 const int CPU_FAMILY_SHIFT = 8;
56 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); 56 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
57 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); 57 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
58 58
59 Label detect_486, cpu486, detect_586, std_cpuid1; 59 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
60 Label ext_cpuid1, ext_cpuid5, done; 60 Label ext_cpuid1, ext_cpuid5, done;
61 61
62 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); 62 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
63 # define __ _masm-> 63 # define __ _masm->
64 64
129 __ movl(Address(rsi, 0), rax); 129 __ movl(Address(rsi, 0), rax);
130 __ movl(Address(rsi, 4), rbx); 130 __ movl(Address(rsi, 4), rbx);
131 __ movl(Address(rsi, 8), rcx); 131 __ movl(Address(rsi, 8), rcx);
132 __ movl(Address(rsi,12), rdx); 132 __ movl(Address(rsi,12), rdx);
133 133
134 __ cmpl(rax, 3); // Is cpuid(0x4) supported? 134 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
135 __ jccb(Assembler::belowEqual, std_cpuid1); 135 __ jccb(Assembler::belowEqual, std_cpuid4);
136
137 //
138 // cpuid(0xB) Processor Topology
139 //
140 __ movl(rax, 0xb);
141 __ xorl(rcx, rcx); // Threads level
142 __ cpuid();
143
144 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
145 __ movl(Address(rsi, 0), rax);
146 __ movl(Address(rsi, 4), rbx);
147 __ movl(Address(rsi, 8), rcx);
148 __ movl(Address(rsi,12), rdx);
149
150 __ movl(rax, 0xb);
151 __ movl(rcx, 1); // Cores level
152 __ cpuid();
153 __ push(rax);
154 __ andl(rax, 0x1f); // Determine if valid topology level
155 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
156 __ andl(rax, 0xffff);
157 __ pop(rax);
158 __ jccb(Assembler::equal, std_cpuid4);
159
160 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
161 __ movl(Address(rsi, 0), rax);
162 __ movl(Address(rsi, 4), rbx);
163 __ movl(Address(rsi, 8), rcx);
164 __ movl(Address(rsi,12), rdx);
165
166 __ movl(rax, 0xb);
167 __ movl(rcx, 2); // Packages level
168 __ cpuid();
169 __ push(rax);
170 __ andl(rax, 0x1f); // Determine if valid topology level
171 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
172 __ andl(rax, 0xffff);
173 __ pop(rax);
174 __ jccb(Assembler::equal, std_cpuid4);
175
176 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
177 __ movl(Address(rsi, 0), rax);
178 __ movl(Address(rsi, 4), rbx);
179 __ movl(Address(rsi, 8), rcx);
180 __ movl(Address(rsi,12), rdx);
136 181
137 // 182 //
138 // cpuid(0x4) Deterministic cache params 183 // cpuid(0x4) Deterministic cache params
139 // 184 //
185 __ bind(std_cpuid4);
140 __ movl(rax, 4); 186 __ movl(rax, 4);
187 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
188 __ jccb(Assembler::greater, std_cpuid1);
189
141 __ xorl(rcx, rcx); // L1 cache 190 __ xorl(rcx, rcx); // L1 cache
142 __ cpuid(); 191 __ cpuid();
143 __ push(rax); 192 __ push(rax);
144 __ andl(rax, 0x1f); // Determine if valid cache parameters used 193 __ andl(rax, 0x1f); // Determine if valid cache parameters used
145 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache 194 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
458 AllocatePrefetchLines = 1; // Conservative value 507 AllocatePrefetchLines = 1; // Conservative value
459 508
460 AllocatePrefetchDistance = allocate_prefetch_distance(); 509 AllocatePrefetchDistance = allocate_prefetch_distance();
461 AllocatePrefetchStyle = allocate_prefetch_style(); 510 AllocatePrefetchStyle = allocate_prefetch_style();
462 511
463 if( AllocatePrefetchStyle == 2 && is_intel() && 512 if( is_intel() && cpu_family() == 6 && supports_sse3() ) {
464 cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core 513 if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core
465 #ifdef _LP64 514 #ifdef _LP64
466 AllocatePrefetchDistance = 384; 515 AllocatePrefetchDistance = 384;
467 #else 516 #else
468 AllocatePrefetchDistance = 320; 517 AllocatePrefetchDistance = 320;
469 #endif 518 #endif
519 }
520 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus
521 AllocatePrefetchDistance = 192;
522 AllocatePrefetchLines = 4;
523 }
470 } 524 }
471 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); 525 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
472 526
473 #ifdef _LP64 527 #ifdef _LP64
474 // Prefetch settings 528 // Prefetch settings