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comparison src/cpu/sparc/vm/assembler_sparc.hpp @ 20804:7848fc12602b

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Merge with jdk8u40-b25
author Gilles Duboscq <gilles.m.duboscq@oracle.com>
date Tue, 07 Apr 2015 14:58:49 +0200
parents 52b4284cb496 b20a35eae442
children
comparison
equal deleted inserted replaced
20184:84105dcdb05b 20804:7848fc12602b
121 121
122 fpop1_op3 = 0x34, 122 fpop1_op3 = 0x34,
123 fpop2_op3 = 0x35, 123 fpop2_op3 = 0x35,
124 impdep1_op3 = 0x36, 124 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36, 125 aes3_op3 = 0x36,
126 sha_op3 = 0x36,
126 alignaddr_op3 = 0x36, 127 alignaddr_op3 = 0x36,
127 faligndata_op3 = 0x36, 128 faligndata_op3 = 0x36,
128 flog3_op3 = 0x36, 129 flog3_op3 = 0x36,
129 edge_op3 = 0x36, 130 edge_op3 = 0x36,
130 fsrc_op3 = 0x36, 131 fsrc_op3 = 0x36,
221 mstosw_opf = 0x113, 222 mstosw_opf = 0x113,
222 mxtod_opf = 0x118, 223 mxtod_opf = 0x118,
223 mwtos_opf = 0x119, 224 mwtos_opf = 0x119,
224 225
225 aes_kexpand0_opf = 0x130, 226 aes_kexpand0_opf = 0x130,
226 aes_kexpand2_opf = 0x131 227 aes_kexpand2_opf = 0x131,
228
229 sha1_opf = 0x141,
230 sha256_opf = 0x142,
231 sha512_opf = 0x143
227 }; 232 };
228 233
229 enum op5s { 234 enum op5s {
230 aes_eround01_op5 = 0x00, 235 aes_eround01_op5 = 0x00,
231 aes_eround23_op5 = 0x01, 236 aes_eround23_op5 = 0x01,
592 return x & ((1 << 10) - 1); 597 return x & ((1 << 10) - 1);
593 } 598 }
594 599
595 // AES crypto instructions supported only on certain processors 600 // AES crypto instructions supported only on certain processors
596 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); } 601 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
602
603 // SHA crypto instructions supported only on certain processors
604 static void sha1_only() { assert( VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); }
605 static void sha256_only() { assert( VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
606 static void sha512_only() { assert( VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
597 607
598 // instruction only in VIS1 608 // instruction only in VIS1
599 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); } 609 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
600 610
601 // instruction only in VIS2 611 // instruction only in VIS2
1177 // wrasi(d, imm) stores (d xor imm) to asi 1187 // wrasi(d, imm) stores (d xor imm) to asi
1178 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | 1188 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
1179 u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); } 1189 u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
1180 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); } 1190 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1181 1191
1182
1183 // VIS1 instructions 1192 // VIS1 instructions
1184 1193
1185 void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); } 1194 void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
1186 1195
1187 void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); } 1196 void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
1200 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); } 1209 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1201 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); } 1210 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1202 1211
1203 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); } 1212 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1204 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); } 1213 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1214
1215 // Crypto SHA instructions
1216
1217 void sha1() { sha1_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
1218 void sha256() { sha256_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); }
1219 void sha512() { sha512_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); }
1205 1220
1206 // Creation 1221 // Creation
1207 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 1222 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1208 #ifdef CHECK_DELAY 1223 #ifdef CHECK_DELAY
1209 delay_state = no_delay; 1224 delay_state = no_delay;