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comparison src/cpu/sparc/vm/vm_version_sparc.cpp @ 20804:7848fc12602b

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Merge with jdk8u40-b25
author Gilles Duboscq <gilles.m.duboscq@oracle.com>
date Tue, 07 Apr 2015 14:58:49 +0200
parents 52b4284cb496 d635fd1ac81c
children
comparison
equal deleted inserted replaced
20184:84105dcdb05b 20804:7848fc12602b
35 # include "os_solaris.inline.hpp" 35 # include "os_solaris.inline.hpp"
36 #endif 36 #endif
37 37
38 int VM_Version::_features = VM_Version::unknown_m; 38 int VM_Version::_features = VM_Version::unknown_m;
39 const char* VM_Version::_features_str = ""; 39 const char* VM_Version::_features_str = "";
40 unsigned int VM_Version::_L2_cache_line_size = 0;
40 41
41 void VM_Version::initialize() { 42 void VM_Version::initialize() {
42 _features = determine_features(); 43 _features = determine_features();
43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); 44 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 45 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
195 warning("CBCOND instruction is not available on this CPU"); 196 warning("CBCOND instruction is not available on this CPU");
196 FLAG_SET_DEFAULT(UseCBCond, false); 197 FLAG_SET_DEFAULT(UseCBCond, false);
197 } 198 }
198 199
199 assert(BlockZeroingLowLimit > 0, "invalid value"); 200 assert(BlockZeroingLowLimit > 0, "invalid value");
200 if (has_block_zeroing()) { 201 if (has_block_zeroing() && cache_line_size > 0) {
201 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { 202 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
202 FLAG_SET_DEFAULT(UseBlockZeroing, true); 203 FLAG_SET_DEFAULT(UseBlockZeroing, true);
203 } 204 }
204 } else if (UseBlockZeroing) { 205 } else if (UseBlockZeroing) {
205 warning("BIS zeroing instructions are not available on this CPU"); 206 warning("BIS zeroing instructions are not available on this CPU");
206 FLAG_SET_DEFAULT(UseBlockZeroing, false); 207 FLAG_SET_DEFAULT(UseBlockZeroing, false);
207 } 208 }
208 209
209 assert(BlockCopyLowLimit > 0, "invalid value"); 210 assert(BlockCopyLowLimit > 0, "invalid value");
210 if (has_block_zeroing()) { // has_blk_init() && is_T4(): core's local L2 cache 211 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
211 if (FLAG_IS_DEFAULT(UseBlockCopy)) { 212 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
212 FLAG_SET_DEFAULT(UseBlockCopy, true); 213 FLAG_SET_DEFAULT(UseBlockCopy, true);
213 } 214 }
214 } else if (UseBlockCopy) { 215 } else if (UseBlockCopy) {
215 warning("BIS instructions are not available or expensive on this CPU"); 216 warning("BIS instructions are not available or expensive on this CPU");
232 233
233 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 234 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
234 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 235 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
235 236
236 char buf[512]; 237 char buf[512];
237 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 238 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
238 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), 239 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
239 (has_hardware_popc() ? ", popc" : ""), 240 (has_hardware_popc() ? ", popc" : ""),
240 (has_vis1() ? ", vis1" : ""), 241 (has_vis1() ? ", vis1" : ""),
241 (has_vis2() ? ", vis2" : ""), 242 (has_vis2() ? ", vis2" : ""),
242 (has_vis3() ? ", vis3" : ""), 243 (has_vis3() ? ", vis3" : ""),
243 (has_blk_init() ? ", blk_init" : ""), 244 (has_blk_init() ? ", blk_init" : ""),
244 (has_cbcond() ? ", cbcond" : ""), 245 (has_cbcond() ? ", cbcond" : ""),
245 (has_aes() ? ", aes" : ""), 246 (has_aes() ? ", aes" : ""),
247 (has_sha1() ? ", sha1" : ""),
248 (has_sha256() ? ", sha256" : ""),
249 (has_sha512() ? ", sha512" : ""),
246 (is_ultra3() ? ", ultra3" : ""), 250 (is_ultra3() ? ", ultra3" : ""),
247 (is_sun4v() ? ", sun4v" : ""), 251 (is_sun4v() ? ", sun4v" : ""),
248 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), 252 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
249 (is_sparc64() ? ", sparc64" : ""), 253 (is_sparc64() ? ", sparc64" : ""),
250 (!has_hardware_mul32() ? ", no-mul32" : ""), 254 (!has_hardware_mul32() ? ", no-mul32" : ""),
299 if (UseAESIntrinsics) { 303 if (UseAESIntrinsics) {
300 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 304 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
301 } 305 }
302 } 306 }
303 307
308 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
309 if (has_sha1() || has_sha256() || has_sha512()) {
310 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
311 if (FLAG_IS_DEFAULT(UseSHA)) {
312 FLAG_SET_DEFAULT(UseSHA, true);
313 }
314 } else {
315 if (UseSHA) {
316 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
317 FLAG_SET_DEFAULT(UseSHA, false);
318 }
319 }
320 } else if (UseSHA) {
321 warning("SHA instructions are not available on this CPU");
322 FLAG_SET_DEFAULT(UseSHA, false);
323 }
324
325 if (!UseSHA) {
326 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
327 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
328 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
329 } else {
330 if (has_sha1()) {
331 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
332 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
333 }
334 } else if (UseSHA1Intrinsics) {
335 warning("SHA1 instruction is not available on this CPU.");
336 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
337 }
338 if (has_sha256()) {
339 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
340 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
341 }
342 } else if (UseSHA256Intrinsics) {
343 warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU.");
344 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
345 }
346
347 if (has_sha512()) {
348 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
349 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
350 }
351 } else if (UseSHA512Intrinsics) {
352 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
353 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
354 }
355 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
356 FLAG_SET_DEFAULT(UseSHA, false);
357 }
358 }
359
304 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && 360 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
305 (cache_line_size > ContendedPaddingWidth)) 361 (cache_line_size > ContendedPaddingWidth))
306 ContendedPaddingWidth = cache_line_size; 362 ContendedPaddingWidth = cache_line_size;
307 363
308 #ifndef PRODUCT 364 #ifndef PRODUCT
309 if (PrintMiscellaneous && Verbose) { 365 if (PrintMiscellaneous && Verbose) {
366 tty->print_cr("L2 cache line size: %u", L2_cache_line_size());
310 tty->print("Allocation"); 367 tty->print("Allocation");
311 if (AllocatePrefetchStyle <= 0) { 368 if (AllocatePrefetchStyle <= 0) {
312 tty->print_cr(": no prefetching"); 369 tty->print_cr(": no prefetching");
313 } else { 370 } else {
314 tty->print(" prefetching: "); 371 tty->print(" prefetching: ");