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comparison src/cpu/ppc/vm/ppc.ad @ 14511:7e8e4d1a41d6

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8035970: PPC64: fix ad file after 8027754: Enable loop optimizations for loops with MathExact Reviewed-by: kvn
author goetz
date Thu, 27 Feb 2014 20:40:24 +0100
parents 0f19095fd8c1
children e5e8aa897002
comparison
equal deleted inserted replaced
14510:3df21373e577 14511:7e8e4d1a41d6
2358 2358
2359 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 2359 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2360 return RegMask(); 2360 return RegMask();
2361 } 2361 }
2362 2362
2363 const RegMask Matcher::mathExactI_result_proj_mask() {
2364 return RARG4_BITS64_REG_mask();
2365 }
2366
2367 const RegMask Matcher::mathExactL_result_proj_mask() {
2368 return RARG4_BITS64_REG_mask();
2369 }
2370
2371 const RegMask Matcher::mathExactI_flags_proj_mask() {
2372 return INT_FLAGS_mask();
2373 }
2374
2375 %} 2363 %}
2376 2364
2377 //----------ENCODING BLOCK----------------------------------------------------- 2365 //----------ENCODING BLOCK-----------------------------------------------------
2378 // This block specifies the encoding classes used by the compiler to output 2366 // This block specifies the encoding classes used by the compiler to output
2379 // byte streams. Encoding classes are parameterized macros used by 2367 // byte streams. Encoding classes are parameterized macros used by
7569 ins_pipe(pipe_class_default); 7557 ins_pipe(pipe_class_default);
7570 %} 7558 %}
7571 7559
7572 //----------Arithmetic Instructions-------------------------------------------- 7560 //----------Arithmetic Instructions--------------------------------------------
7573 // Addition Instructions 7561 // Addition Instructions
7574
7575 // PPC has no instruction setting overflow of 32-bit integer.
7576 //instruct addExactI_rReg(rarg4RegI dst, rRegI src, flagsReg cr) %{
7577 // match(AddExactI dst src);
7578 // effect(DEF cr);
7579 //
7580 // format %{ "ADD $dst, $dst, $src \t// addExact int, sets $cr" %}
7581 // ins_encode( enc_add(dst, dst, src) );
7582 // ins_pipe(pipe_class_default);
7583 //%}
7584 7562
7585 // Register Addition 7563 // Register Addition
7586 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{ 7564 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7587 match(Set dst (AddI src1 src2)); 7565 match(Set dst (AddI src1 src2));
7588 format %{ "ADD $dst, $src1, $src2" %} 7566 format %{ "ADD $dst, $src1, $src2" %}