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7201026: add vector for shift count Summary: Add generation of vectors for scalar shift count. Reviewed-by: roland, twisti, dlong
author kvn
date Tue, 02 Oct 2012 12:25:13 -0700
parents 7eca5de9e0b6
children b2c669fd8114
comparison
equal deleted inserted replaced
6822:f6b0eb4e44cf 6823:859c45fb8cea
567 case 16: return Op_VecX; 567 case 16: return Op_VecX;
568 case 32: return Op_VecY; 568 case 32: return Op_VecY;
569 } 569 }
570 ShouldNotReachHere(); 570 ShouldNotReachHere();
571 return 0; 571 return 0;
572 }
573
574 // Only lowest bits of xmm reg are used for vector shift count.
575 const int Matcher::vector_shift_count_ideal_reg(int size) {
576 return Op_VecS;
572 } 577 }
573 578
574 // x86 supports misaligned vectors store/load. 579 // x86 supports misaligned vectors store/load.
575 const bool Matcher::misaligned_vectors_ok() { 580 const bool Matcher::misaligned_vectors_ok() {
576 return !AlignVector; // can be changed by flag 581 return !AlignVector; // can be changed by flag
3756 __ vdivpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); 3761 __ vdivpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256);
3757 %} 3762 %}
3758 ins_pipe( pipe_slow ); 3763 ins_pipe( pipe_slow );
3759 %} 3764 %}
3760 3765
3766 // ------------------------------ Shift ---------------------------------------
3767
3768 // Left and right shift count vectors are the same on x86
3769 // (only lowest bits of xmm reg are used for count).
3770 instruct vshiftcnt(vecS dst, rRegI cnt) %{
3771 match(Set dst (LShiftCntV cnt));
3772 match(Set dst (RShiftCntV cnt));
3773 format %{ "movd $dst,$cnt\t! load shift count" %}
3774 ins_encode %{
3775 __ movdl($dst$$XMMRegister, $cnt$$Register);
3776 %}
3777 ins_pipe( pipe_slow );
3778 %}
3779
3761 // ------------------------------ LeftShift ----------------------------------- 3780 // ------------------------------ LeftShift -----------------------------------
3762 3781
3763 // Shorts/Chars vector left shift 3782 // Shorts/Chars vector left shift
3764 instruct vsll2S(vecS dst, regF shift) %{ 3783 instruct vsll2S(vecS dst, vecS shift) %{
3765 predicate(n->as_Vector()->length() == 2); 3784 predicate(n->as_Vector()->length() == 2);
3766 match(Set dst (LShiftVS dst shift)); 3785 match(Set dst (LShiftVS dst shift));
3767 format %{ "psllw $dst,$shift\t! left shift packed2S" %} 3786 format %{ "psllw $dst,$shift\t! left shift packed2S" %}
3768 ins_encode %{ 3787 ins_encode %{
3769 __ psllw($dst$$XMMRegister, $shift$$XMMRegister); 3788 __ psllw($dst$$XMMRegister, $shift$$XMMRegister);
3779 __ psllw($dst$$XMMRegister, (int)$shift$$constant); 3798 __ psllw($dst$$XMMRegister, (int)$shift$$constant);
3780 %} 3799 %}
3781 ins_pipe( pipe_slow ); 3800 ins_pipe( pipe_slow );
3782 %} 3801 %}
3783 3802
3784 instruct vsll2S_reg(vecS dst, vecS src, regF shift) %{ 3803 instruct vsll2S_reg(vecS dst, vecS src, vecS shift) %{
3785 predicate(UseAVX > 0 && n->as_Vector()->length() == 2); 3804 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3786 match(Set dst (LShiftVS src shift)); 3805 match(Set dst (LShiftVS src shift));
3787 format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %} 3806 format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %}
3788 ins_encode %{ 3807 ins_encode %{
3789 bool vector256 = false; 3808 bool vector256 = false;
3801 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); 3820 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3802 %} 3821 %}
3803 ins_pipe( pipe_slow ); 3822 ins_pipe( pipe_slow );
3804 %} 3823 %}
3805 3824
3806 instruct vsll4S(vecD dst, regF shift) %{ 3825 instruct vsll4S(vecD dst, vecS shift) %{
3807 predicate(n->as_Vector()->length() == 4); 3826 predicate(n->as_Vector()->length() == 4);
3808 match(Set dst (LShiftVS dst shift)); 3827 match(Set dst (LShiftVS dst shift));
3809 format %{ "psllw $dst,$shift\t! left shift packed4S" %} 3828 format %{ "psllw $dst,$shift\t! left shift packed4S" %}
3810 ins_encode %{ 3829 ins_encode %{
3811 __ psllw($dst$$XMMRegister, $shift$$XMMRegister); 3830 __ psllw($dst$$XMMRegister, $shift$$XMMRegister);
3821 __ psllw($dst$$XMMRegister, (int)$shift$$constant); 3840 __ psllw($dst$$XMMRegister, (int)$shift$$constant);
3822 %} 3841 %}
3823 ins_pipe( pipe_slow ); 3842 ins_pipe( pipe_slow );
3824 %} 3843 %}
3825 3844
3826 instruct vsll4S_reg(vecD dst, vecD src, regF shift) %{ 3845 instruct vsll4S_reg(vecD dst, vecD src, vecS shift) %{
3827 predicate(UseAVX > 0 && n->as_Vector()->length() == 4); 3846 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3828 match(Set dst (LShiftVS src shift)); 3847 match(Set dst (LShiftVS src shift));
3829 format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %} 3848 format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %}
3830 ins_encode %{ 3849 ins_encode %{
3831 bool vector256 = false; 3850 bool vector256 = false;
3843 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); 3862 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3844 %} 3863 %}
3845 ins_pipe( pipe_slow ); 3864 ins_pipe( pipe_slow );
3846 %} 3865 %}
3847 3866
3848 instruct vsll8S(vecX dst, regF shift) %{ 3867 instruct vsll8S(vecX dst, vecS shift) %{
3849 predicate(n->as_Vector()->length() == 8); 3868 predicate(n->as_Vector()->length() == 8);
3850 match(Set dst (LShiftVS dst shift)); 3869 match(Set dst (LShiftVS dst shift));
3851 format %{ "psllw $dst,$shift\t! left shift packed8S" %} 3870 format %{ "psllw $dst,$shift\t! left shift packed8S" %}
3852 ins_encode %{ 3871 ins_encode %{
3853 __ psllw($dst$$XMMRegister, $shift$$XMMRegister); 3872 __ psllw($dst$$XMMRegister, $shift$$XMMRegister);
3863 __ psllw($dst$$XMMRegister, (int)$shift$$constant); 3882 __ psllw($dst$$XMMRegister, (int)$shift$$constant);
3864 %} 3883 %}
3865 ins_pipe( pipe_slow ); 3884 ins_pipe( pipe_slow );
3866 %} 3885 %}
3867 3886
3868 instruct vsll8S_reg(vecX dst, vecX src, regF shift) %{ 3887 instruct vsll8S_reg(vecX dst, vecX src, vecS shift) %{
3869 predicate(UseAVX > 0 && n->as_Vector()->length() == 8); 3888 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
3870 match(Set dst (LShiftVS src shift)); 3889 match(Set dst (LShiftVS src shift));
3871 format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %} 3890 format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %}
3872 ins_encode %{ 3891 ins_encode %{
3873 bool vector256 = false; 3892 bool vector256 = false;
3885 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); 3904 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3886 %} 3905 %}
3887 ins_pipe( pipe_slow ); 3906 ins_pipe( pipe_slow );
3888 %} 3907 %}
3889 3908
3890 instruct vsll16S_reg(vecY dst, vecY src, regF shift) %{ 3909 instruct vsll16S_reg(vecY dst, vecY src, vecS shift) %{
3891 predicate(UseAVX > 1 && n->as_Vector()->length() == 16); 3910 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
3892 match(Set dst (LShiftVS src shift)); 3911 match(Set dst (LShiftVS src shift));
3893 format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %} 3912 format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %}
3894 ins_encode %{ 3913 ins_encode %{
3895 bool vector256 = true; 3914 bool vector256 = true;
3908 %} 3927 %}
3909 ins_pipe( pipe_slow ); 3928 ins_pipe( pipe_slow );
3910 %} 3929 %}
3911 3930
3912 // Integers vector left shift 3931 // Integers vector left shift
3913 instruct vsll2I(vecD dst, regF shift) %{ 3932 instruct vsll2I(vecD dst, vecS shift) %{
3914 predicate(n->as_Vector()->length() == 2); 3933 predicate(n->as_Vector()->length() == 2);
3915 match(Set dst (LShiftVI dst shift)); 3934 match(Set dst (LShiftVI dst shift));
3916 format %{ "pslld $dst,$shift\t! left shift packed2I" %} 3935 format %{ "pslld $dst,$shift\t! left shift packed2I" %}
3917 ins_encode %{ 3936 ins_encode %{
3918 __ pslld($dst$$XMMRegister, $shift$$XMMRegister); 3937 __ pslld($dst$$XMMRegister, $shift$$XMMRegister);
3928 __ pslld($dst$$XMMRegister, (int)$shift$$constant); 3947 __ pslld($dst$$XMMRegister, (int)$shift$$constant);
3929 %} 3948 %}
3930 ins_pipe( pipe_slow ); 3949 ins_pipe( pipe_slow );
3931 %} 3950 %}
3932 3951
3933 instruct vsll2I_reg(vecD dst, vecD src, regF shift) %{ 3952 instruct vsll2I_reg(vecD dst, vecD src, vecS shift) %{
3934 predicate(UseAVX > 0 && n->as_Vector()->length() == 2); 3953 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3935 match(Set dst (LShiftVI src shift)); 3954 match(Set dst (LShiftVI src shift));
3936 format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %} 3955 format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %}
3937 ins_encode %{ 3956 ins_encode %{
3938 bool vector256 = false; 3957 bool vector256 = false;
3950 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); 3969 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3951 %} 3970 %}
3952 ins_pipe( pipe_slow ); 3971 ins_pipe( pipe_slow );
3953 %} 3972 %}
3954 3973
3955 instruct vsll4I(vecX dst, regF shift) %{ 3974 instruct vsll4I(vecX dst, vecS shift) %{
3956 predicate(n->as_Vector()->length() == 4); 3975 predicate(n->as_Vector()->length() == 4);
3957 match(Set dst (LShiftVI dst shift)); 3976 match(Set dst (LShiftVI dst shift));
3958 format %{ "pslld $dst,$shift\t! left shift packed4I" %} 3977 format %{ "pslld $dst,$shift\t! left shift packed4I" %}
3959 ins_encode %{ 3978 ins_encode %{
3960 __ pslld($dst$$XMMRegister, $shift$$XMMRegister); 3979 __ pslld($dst$$XMMRegister, $shift$$XMMRegister);
3970 __ pslld($dst$$XMMRegister, (int)$shift$$constant); 3989 __ pslld($dst$$XMMRegister, (int)$shift$$constant);
3971 %} 3990 %}
3972 ins_pipe( pipe_slow ); 3991 ins_pipe( pipe_slow );
3973 %} 3992 %}
3974 3993
3975 instruct vsll4I_reg(vecX dst, vecX src, regF shift) %{ 3994 instruct vsll4I_reg(vecX dst, vecX src, vecS shift) %{
3976 predicate(UseAVX > 0 && n->as_Vector()->length() == 4); 3995 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3977 match(Set dst (LShiftVI src shift)); 3996 match(Set dst (LShiftVI src shift));
3978 format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %} 3997 format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %}
3979 ins_encode %{ 3998 ins_encode %{
3980 bool vector256 = false; 3999 bool vector256 = false;
3992 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); 4011 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3993 %} 4012 %}
3994 ins_pipe( pipe_slow ); 4013 ins_pipe( pipe_slow );
3995 %} 4014 %}
3996 4015
3997 instruct vsll8I_reg(vecY dst, vecY src, regF shift) %{ 4016 instruct vsll8I_reg(vecY dst, vecY src, vecS shift) %{
3998 predicate(UseAVX > 1 && n->as_Vector()->length() == 8); 4017 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
3999 match(Set dst (LShiftVI src shift)); 4018 match(Set dst (LShiftVI src shift));
4000 format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %} 4019 format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %}
4001 ins_encode %{ 4020 ins_encode %{
4002 bool vector256 = true; 4021 bool vector256 = true;
4015 %} 4034 %}
4016 ins_pipe( pipe_slow ); 4035 ins_pipe( pipe_slow );
4017 %} 4036 %}
4018 4037
4019 // Longs vector left shift 4038 // Longs vector left shift
4020 instruct vsll2L(vecX dst, regF shift) %{ 4039 instruct vsll2L(vecX dst, vecS shift) %{
4021 predicate(n->as_Vector()->length() == 2); 4040 predicate(n->as_Vector()->length() == 2);
4022 match(Set dst (LShiftVL dst shift)); 4041 match(Set dst (LShiftVL dst shift));
4023 format %{ "psllq $dst,$shift\t! left shift packed2L" %} 4042 format %{ "psllq $dst,$shift\t! left shift packed2L" %}
4024 ins_encode %{ 4043 ins_encode %{
4025 __ psllq($dst$$XMMRegister, $shift$$XMMRegister); 4044 __ psllq($dst$$XMMRegister, $shift$$XMMRegister);
4035 __ psllq($dst$$XMMRegister, (int)$shift$$constant); 4054 __ psllq($dst$$XMMRegister, (int)$shift$$constant);
4036 %} 4055 %}
4037 ins_pipe( pipe_slow ); 4056 ins_pipe( pipe_slow );
4038 %} 4057 %}
4039 4058
4040 instruct vsll2L_reg(vecX dst, vecX src, regF shift) %{ 4059 instruct vsll2L_reg(vecX dst, vecX src, vecS shift) %{
4041 predicate(UseAVX > 0 && n->as_Vector()->length() == 2); 4060 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4042 match(Set dst (LShiftVL src shift)); 4061 match(Set dst (LShiftVL src shift));
4043 format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %} 4062 format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %}
4044 ins_encode %{ 4063 ins_encode %{
4045 bool vector256 = false; 4064 bool vector256 = false;
4057 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); 4076 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4058 %} 4077 %}
4059 ins_pipe( pipe_slow ); 4078 ins_pipe( pipe_slow );
4060 %} 4079 %}
4061 4080
4062 instruct vsll4L_reg(vecY dst, vecY src, regF shift) %{ 4081 instruct vsll4L_reg(vecY dst, vecY src, vecS shift) %{
4063 predicate(UseAVX > 1 && n->as_Vector()->length() == 4); 4082 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4064 match(Set dst (LShiftVL src shift)); 4083 match(Set dst (LShiftVL src shift));
4065 format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %} 4084 format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %}
4066 ins_encode %{ 4085 ins_encode %{
4067 bool vector256 = true; 4086 bool vector256 = true;
4086 // Shorts/Chars vector logical right shift produces incorrect Java result 4105 // Shorts/Chars vector logical right shift produces incorrect Java result
4087 // for negative data because java code convert short value into int with 4106 // for negative data because java code convert short value into int with
4088 // sign extension before a shift. 4107 // sign extension before a shift.
4089 4108
4090 // Integers vector logical right shift 4109 // Integers vector logical right shift
4091 instruct vsrl2I(vecD dst, regF shift) %{ 4110 instruct vsrl2I(vecD dst, vecS shift) %{
4092 predicate(n->as_Vector()->length() == 2); 4111 predicate(n->as_Vector()->length() == 2);
4093 match(Set dst (URShiftVI dst shift)); 4112 match(Set dst (URShiftVI dst shift));
4094 format %{ "psrld $dst,$shift\t! logical right shift packed2I" %} 4113 format %{ "psrld $dst,$shift\t! logical right shift packed2I" %}
4095 ins_encode %{ 4114 ins_encode %{
4096 __ psrld($dst$$XMMRegister, $shift$$XMMRegister); 4115 __ psrld($dst$$XMMRegister, $shift$$XMMRegister);
4106 __ psrld($dst$$XMMRegister, (int)$shift$$constant); 4125 __ psrld($dst$$XMMRegister, (int)$shift$$constant);
4107 %} 4126 %}
4108 ins_pipe( pipe_slow ); 4127 ins_pipe( pipe_slow );
4109 %} 4128 %}
4110 4129
4111 instruct vsrl2I_reg(vecD dst, vecD src, regF shift) %{ 4130 instruct vsrl2I_reg(vecD dst, vecD src, vecS shift) %{
4112 predicate(UseAVX > 0 && n->as_Vector()->length() == 2); 4131 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4113 match(Set dst (URShiftVI src shift)); 4132 match(Set dst (URShiftVI src shift));
4114 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %} 4133 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %}
4115 ins_encode %{ 4134 ins_encode %{
4116 bool vector256 = false; 4135 bool vector256 = false;
4128 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); 4147 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4129 %} 4148 %}
4130 ins_pipe( pipe_slow ); 4149 ins_pipe( pipe_slow );
4131 %} 4150 %}
4132 4151
4133 instruct vsrl4I(vecX dst, regF shift) %{ 4152 instruct vsrl4I(vecX dst, vecS shift) %{
4134 predicate(n->as_Vector()->length() == 4); 4153 predicate(n->as_Vector()->length() == 4);
4135 match(Set dst (URShiftVI dst shift)); 4154 match(Set dst (URShiftVI dst shift));
4136 format %{ "psrld $dst,$shift\t! logical right shift packed4I" %} 4155 format %{ "psrld $dst,$shift\t! logical right shift packed4I" %}
4137 ins_encode %{ 4156 ins_encode %{
4138 __ psrld($dst$$XMMRegister, $shift$$XMMRegister); 4157 __ psrld($dst$$XMMRegister, $shift$$XMMRegister);
4148 __ psrld($dst$$XMMRegister, (int)$shift$$constant); 4167 __ psrld($dst$$XMMRegister, (int)$shift$$constant);
4149 %} 4168 %}
4150 ins_pipe( pipe_slow ); 4169 ins_pipe( pipe_slow );
4151 %} 4170 %}
4152 4171
4153 instruct vsrl4I_reg(vecX dst, vecX src, regF shift) %{ 4172 instruct vsrl4I_reg(vecX dst, vecX src, vecS shift) %{
4154 predicate(UseAVX > 0 && n->as_Vector()->length() == 4); 4173 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4155 match(Set dst (URShiftVI src shift)); 4174 match(Set dst (URShiftVI src shift));
4156 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %} 4175 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %}
4157 ins_encode %{ 4176 ins_encode %{
4158 bool vector256 = false; 4177 bool vector256 = false;
4170 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); 4189 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4171 %} 4190 %}
4172 ins_pipe( pipe_slow ); 4191 ins_pipe( pipe_slow );
4173 %} 4192 %}
4174 4193
4175 instruct vsrl8I_reg(vecY dst, vecY src, regF shift) %{ 4194 instruct vsrl8I_reg(vecY dst, vecY src, vecS shift) %{
4176 predicate(UseAVX > 1 && n->as_Vector()->length() == 8); 4195 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4177 match(Set dst (URShiftVI src shift)); 4196 match(Set dst (URShiftVI src shift));
4178 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %} 4197 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %}
4179 ins_encode %{ 4198 ins_encode %{
4180 bool vector256 = true; 4199 bool vector256 = true;
4193 %} 4212 %}
4194 ins_pipe( pipe_slow ); 4213 ins_pipe( pipe_slow );
4195 %} 4214 %}
4196 4215
4197 // Longs vector logical right shift 4216 // Longs vector logical right shift
4198 instruct vsrl2L(vecX dst, regF shift) %{ 4217 instruct vsrl2L(vecX dst, vecS shift) %{
4199 predicate(n->as_Vector()->length() == 2); 4218 predicate(n->as_Vector()->length() == 2);
4200 match(Set dst (URShiftVL dst shift)); 4219 match(Set dst (URShiftVL dst shift));
4201 format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %} 4220 format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %}
4202 ins_encode %{ 4221 ins_encode %{
4203 __ psrlq($dst$$XMMRegister, $shift$$XMMRegister); 4222 __ psrlq($dst$$XMMRegister, $shift$$XMMRegister);
4213 __ psrlq($dst$$XMMRegister, (int)$shift$$constant); 4232 __ psrlq($dst$$XMMRegister, (int)$shift$$constant);
4214 %} 4233 %}
4215 ins_pipe( pipe_slow ); 4234 ins_pipe( pipe_slow );
4216 %} 4235 %}
4217 4236
4218 instruct vsrl2L_reg(vecX dst, vecX src, regF shift) %{ 4237 instruct vsrl2L_reg(vecX dst, vecX src, vecS shift) %{
4219 predicate(UseAVX > 0 && n->as_Vector()->length() == 2); 4238 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4220 match(Set dst (URShiftVL src shift)); 4239 match(Set dst (URShiftVL src shift));
4221 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %} 4240 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %}
4222 ins_encode %{ 4241 ins_encode %{
4223 bool vector256 = false; 4242 bool vector256 = false;
4235 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); 4254 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4236 %} 4255 %}
4237 ins_pipe( pipe_slow ); 4256 ins_pipe( pipe_slow );
4238 %} 4257 %}
4239 4258
4240 instruct vsrl4L_reg(vecY dst, vecY src, regF shift) %{ 4259 instruct vsrl4L_reg(vecY dst, vecY src, vecS shift) %{
4241 predicate(UseAVX > 1 && n->as_Vector()->length() == 4); 4260 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4242 match(Set dst (URShiftVL src shift)); 4261 match(Set dst (URShiftVL src shift));
4243 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %} 4262 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %}
4244 ins_encode %{ 4263 ins_encode %{
4245 bool vector256 = true; 4264 bool vector256 = true;
4260 %} 4279 %}
4261 4280
4262 // ------------------- ArithmeticRightShift ----------------------------------- 4281 // ------------------- ArithmeticRightShift -----------------------------------
4263 4282
4264 // Shorts/Chars vector arithmetic right shift 4283 // Shorts/Chars vector arithmetic right shift
4265 instruct vsra2S(vecS dst, regF shift) %{ 4284 instruct vsra2S(vecS dst, vecS shift) %{
4266 predicate(n->as_Vector()->length() == 2); 4285 predicate(n->as_Vector()->length() == 2);
4267 match(Set dst (RShiftVS dst shift)); 4286 match(Set dst (RShiftVS dst shift));
4268 format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %} 4287 format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %}
4269 ins_encode %{ 4288 ins_encode %{
4270 __ psraw($dst$$XMMRegister, $shift$$XMMRegister); 4289 __ psraw($dst$$XMMRegister, $shift$$XMMRegister);
4280 __ psraw($dst$$XMMRegister, (int)$shift$$constant); 4299 __ psraw($dst$$XMMRegister, (int)$shift$$constant);
4281 %} 4300 %}
4282 ins_pipe( pipe_slow ); 4301 ins_pipe( pipe_slow );
4283 %} 4302 %}
4284 4303
4285 instruct vsra2S_reg(vecS dst, vecS src, regF shift) %{ 4304 instruct vsra2S_reg(vecS dst, vecS src, vecS shift) %{
4286 predicate(UseAVX > 0 && n->as_Vector()->length() == 2); 4305 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4287 match(Set dst (RShiftVS src shift)); 4306 match(Set dst (RShiftVS src shift));
4288 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %} 4307 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %}
4289 ins_encode %{ 4308 ins_encode %{
4290 bool vector256 = false; 4309 bool vector256 = false;
4302 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); 4321 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4303 %} 4322 %}
4304 ins_pipe( pipe_slow ); 4323 ins_pipe( pipe_slow );
4305 %} 4324 %}
4306 4325
4307 instruct vsra4S(vecD dst, regF shift) %{ 4326 instruct vsra4S(vecD dst, vecS shift) %{
4308 predicate(n->as_Vector()->length() == 4); 4327 predicate(n->as_Vector()->length() == 4);
4309 match(Set dst (RShiftVS dst shift)); 4328 match(Set dst (RShiftVS dst shift));
4310 format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %} 4329 format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %}
4311 ins_encode %{ 4330 ins_encode %{
4312 __ psraw($dst$$XMMRegister, $shift$$XMMRegister); 4331 __ psraw($dst$$XMMRegister, $shift$$XMMRegister);
4322 __ psraw($dst$$XMMRegister, (int)$shift$$constant); 4341 __ psraw($dst$$XMMRegister, (int)$shift$$constant);
4323 %} 4342 %}
4324 ins_pipe( pipe_slow ); 4343 ins_pipe( pipe_slow );
4325 %} 4344 %}
4326 4345
4327 instruct vsra4S_reg(vecD dst, vecD src, regF shift) %{ 4346 instruct vsra4S_reg(vecD dst, vecD src, vecS shift) %{
4328 predicate(UseAVX > 0 && n->as_Vector()->length() == 4); 4347 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4329 match(Set dst (RShiftVS src shift)); 4348 match(Set dst (RShiftVS src shift));
4330 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %} 4349 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %}
4331 ins_encode %{ 4350 ins_encode %{
4332 bool vector256 = false; 4351 bool vector256 = false;
4344 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); 4363 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4345 %} 4364 %}
4346 ins_pipe( pipe_slow ); 4365 ins_pipe( pipe_slow );
4347 %} 4366 %}
4348 4367
4349 instruct vsra8S(vecX dst, regF shift) %{ 4368 instruct vsra8S(vecX dst, vecS shift) %{
4350 predicate(n->as_Vector()->length() == 8); 4369 predicate(n->as_Vector()->length() == 8);
4351 match(Set dst (RShiftVS dst shift)); 4370 match(Set dst (RShiftVS dst shift));
4352 format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %} 4371 format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %}
4353 ins_encode %{ 4372 ins_encode %{
4354 __ psraw($dst$$XMMRegister, $shift$$XMMRegister); 4373 __ psraw($dst$$XMMRegister, $shift$$XMMRegister);
4364 __ psraw($dst$$XMMRegister, (int)$shift$$constant); 4383 __ psraw($dst$$XMMRegister, (int)$shift$$constant);
4365 %} 4384 %}
4366 ins_pipe( pipe_slow ); 4385 ins_pipe( pipe_slow );
4367 %} 4386 %}
4368 4387
4369 instruct vsra8S_reg(vecX dst, vecX src, regF shift) %{ 4388 instruct vsra8S_reg(vecX dst, vecX src, vecS shift) %{
4370 predicate(UseAVX > 0 && n->as_Vector()->length() == 8); 4389 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
4371 match(Set dst (RShiftVS src shift)); 4390 match(Set dst (RShiftVS src shift));
4372 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %} 4391 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %}
4373 ins_encode %{ 4392 ins_encode %{
4374 bool vector256 = false; 4393 bool vector256 = false;
4386 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); 4405 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4387 %} 4406 %}
4388 ins_pipe( pipe_slow ); 4407 ins_pipe( pipe_slow );
4389 %} 4408 %}
4390 4409
4391 instruct vsra16S_reg(vecY dst, vecY src, regF shift) %{ 4410 instruct vsra16S_reg(vecY dst, vecY src, vecS shift) %{
4392 predicate(UseAVX > 1 && n->as_Vector()->length() == 16); 4411 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
4393 match(Set dst (RShiftVS src shift)); 4412 match(Set dst (RShiftVS src shift));
4394 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %} 4413 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %}
4395 ins_encode %{ 4414 ins_encode %{
4396 bool vector256 = true; 4415 bool vector256 = true;
4409 %} 4428 %}
4410 ins_pipe( pipe_slow ); 4429 ins_pipe( pipe_slow );
4411 %} 4430 %}
4412 4431
4413 // Integers vector arithmetic right shift 4432 // Integers vector arithmetic right shift
4414 instruct vsra2I(vecD dst, regF shift) %{ 4433 instruct vsra2I(vecD dst, vecS shift) %{
4415 predicate(n->as_Vector()->length() == 2); 4434 predicate(n->as_Vector()->length() == 2);
4416 match(Set dst (RShiftVI dst shift)); 4435 match(Set dst (RShiftVI dst shift));
4417 format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %} 4436 format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %}
4418 ins_encode %{ 4437 ins_encode %{
4419 __ psrad($dst$$XMMRegister, $shift$$XMMRegister); 4438 __ psrad($dst$$XMMRegister, $shift$$XMMRegister);
4429 __ psrad($dst$$XMMRegister, (int)$shift$$constant); 4448 __ psrad($dst$$XMMRegister, (int)$shift$$constant);
4430 %} 4449 %}
4431 ins_pipe( pipe_slow ); 4450 ins_pipe( pipe_slow );
4432 %} 4451 %}
4433 4452
4434 instruct vsra2I_reg(vecD dst, vecD src, regF shift) %{ 4453 instruct vsra2I_reg(vecD dst, vecD src, vecS shift) %{
4435 predicate(UseAVX > 0 && n->as_Vector()->length() == 2); 4454 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4436 match(Set dst (RShiftVI src shift)); 4455 match(Set dst (RShiftVI src shift));
4437 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %} 4456 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %}
4438 ins_encode %{ 4457 ins_encode %{
4439 bool vector256 = false; 4458 bool vector256 = false;
4451 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); 4470 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4452 %} 4471 %}
4453 ins_pipe( pipe_slow ); 4472 ins_pipe( pipe_slow );
4454 %} 4473 %}
4455 4474
4456 instruct vsra4I(vecX dst, regF shift) %{ 4475 instruct vsra4I(vecX dst, vecS shift) %{
4457 predicate(n->as_Vector()->length() == 4); 4476 predicate(n->as_Vector()->length() == 4);
4458 match(Set dst (RShiftVI dst shift)); 4477 match(Set dst (RShiftVI dst shift));
4459 format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %} 4478 format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %}
4460 ins_encode %{ 4479 ins_encode %{
4461 __ psrad($dst$$XMMRegister, $shift$$XMMRegister); 4480 __ psrad($dst$$XMMRegister, $shift$$XMMRegister);
4471 __ psrad($dst$$XMMRegister, (int)$shift$$constant); 4490 __ psrad($dst$$XMMRegister, (int)$shift$$constant);
4472 %} 4491 %}
4473 ins_pipe( pipe_slow ); 4492 ins_pipe( pipe_slow );
4474 %} 4493 %}
4475 4494
4476 instruct vsra4I_reg(vecX dst, vecX src, regF shift) %{ 4495 instruct vsra4I_reg(vecX dst, vecX src, vecS shift) %{
4477 predicate(UseAVX > 0 && n->as_Vector()->length() == 4); 4496 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4478 match(Set dst (RShiftVI src shift)); 4497 match(Set dst (RShiftVI src shift));
4479 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %} 4498 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %}
4480 ins_encode %{ 4499 ins_encode %{
4481 bool vector256 = false; 4500 bool vector256 = false;
4493 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); 4512 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4494 %} 4513 %}
4495 ins_pipe( pipe_slow ); 4514 ins_pipe( pipe_slow );
4496 %} 4515 %}
4497 4516
4498 instruct vsra8I_reg(vecY dst, vecY src, regF shift) %{ 4517 instruct vsra8I_reg(vecY dst, vecY src, vecS shift) %{
4499 predicate(UseAVX > 1 && n->as_Vector()->length() == 8); 4518 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4500 match(Set dst (RShiftVI src shift)); 4519 match(Set dst (RShiftVI src shift));
4501 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %} 4520 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %}
4502 ins_encode %{ 4521 ins_encode %{
4503 bool vector256 = true; 4522 bool vector256 = true;