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comparison graal/com.oracle.max.asm.amd64/src/com/oracle/max/asm/amd64/X86InstructionDecoder.java @ 6493:85c1b84f8fd9

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moved ADM64-specific assembler code into separate project
author Doug Simon <doug.simon@oracle.com>
date Tue, 02 Oct 2012 22:22:06 +0200
parents graal/com.oracle.max.asm/src/com/oracle/max/asm/target/amd64/X86InstructionDecoder.java@2f2c6347fce4
children
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6492:dc409418cc2c 6493:85c1b84f8fd9
1 /*
2 * Copyright (c) 2009, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 */
23 package com.oracle.max.asm.amd64;
24
25
26 public final class X86InstructionDecoder {
27
28 private boolean targetIs64Bit;
29 private byte[] code;
30 private int currentEndOfInstruction;
31 private int currentDisplacementPosition;
32
33 private static class Prefix {
34
35 // segment overrides
36 public static final int CSSegment = 0x2e;
37 public static final int SSSegment = 0x36;
38 public static final int DSSegment = 0x3e;
39 public static final int ESSegment = 0x26;
40 public static final int FSSegment = 0x64;
41 public static final int GSSegment = 0x65;
42 public static final int REX = 0x40;
43 public static final int REXB = 0x41;
44 public static final int REXX = 0x42;
45 public static final int REXXB = 0x43;
46 public static final int REXR = 0x44;
47 public static final int REXRB = 0x45;
48 public static final int REXRX = 0x46;
49 public static final int REXRXB = 0x47;
50 public static final int REXW = 0x48;
51 public static final int REXWB = 0x49;
52 public static final int REXWX = 0x4A;
53 public static final int REXWXB = 0x4B;
54 public static final int REXWR = 0x4C;
55 public static final int REXWRB = 0x4D;
56 public static final int REXWRX = 0x4E;
57 public static final int REXWRXB = 0x4F;
58 }
59
60 private X86InstructionDecoder(byte[] code, boolean targetIs64Bit) {
61 this.code = code;
62 this.targetIs64Bit = targetIs64Bit;
63 }
64
65 public int currentEndOfInstruction() {
66 return currentEndOfInstruction;
67 }
68
69 public int currentDisplacementPosition() {
70 return currentDisplacementPosition;
71 }
72
73 public void decodePosition(int inst) {
74
75 assert inst >= 0 && inst < code.length;
76
77 // Decode the given instruction, and return the Pointer of
78 // an embedded 32-bit operand word.
79
80 // If "which" is WhichOperand.disp32operand, selects the displacement portion
81 // of an effective Pointer specifier.
82 // If "which" is imm64Operand, selects the trailing immediate constant.
83 // If "which" is WhichOperand.call32operand, selects the displacement of a call or jump.
84 // Caller is responsible for ensuring that there is such an operand,
85 // and that it is 32/64 bits wide.
86
87 // If "which" is endPcOperand, find the end of the instruction.
88
89 int ip = inst;
90 boolean is64bit = false;
91
92 boolean hasDisp32 = false;
93 int tailSize = 0; // other random bytes (#32, #16, etc.) at end of insn
94
95 boolean againAfterPrefix = true;
96
97 while (againAfterPrefix) {
98 againAfterPrefix = false;
99 switch (0xFF & code[ip++]) {
100
101 // These convenience macros generate groups of "case" labels for the switch.
102
103 case Prefix.CSSegment:
104 case Prefix.SSSegment:
105 case Prefix.DSSegment:
106 case Prefix.ESSegment:
107 case Prefix.FSSegment:
108 case Prefix.GSSegment:
109 // Seems dubious
110 assert !targetIs64Bit : "shouldn't have that prefix";
111 assert ip == inst + 1 : "only one prefix allowed";
112 againAfterPrefix = true;
113 break;
114
115 case 0x67:
116 case Prefix.REX:
117 case Prefix.REXB:
118 case Prefix.REXX:
119 case Prefix.REXXB:
120 case Prefix.REXR:
121 case Prefix.REXRB:
122 case Prefix.REXRX:
123 case Prefix.REXRXB:
124 assert targetIs64Bit : "64bit prefixes";
125 againAfterPrefix = true;
126 break;
127
128 case Prefix.REXW:
129 case Prefix.REXWB:
130 case Prefix.REXWX:
131 case Prefix.REXWXB:
132 case Prefix.REXWR:
133 case Prefix.REXWRB:
134 case Prefix.REXWRX:
135 case Prefix.REXWRXB:
136 assert targetIs64Bit : "64bit prefixes";
137 is64bit = true;
138 againAfterPrefix = true;
139 break;
140
141 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
142 case 0x88: // movb a, r
143 case 0x89: // movl a, r
144 case 0x8A: // movb r, a
145 case 0x8B: // movl r, a
146 case 0x8F: // popl a
147 hasDisp32 = true;
148 break;
149
150 case 0x68: // pushq #32
151 currentEndOfInstruction = ip + 4;
152 currentDisplacementPosition = ip;
153 return; // not produced by emitOperand
154
155 case 0x66: // movw ... (size prefix)
156 boolean againAfterSizePrefix2 = true;
157 while (againAfterSizePrefix2) {
158 againAfterSizePrefix2 = false;
159 switch (0xFF & code[ip++]) {
160 case Prefix.REX:
161 case Prefix.REXB:
162 case Prefix.REXX:
163 case Prefix.REXXB:
164 case Prefix.REXR:
165 case Prefix.REXRB:
166 case Prefix.REXRX:
167 case Prefix.REXRXB:
168 case Prefix.REXW:
169 case Prefix.REXWB:
170 case Prefix.REXWX:
171 case Prefix.REXWXB:
172 case Prefix.REXWR:
173 case Prefix.REXWRB:
174 case Prefix.REXWRX:
175 case Prefix.REXWRXB:
176 assert targetIs64Bit : "64bit prefix found";
177 againAfterSizePrefix2 = true;
178 break;
179 case 0x8B: // movw r, a
180 case 0x89: // movw a, r
181 hasDisp32 = true;
182 break;
183 case 0xC7: // movw a, #16
184 hasDisp32 = true;
185 tailSize = 2; // the imm16
186 break;
187 case 0x0F: // several SSE/SSE2 variants
188 ip--; // reparse the 0x0F
189 againAfterPrefix = true;
190 break;
191 default:
192 throw new InternalError("should not reach here");
193 }
194 }
195 break;
196
197 case 0xB8: // movl/q r, #32/#64(oop?)
198 case 0xB9:
199 case 0xBA:
200 case 0xBB:
201 case 0xBC:
202 case 0xBD:
203 case 0xBE:
204 case 0xBF:
205 currentEndOfInstruction = ip + (is64bit ? 8 : 4);
206 currentDisplacementPosition = ip;
207 return;
208
209 case 0x69: // imul r, a, #32
210 case 0xC7: // movl a, #32(oop?)
211 tailSize = 4;
212 hasDisp32 = true; // has both kinds of operands!
213 break;
214
215 case 0x0F: // movx..., etc.
216 switch (0xFF & code[ip++]) {
217 case 0x12: // movlps
218 case 0x28: // movaps
219 case 0x2E: // ucomiss
220 case 0x2F: // comiss
221 case 0x54: // andps
222 case 0x55: // andnps
223 case 0x56: // orps
224 case 0x57: // xorps
225 case 0x6E: // movd
226 case 0x7E: // movd
227 case 0xAE: // ldmxcsr a
228 // 64bit side says it these have both operands but that doesn't
229 // appear to be true
230 hasDisp32 = true;
231 break;
232
233 case 0xAD: // shrd r, a, %cl
234 case 0xAF: // imul r, a
235 case 0xBE: // movsbl r, a (movsxb)
236 case 0xBF: // movswl r, a (movsxw)
237 case 0xB6: // movzbl r, a (movzxb)
238 case 0xB7: // movzwl r, a (movzxw)
239 case 0x40: // cmovl cc, r, a
240 case 0x41:
241 case 0x42:
242 case 0x43:
243 case 0x44:
244 case 0x45:
245 case 0x46:
246 case 0x47:
247 case 0x48:
248 case 0x49:
249 case 0x4A:
250 case 0x4B:
251 case 0x4C:
252 case 0x4D:
253 case 0x4E:
254 case 0x4F:
255 case 0xB0: // cmpxchgb
256 case 0xB1: // cmpxchg
257 case 0xC1: // xaddl
258 case 0xC7: // cmpxchg8
259 case 0x90: // setcc a
260 case 0x91:
261 case 0x92:
262 case 0x93:
263 case 0x94:
264 case 0x95:
265 case 0x96:
266 case 0x97:
267 case 0x98:
268 case 0x99:
269 case 0x9A:
270 case 0x9B:
271 case 0x9C:
272 case 0x9D:
273 case 0x9E:
274 case 0x9F:
275 hasDisp32 = true;
276 // fall out of the switch to decode the Pointer
277 break;
278
279 case 0xAC: // shrd r, a, #8
280 hasDisp32 = true;
281 tailSize = 1; // the imm8
282 break;
283
284 case 0x80: // jcc rdisp32
285 case 0x81:
286 case 0x82:
287 case 0x83:
288 case 0x84:
289 case 0x85:
290 case 0x86:
291 case 0x87:
292 case 0x88:
293 case 0x89:
294 case 0x8A:
295 case 0x8B:
296 case 0x8C:
297 case 0x8D:
298 case 0x8E:
299 case 0x8F:
300 currentEndOfInstruction = ip + 4;
301 currentDisplacementPosition = ip;
302 return;
303 default:
304 throw new InternalError("should not reach here");
305 }
306 break;
307
308 case 0x81: // addl a, #32; addl r, #32
309 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
310 // on 32bit in the case of cmpl, the imm might be an oop
311 tailSize = 4;
312 hasDisp32 = true; // has both kinds of operands!
313 break;
314
315 case 0x83: // addl a, #8; addl r, #8
316 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
317 hasDisp32 = true; // has both kinds of operands!
318 tailSize = 1;
319 break;
320
321 case 0x9B:
322 switch (0xFF & code[ip++]) {
323 case 0xD9: // fnstcw a
324 hasDisp32 = true;
325 break;
326 default:
327 throw new InternalError("should not reach here");
328 }
329 break;
330
331 case 0x00: // addb a, r; addl a, r; addb r, a; addl r, a
332 case 0x01:
333 case 0x02:
334 case 0x03:
335 case 0x10: // adc...
336 case 0x11:
337 case 0x12:
338 case 0x13:
339 case 0x20: // and...
340 case 0x21:
341 case 0x22:
342 case 0x23:
343 case 0x30: // xor...
344 case 0x31:
345 case 0x32:
346 case 0x33:
347 case 0x08: // or...
348 case 0x09:
349 case 0x0a:
350 case 0x0b:
351 case 0x18: // sbb...
352 case 0x19:
353 case 0x1a:
354 case 0x1b:
355 case 0x28: // sub...
356 case 0x29:
357 case 0x2a:
358 case 0x2b:
359 case 0xF7: // mull a
360 case 0x8D: // lea r, a
361 case 0x87: // xchg r, a
362 case 0x38: // cmp...
363 case 0x39:
364 case 0x3a:
365 case 0x3b:
366 case 0x85: // test r, a
367 hasDisp32 = true; // has both kinds of operands!
368 break;
369
370 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
371 case 0xC6: // movb a, #8
372 case 0x80: // cmpb a, #8
373 case 0x6B: // imul r, a, #8
374 hasDisp32 = true; // has both kinds of operands!
375 tailSize = 1; // the imm8
376 break;
377
378 case 0xE8: // call rdisp32
379 case 0xE9: // jmp rdisp32
380 currentEndOfInstruction = ip + 4;
381 currentDisplacementPosition = ip;
382 return;
383
384 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
385 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
386 case 0xD9: // fldS a; fstS a; fstpS a; fldcw a
387 case 0xDD: // fldD a; fstD a; fstpD a
388 case 0xDB: // fildS a; fistpS a; fldX a; fstpX a
389 case 0xDF: // fildD a; fistpD a
390 case 0xD8: // faddS a; fsubrS a; fmulS a; fdivrS a; fcompS a
391 case 0xDC: // faddD a; fsubrD a; fmulD a; fdivrD a; fcompD a
392 case 0xDE: // faddpD a; fsubrpD a; fmulpD a; fdivrpD a; fcomppD a
393 hasDisp32 = true;
394 break;
395
396 case 0xF0: // Lock
397 againAfterPrefix = true;
398 break;
399
400 case 0xF3: // For SSE
401 case 0xF2: // For SSE2
402 switch (0xFF & code[ip++]) {
403 case Prefix.REX:
404 case Prefix.REXB:
405 case Prefix.REXX:
406 case Prefix.REXXB:
407 case Prefix.REXR:
408 case Prefix.REXRB:
409 case Prefix.REXRX:
410 case Prefix.REXRXB:
411 case Prefix.REXW:
412 case Prefix.REXWB:
413 case Prefix.REXWX:
414 case Prefix.REXWXB:
415 case Prefix.REXWR:
416 case Prefix.REXWRB:
417 case Prefix.REXWRX:
418 case Prefix.REXWRXB:
419 assert targetIs64Bit : "found 64bit prefix";
420 ip++;
421 // fall through
422 default:
423 ip++;
424 }
425 hasDisp32 = true; // has both kinds of operands!
426 break;
427
428 default:
429 throw new InternalError("should not reach here");
430 }
431 }
432
433 assert hasDisp32 : "(thomaswue) not sure if this holds: instruction has no disp32 field";
434
435 // parse the output of emitOperand
436 int op2 = 0xFF & code[ip++];
437 int base = op2 & 0x07;
438 int op3 = -1;
439 int b100 = 4;
440 int b101 = 5;
441 if (base == b100 && (op2 >> 6) != 3) {
442 op3 = 0xFF & code[ip++];
443 base = op3 & 0x07; // refetch the base
444 }
445 // now ip points at the disp (if any)
446
447 switch (op2 >> 6) {
448 case 0:
449 // [00 reg 100][ss index base]
450 // [00 reg 100][00 100 esp]
451 // [00 reg base]
452 // [00 reg 100][ss index 101][disp32]
453 // [00 reg 101] [disp32]
454
455 if (base == b101) {
456
457 currentDisplacementPosition = ip;
458 ip += 4; // skip the disp32
459 }
460 break;
461
462 case 1:
463 // [01 reg 100][ss index base][disp8]
464 // [01 reg 100][00 100 esp][disp8]
465 // [01 reg base] [disp8]
466 ip += 1; // skip the disp8
467 break;
468
469 case 2:
470 // [10 reg 100][ss index base][disp32]
471 // [10 reg 100][00 100 esp][disp32]
472 // [10 reg base] [disp32]
473 currentDisplacementPosition = ip;
474 ip += 4; // skip the disp32
475 break;
476
477 case 3:
478 // [11 reg base] (not a memory addressing mode)
479 break;
480 }
481
482 currentEndOfInstruction = ip + tailSize;
483 }
484
485 public static void patchRelativeInstruction(byte[] code, int codePos, int relative) {
486 X86InstructionDecoder decoder = new X86InstructionDecoder(code, true);
487 decoder.decodePosition(codePos);
488 int patchPos = decoder.currentDisplacementPosition();
489 int endOfInstruction = decoder.currentEndOfInstruction();
490 int offset = relative - endOfInstruction + codePos;
491 patchDisp32(code, patchPos, offset);
492 }
493
494 private static void patchDisp32(byte[] code, int pos, int offset) {
495 assert pos + 4 <= code.length;
496
497 assert code[pos] == 0;
498 assert code[pos + 1] == 0;
499 assert code[pos + 2] == 0;
500 assert code[pos + 3] == 0;
501
502 code[pos] = (byte) (offset & 0xFF);
503 code[pos + 1] = (byte) ((offset >> 8) & 0xFF);
504 code[pos + 2] = (byte) ((offset >> 16) & 0xFF);
505 code[pos + 3] = (byte) ((offset >> 24) & 0xFF);
506 }
507 }