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Merge with jdk8-b132
author Gilles Duboscq <duboscq@ssw.jku.at>
date Wed, 15 Oct 2014 11:59:32 +0200
parents 4ca6dc0799b6 984401824c5e
children 52b4284cb496
comparison
equal deleted inserted replaced
17450:45b45f902bed 17524:89152779163c
755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
756 } 756 }
757 #endif 757 #endif
758 758
759 759
760 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, 760 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
761 int src1_enc, int disp32, int src2_enc, int dst_enc) { 761 int src1_enc, int disp32, int src2_enc, int dst_enc) {
762 762
763 #ifdef ASSERT 763 #ifdef ASSERT
764 // The following code implements the +VerifyOops feature. 764 // The following code implements the +VerifyOops feature.
765 // It verifies oop values which are loaded into or stored out of 765 // It verifies oop values which are loaded into or stored out of
910 | (src1_enc << 14); 910 | (src1_enc << 14);
911 911
912 uint index = src2_enc; 912 uint index = src2_enc;
913 int disp = disp32; 913 int disp = disp32;
914 914
915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) 915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
916 disp += STACK_BIAS; 916 disp += STACK_BIAS;
917 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
918 if (!Assembler::is_simm13(disp)) {
919 ra->C->record_method_not_compilable("unable to handle large constant offsets");
920 return;
921 }
922 }
917 923
918 // We should have a compiler bailout here rather than a guarantee. 924 // We should have a compiler bailout here rather than a guarantee.
919 // Better yet would be some mechanism to handle variable-size matches correctly. 925 // Better yet would be some mechanism to handle variable-size matches correctly.
920 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); 926 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
921 927
1277 if (r->is_Register()) return rc_int; 1283 if (r->is_Register()) return rc_int;
1278 assert(r->is_FloatRegister(), "must be"); 1284 assert(r->is_FloatRegister(), "must be");
1279 return rc_float; 1285 return rc_float;
1280 } 1286 }
1281 1287
1282 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { 1288 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1283 if( cbuf ) { 1289 if (cbuf) {
1284 // Better yet would be some mechanism to handle variable-size matches correctly 1290 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1285 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1286 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1287 } else {
1288 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1289 }
1290 } 1291 }
1291 #ifndef PRODUCT 1292 #ifndef PRODUCT
1292 else if( !do_size ) { 1293 else if (!do_size) {
1293 if( size != 0 ) st->print("\n\t"); 1294 if (size != 0) st->print("\n\t");
1294 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); 1295 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1295 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); 1296 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1296 } 1297 }
1297 #endif 1298 #endif
1298 return size+4; 1299 return size+4;
1299 } 1300 }
1300 1301
2085 __ untested("encoding"); 2086 __ untested("encoding");
2086 #endif 2087 #endif
2087 %} 2088 %}
2088 2089
2089 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 2090 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2090 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, 2091 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2091 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2092 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2092 %} 2093 %}
2093 2094
2094 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 2095 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2095 emit_form3_mem_reg(cbuf, this, $primary, -1, 2096 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2096 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2097 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2097 %} 2098 %}
2098 2099
2099 enc_class form3_mem_prefetch_read( memory mem ) %{ 2100 enc_class form3_mem_prefetch_read( memory mem ) %{
2100 emit_form3_mem_reg(cbuf, this, $primary, -1, 2101 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2101 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 2102 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2102 %} 2103 %}
2103 2104
2104 enc_class form3_mem_prefetch_write( memory mem ) %{ 2105 enc_class form3_mem_prefetch_write( memory mem ) %{
2105 emit_form3_mem_reg(cbuf, this, $primary, -1, 2106 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2106 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 2107 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2107 %} 2108 %}
2108 2109
2109 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 2110 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2110 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2111 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2111 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2112 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2112 guarantee($mem$$index == R_G0_enc, "double index?"); 2113 guarantee($mem$$index == R_G0_enc, "double index?");
2113 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 2114 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2114 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 2115 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2115 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 2116 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2116 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 2117 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2117 %} 2118 %}
2118 2119
2119 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 2120 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2120 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2121 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2121 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2122 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2122 guarantee($mem$$index == R_G0_enc, "double index?"); 2123 guarantee($mem$$index == R_G0_enc, "double index?");
2123 // Load long with 2 instructions 2124 // Load long with 2 instructions
2124 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 2125 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2125 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 2126 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2126 %} 2127 %}
2127 2128
2128 //%%% form3_mem_plus_4_reg is a hack--get rid of it 2129 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2129 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 2130 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2130 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 2131 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2131 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 2132 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2132 %} 2133 %}
2133 2134
2134 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 2135 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2135 // Encode a reg-reg copy. If it is useless, then empty encoding. 2136 // Encode a reg-reg copy. If it is useless, then empty encoding.
2136 if( $rs2$$reg != $rd$$reg ) 2137 if( $rs2$$reg != $rd$$reg )
3352 op_cost(0); 3353 op_cost(0);
3353 format %{ %} 3354 format %{ %}
3354 interface(CONST_INTER); 3355 interface(CONST_INTER);
3355 %} 3356 %}
3356 3357
3357 // Unsigned (positive) Integer Immediate: 13-bit 3358 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3358 operand immU13() %{ 3359 operand immU12() %{
3359 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3360 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3360 match(ConI); 3361 match(ConI);
3361 op_cost(0); 3362 op_cost(0);
3362 3363
3363 format %{ %} 3364 format %{ %}
3384 3385
3385 // Integer Immediate: 5-bit 3386 // Integer Immediate: 5-bit
3386 operand immI5() %{ 3387 operand immI5() %{
3387 predicate(Assembler::is_simm5(n->get_int())); 3388 predicate(Assembler::is_simm5(n->get_int()));
3388 match(ConI); 3389 match(ConI);
3390 op_cost(0);
3391 format %{ %}
3392 interface(CONST_INTER);
3393 %}
3394
3395 // Int Immediate non-negative
3396 operand immU31()
3397 %{
3398 predicate(n->get_int() >= 0);
3399 match(ConI);
3400
3389 op_cost(0); 3401 op_cost(0);
3390 format %{ %} 3402 format %{ %}
3391 interface(CONST_INTER); 3403 interface(CONST_INTER);
3392 %} 3404 %}
3393 3405
5717 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ 5729 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5718 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5730 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5719 effect(TEMP dst, TEMP tmp); 5731 effect(TEMP dst, TEMP tmp);
5720 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5732 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5721 5733
5722 size((3+1)*4); // set may use two instructions.
5723 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" 5734 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5724 "SET $mask,$tmp\n\t" 5735 "SET $mask,$tmp\n\t"
5725 "AND $dst,$tmp,$dst" %} 5736 "AND $dst,$tmp,$dst" %}
5726 ins_encode %{ 5737 ins_encode %{
5727 Register Rdst = $dst$$Register; 5738 Register Rdst = $dst$$Register;
5839 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5850 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5840 %} 5851 %}
5841 ins_pipe(iload_mem); 5852 ins_pipe(iload_mem);
5842 %} 5853 %}
5843 5854
5844 // Load Integer with a 13-bit mask into a Long Register 5855 // Load Integer with a 12-bit mask into a Long Register
5845 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5856 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5846 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5857 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5847 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5858 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5848 5859
5849 size(2*4); 5860 size(2*4);
5850 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" 5861 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5851 "AND $dst,$mask,$dst" %} 5862 "AND $dst,$mask,$dst" %}
5852 ins_encode %{ 5863 ins_encode %{
5853 Register Rdst = $dst$$Register; 5864 Register Rdst = $dst$$Register;
5854 __ lduw($mem$$Address, Rdst); 5865 __ lduw($mem$$Address, Rdst);
5855 __ and3(Rdst, $mask$$constant, Rdst); 5866 __ and3(Rdst, $mask$$constant, Rdst);
5856 %} 5867 %}
5857 ins_pipe(iload_mem); 5868 ins_pipe(iload_mem);
5858 %} 5869 %}
5859 5870
5860 // Load Integer with a 32-bit mask into a Long Register 5871 // Load Integer with a 31-bit mask into a Long Register
5861 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5872 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5862 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5873 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5863 effect(TEMP dst, TEMP tmp); 5874 effect(TEMP dst, TEMP tmp);
5864 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5875 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5865 5876
5866 size((3+1)*4); // set may use two instructions. 5877 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5867 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5868 "SET $mask,$tmp\n\t" 5878 "SET $mask,$tmp\n\t"
5869 "AND $dst,$tmp,$dst" %} 5879 "AND $dst,$tmp,$dst" %}
5870 ins_encode %{ 5880 ins_encode %{
5871 Register Rdst = $dst$$Register; 5881 Register Rdst = $dst$$Register;
5872 Register Rtmp = $tmp$$Register; 5882 Register Rtmp = $tmp$$Register;
8957 opcode(Assembler::andcc_op3, Assembler::arith_op); 8967 opcode(Assembler::andcc_op3, Assembler::arith_op);
8958 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8968 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8959 ins_pipe(ialu_cconly_reg_reg); 8969 ins_pipe(ialu_cconly_reg_reg);
8960 %} 8970 %}
8961 8971
8962 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ 8972 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8963 match(Set icc (CmpU op1 op2)); 8973 match(Set icc (CmpU op1 op2));
8964 8974
8965 size(4); 8975 size(4);
8966 format %{ "CMP $op1,$op2\t! unsigned" %} 8976 format %{ "CMP $op1,$op2\t! unsigned" %}
8967 opcode(Assembler::subcc_op3, Assembler::arith_op); 8977 opcode(Assembler::subcc_op3, Assembler::arith_op);