Mercurial > hg > truffle
comparison src/cpu/x86/vm/assembler_x86.cpp @ 4768:8940fd98d540
Merge
author | kvn |
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date | Thu, 29 Dec 2011 11:37:50 -0800 |
parents | 96ce4c27112f 40c2484c09e1 |
children | 1cb50d7a9d95 |
comparison
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4730:7faca6dfa2ed | 4768:8940fd98d540 |
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531 debug_only(has_disp32 = true); // has both kinds of operands! | 531 debug_only(has_disp32 = true); // has both kinds of operands! |
532 break; | 532 break; |
533 | 533 |
534 case 0x0F: // movx..., etc. | 534 case 0x0F: // movx..., etc. |
535 switch (0xFF & *ip++) { | 535 switch (0xFF & *ip++) { |
536 case 0x3A: // pcmpestri | |
537 tail_size = 1; | |
538 case 0x38: // ptest, pmovzxbw | |
539 ip++; // skip opcode | |
540 debug_only(has_disp32 = true); // has both kinds of operands! | |
541 break; | |
542 | |
543 case 0x70: // pshufd r, r/a, #8 | |
544 debug_only(has_disp32 = true); // has both kinds of operands! | |
545 case 0x73: // psrldq r, #8 | |
546 tail_size = 1; | |
547 break; | |
548 | |
536 case 0x12: // movlps | 549 case 0x12: // movlps |
537 case 0x28: // movaps | 550 case 0x28: // movaps |
538 case 0x2E: // ucomiss | 551 case 0x2E: // ucomiss |
539 case 0x2F: // comiss | 552 case 0x2F: // comiss |
540 case 0x54: // andps | 553 case 0x54: // andps |
541 case 0x55: // andnps | 554 case 0x55: // andnps |
542 case 0x56: // orps | 555 case 0x56: // orps |
543 case 0x57: // xorps | 556 case 0x57: // xorps |
544 case 0x6E: // movd | 557 case 0x6E: // movd |
545 case 0x7E: // movd | 558 case 0x7E: // movd |
546 case 0xAE: // ldmxcsr a | 559 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush |
547 // 64bit side says it these have both operands but that doesn't | |
548 // appear to be true | |
549 debug_only(has_disp32 = true); | 560 debug_only(has_disp32 = true); |
550 break; | 561 break; |
551 | 562 |
552 case 0xAD: // shrd r, a, %cl | 563 case 0xAD: // shrd r, a, %cl |
553 case 0xAF: // imul r, a | 564 case 0xAF: // imul r, a |
563 case REP16(0x90): // setcc a | 574 case REP16(0x90): // setcc a |
564 debug_only(has_disp32 = true); | 575 debug_only(has_disp32 = true); |
565 // fall out of the switch to decode the address | 576 // fall out of the switch to decode the address |
566 break; | 577 break; |
567 | 578 |
579 case 0xC4: // pinsrw r, a, #8 | |
580 debug_only(has_disp32 = true); | |
581 case 0xC5: // pextrw r, r, #8 | |
582 tail_size = 1; // the imm8 | |
583 break; | |
584 | |
568 case 0xAC: // shrd r, a, #8 | 585 case 0xAC: // shrd r, a, #8 |
569 debug_only(has_disp32 = true); | 586 debug_only(has_disp32 = true); |
570 tail_size = 1; // the imm8 | 587 tail_size = 1; // the imm8 |
571 break; | 588 break; |
572 | 589 |
623 case 0x6B: // imul r, a, #8 | 640 case 0x6B: // imul r, a, #8 |
624 debug_only(has_disp32 = true); // has both kinds of operands! | 641 debug_only(has_disp32 = true); // has both kinds of operands! |
625 tail_size = 1; // the imm8 | 642 tail_size = 1; // the imm8 |
626 break; | 643 break; |
627 | 644 |
628 case 0xE8: // call rdisp32 | 645 case 0xC4: // VEX_3bytes |
629 case 0xE9: // jmp rdisp32 | 646 case 0xC5: // VEX_2bytes |
630 if (which == end_pc_operand) return ip + 4; | 647 assert((UseAVX > 0), "shouldn't have VEX prefix"); |
631 assert(which == call32_operand, "call has no disp32 or imm"); | 648 assert(ip == inst+1, "no prefixes allowed"); |
632 return ip; | 649 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions |
650 // but they have prefix 0x0F and processed when 0x0F processed above. | |
651 // | |
652 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES | |
653 // instructions (these instructions are not supported in 64-bit mode). | |
654 // To distinguish them bits [7:6] are set in the VEX second byte since | |
655 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set | |
656 // those VEX bits REX and vvvv bits are inverted. | |
657 // | |
658 // Fortunately C2 doesn't generate these instructions so we don't need | |
659 // to check for them in product version. | |
660 | |
661 // Check second byte | |
662 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); | |
663 | |
664 // First byte | |
665 if ((0xFF & *inst) == VEX_3bytes) { | |
666 ip++; // third byte | |
667 is_64bit = ((VEX_W & *ip) == VEX_W); | |
668 } | |
669 ip++; // opcode | |
670 // To find the end of instruction (which == end_pc_operand). | |
671 switch (0xFF & *ip) { | |
672 case 0x61: // pcmpestri r, r/a, #8 | |
673 case 0x70: // pshufd r, r/a, #8 | |
674 case 0x73: // psrldq r, #8 | |
675 tail_size = 1; // the imm8 | |
676 break; | |
677 default: | |
678 break; | |
679 } | |
680 ip++; // skip opcode | |
681 debug_only(has_disp32 = true); // has both kinds of operands! | |
682 break; | |
633 | 683 |
634 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | 684 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 |
635 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | 685 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl |
636 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | 686 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a |
637 case 0xDD: // fld_d a; fst_d a; fstp_d a | 687 case 0xDD: // fld_d a; fst_d a; fstp_d a |
640 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | 690 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a |
641 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | 691 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a |
642 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | 692 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a |
643 debug_only(has_disp32 = true); | 693 debug_only(has_disp32 = true); |
644 break; | 694 break; |
695 | |
696 case 0xE8: // call rdisp32 | |
697 case 0xE9: // jmp rdisp32 | |
698 if (which == end_pc_operand) return ip + 4; | |
699 assert(which == call32_operand, "call has no disp32 or imm"); | |
700 return ip; | |
645 | 701 |
646 case 0xF0: // Lock | 702 case 0xF0: // Lock |
647 assert(os::is_MP(), "only on MP"); | 703 assert(os::is_MP(), "only on MP"); |
648 goto again_after_prefix; | 704 goto again_after_prefix; |
649 | 705 |
916 emit_long(0); // 32-bits offset (4 bytes) | 972 emit_long(0); // 32-bits offset (4 bytes) |
917 } | 973 } |
918 | 974 |
919 void Assembler::addsd(XMMRegister dst, XMMRegister src) { | 975 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
920 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 976 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
921 emit_byte(0xF2); | 977 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
922 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
923 emit_byte(0x0F); | |
924 emit_byte(0x58); | 978 emit_byte(0x58); |
925 emit_byte(0xC0 | encode); | 979 emit_byte(0xC0 | encode); |
926 } | 980 } |
927 | 981 |
928 void Assembler::addsd(XMMRegister dst, Address src) { | 982 void Assembler::addsd(XMMRegister dst, Address src) { |
929 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 983 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
930 InstructionMark im(this); | 984 InstructionMark im(this); |
931 emit_byte(0xF2); | 985 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
932 prefix(src, dst); | |
933 emit_byte(0x0F); | |
934 emit_byte(0x58); | 986 emit_byte(0x58); |
935 emit_operand(dst, src); | 987 emit_operand(dst, src); |
936 } | 988 } |
937 | 989 |
938 void Assembler::addss(XMMRegister dst, XMMRegister src) { | 990 void Assembler::addss(XMMRegister dst, XMMRegister src) { |
939 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 991 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
940 emit_byte(0xF3); | 992 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
941 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
942 emit_byte(0x0F); | |
943 emit_byte(0x58); | 993 emit_byte(0x58); |
944 emit_byte(0xC0 | encode); | 994 emit_byte(0xC0 | encode); |
945 } | 995 } |
946 | 996 |
947 void Assembler::addss(XMMRegister dst, Address src) { | 997 void Assembler::addss(XMMRegister dst, Address src) { |
948 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 998 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
949 InstructionMark im(this); | 999 InstructionMark im(this); |
950 emit_byte(0xF3); | 1000 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
951 prefix(src, dst); | |
952 emit_byte(0x0F); | |
953 emit_byte(0x58); | 1001 emit_byte(0x58); |
954 emit_operand(dst, src); | 1002 emit_operand(dst, src); |
1003 } | |
1004 | |
1005 void Assembler::andl(Address dst, int32_t imm32) { | |
1006 InstructionMark im(this); | |
1007 prefix(dst); | |
1008 emit_byte(0x81); | |
1009 emit_operand(rsp, dst, 4); | |
1010 emit_long(imm32); | |
955 } | 1011 } |
956 | 1012 |
957 void Assembler::andl(Register dst, int32_t imm32) { | 1013 void Assembler::andl(Register dst, int32_t imm32) { |
958 prefix(dst); | 1014 prefix(dst); |
959 emit_arith(0x81, 0xE0, dst, imm32); | 1015 emit_arith(0x81, 0xE0, dst, imm32); |
972 } | 1028 } |
973 | 1029 |
974 void Assembler::andpd(XMMRegister dst, Address src) { | 1030 void Assembler::andpd(XMMRegister dst, Address src) { |
975 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1031 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
976 InstructionMark im(this); | 1032 InstructionMark im(this); |
977 emit_byte(0x66); | 1033 simd_prefix(dst, dst, src, VEX_SIMD_66); |
978 prefix(src, dst); | |
979 emit_byte(0x0F); | |
980 emit_byte(0x54); | 1034 emit_byte(0x54); |
981 emit_operand(dst, src); | 1035 emit_operand(dst, src); |
1036 } | |
1037 | |
1038 void Assembler::andpd(XMMRegister dst, XMMRegister src) { | |
1039 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1040 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | |
1041 emit_byte(0x54); | |
1042 emit_byte(0xC0 | encode); | |
1043 } | |
1044 | |
1045 void Assembler::andps(XMMRegister dst, Address src) { | |
1046 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1047 InstructionMark im(this); | |
1048 simd_prefix(dst, dst, src, VEX_SIMD_NONE); | |
1049 emit_byte(0x54); | |
1050 emit_operand(dst, src); | |
1051 } | |
1052 | |
1053 void Assembler::andps(XMMRegister dst, XMMRegister src) { | |
1054 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1055 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE); | |
1056 emit_byte(0x54); | |
1057 emit_byte(0xC0 | encode); | |
982 } | 1058 } |
983 | 1059 |
984 void Assembler::bsfl(Register dst, Register src) { | 1060 void Assembler::bsfl(Register dst, Register src) { |
985 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 1061 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
986 emit_byte(0x0F); | 1062 emit_byte(0x0F); |
1023 emit_data(int(0), rtype, operand); | 1099 emit_data(int(0), rtype, operand); |
1024 } | 1100 } |
1025 } | 1101 } |
1026 | 1102 |
1027 void Assembler::call(Register dst) { | 1103 void Assembler::call(Register dst) { |
1028 // This was originally using a 32bit register encoding | 1104 int encode = prefix_and_encode(dst->encoding()); |
1029 // and surely we want 64bit! | |
1030 // this is a 32bit encoding but in 64bit mode the default | |
1031 // operand size is 64bit so there is no need for the | |
1032 // wide prefix. So prefix only happens if we use the | |
1033 // new registers. Much like push/pop. | |
1034 int x = offset(); | |
1035 // this may be true but dbx disassembles it as if it | |
1036 // were 32bits... | |
1037 // int encode = prefix_and_encode(dst->encoding()); | |
1038 // if (offset() != x) assert(dst->encoding() >= 8, "what?"); | |
1039 int encode = prefixq_and_encode(dst->encoding()); | |
1040 | |
1041 emit_byte(0xFF); | 1105 emit_byte(0xFF); |
1042 emit_byte(0xD0 | encode); | 1106 emit_byte(0xD0 | encode); |
1043 } | 1107 } |
1044 | 1108 |
1045 | 1109 |
1155 | 1219 |
1156 void Assembler::comisd(XMMRegister dst, Address src) { | 1220 void Assembler::comisd(XMMRegister dst, Address src) { |
1157 // NOTE: dbx seems to decode this as comiss even though the | 1221 // NOTE: dbx seems to decode this as comiss even though the |
1158 // 0x66 is there. Strangly ucomisd comes out correct | 1222 // 0x66 is there. Strangly ucomisd comes out correct |
1159 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1223 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1160 emit_byte(0x66); | 1224 InstructionMark im(this); |
1161 comiss(dst, src); | 1225 simd_prefix(dst, src, VEX_SIMD_66); |
1226 emit_byte(0x2F); | |
1227 emit_operand(dst, src); | |
1228 } | |
1229 | |
1230 void Assembler::comisd(XMMRegister dst, XMMRegister src) { | |
1231 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1232 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); | |
1233 emit_byte(0x2F); | |
1234 emit_byte(0xC0 | encode); | |
1162 } | 1235 } |
1163 | 1236 |
1164 void Assembler::comiss(XMMRegister dst, Address src) { | 1237 void Assembler::comiss(XMMRegister dst, Address src) { |
1165 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1238 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1166 | 1239 InstructionMark im(this); |
1167 InstructionMark im(this); | 1240 simd_prefix(dst, src, VEX_SIMD_NONE); |
1168 prefix(src, dst); | |
1169 emit_byte(0x0F); | |
1170 emit_byte(0x2F); | 1241 emit_byte(0x2F); |
1171 emit_operand(dst, src); | 1242 emit_operand(dst, src); |
1172 } | 1243 } |
1173 | 1244 |
1245 void Assembler::comiss(XMMRegister dst, XMMRegister src) { | |
1246 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1247 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); | |
1248 emit_byte(0x2F); | |
1249 emit_byte(0xC0 | encode); | |
1250 } | |
1251 | |
1174 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { | 1252 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { |
1175 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1253 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1176 emit_byte(0xF3); | 1254 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
1177 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1178 emit_byte(0x0F); | |
1179 emit_byte(0xE6); | 1255 emit_byte(0xE6); |
1180 emit_byte(0xC0 | encode); | 1256 emit_byte(0xC0 | encode); |
1181 } | 1257 } |
1182 | 1258 |
1183 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | 1259 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { |
1184 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1260 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1185 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 1261 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
1186 emit_byte(0x0F); | |
1187 emit_byte(0x5B); | 1262 emit_byte(0x5B); |
1188 emit_byte(0xC0 | encode); | 1263 emit_byte(0xC0 | encode); |
1189 } | 1264 } |
1190 | 1265 |
1191 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | 1266 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { |
1192 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1267 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1193 emit_byte(0xF2); | 1268 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1194 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1195 emit_byte(0x0F); | |
1196 emit_byte(0x5A); | 1269 emit_byte(0x5A); |
1197 emit_byte(0xC0 | encode); | 1270 emit_byte(0xC0 | encode); |
1198 } | 1271 } |
1199 | 1272 |
1273 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { | |
1274 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1275 InstructionMark im(this); | |
1276 simd_prefix(dst, dst, src, VEX_SIMD_F2); | |
1277 emit_byte(0x5A); | |
1278 emit_operand(dst, src); | |
1279 } | |
1280 | |
1200 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { | 1281 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { |
1201 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1282 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1202 emit_byte(0xF2); | 1283 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1203 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1204 emit_byte(0x0F); | |
1205 emit_byte(0x2A); | 1284 emit_byte(0x2A); |
1206 emit_byte(0xC0 | encode); | 1285 emit_byte(0xC0 | encode); |
1207 } | 1286 } |
1208 | 1287 |
1288 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { | |
1289 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1290 InstructionMark im(this); | |
1291 simd_prefix(dst, dst, src, VEX_SIMD_F2); | |
1292 emit_byte(0x2A); | |
1293 emit_operand(dst, src); | |
1294 } | |
1295 | |
1209 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { | 1296 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { |
1210 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1297 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1211 emit_byte(0xF3); | 1298 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1212 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1213 emit_byte(0x0F); | |
1214 emit_byte(0x2A); | 1299 emit_byte(0x2A); |
1215 emit_byte(0xC0 | encode); | 1300 emit_byte(0xC0 | encode); |
1216 } | 1301 } |
1217 | 1302 |
1303 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { | |
1304 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1305 InstructionMark im(this); | |
1306 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
1307 emit_byte(0x2A); | |
1308 emit_operand(dst, src); | |
1309 } | |
1310 | |
1218 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { | 1311 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { |
1219 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1312 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1220 emit_byte(0xF3); | 1313 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1221 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1222 emit_byte(0x0F); | |
1223 emit_byte(0x5A); | 1314 emit_byte(0x5A); |
1224 emit_byte(0xC0 | encode); | 1315 emit_byte(0xC0 | encode); |
1225 } | 1316 } |
1226 | 1317 |
1318 void Assembler::cvtss2sd(XMMRegister dst, Address src) { | |
1319 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1320 InstructionMark im(this); | |
1321 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
1322 emit_byte(0x5A); | |
1323 emit_operand(dst, src); | |
1324 } | |
1325 | |
1326 | |
1227 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { | 1327 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { |
1228 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1328 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1229 emit_byte(0xF2); | 1329 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
1230 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1231 emit_byte(0x0F); | |
1232 emit_byte(0x2C); | 1330 emit_byte(0x2C); |
1233 emit_byte(0xC0 | encode); | 1331 emit_byte(0xC0 | encode); |
1234 } | 1332 } |
1235 | 1333 |
1236 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | 1334 void Assembler::cvttss2sil(Register dst, XMMRegister src) { |
1237 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1335 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1238 emit_byte(0xF3); | 1336 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
1239 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1240 emit_byte(0x0F); | |
1241 emit_byte(0x2C); | 1337 emit_byte(0x2C); |
1242 emit_byte(0xC0 | encode); | 1338 emit_byte(0xC0 | encode); |
1243 } | 1339 } |
1244 | 1340 |
1245 void Assembler::decl(Address dst) { | 1341 void Assembler::decl(Address dst) { |
1251 } | 1347 } |
1252 | 1348 |
1253 void Assembler::divsd(XMMRegister dst, Address src) { | 1349 void Assembler::divsd(XMMRegister dst, Address src) { |
1254 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1350 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1255 InstructionMark im(this); | 1351 InstructionMark im(this); |
1256 emit_byte(0xF2); | 1352 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
1257 prefix(src, dst); | |
1258 emit_byte(0x0F); | |
1259 emit_byte(0x5E); | 1353 emit_byte(0x5E); |
1260 emit_operand(dst, src); | 1354 emit_operand(dst, src); |
1261 } | 1355 } |
1262 | 1356 |
1263 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | 1357 void Assembler::divsd(XMMRegister dst, XMMRegister src) { |
1264 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1358 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1265 emit_byte(0xF2); | 1359 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1266 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1267 emit_byte(0x0F); | |
1268 emit_byte(0x5E); | 1360 emit_byte(0x5E); |
1269 emit_byte(0xC0 | encode); | 1361 emit_byte(0xC0 | encode); |
1270 } | 1362 } |
1271 | 1363 |
1272 void Assembler::divss(XMMRegister dst, Address src) { | 1364 void Assembler::divss(XMMRegister dst, Address src) { |
1273 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1365 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1274 InstructionMark im(this); | 1366 InstructionMark im(this); |
1275 emit_byte(0xF3); | 1367 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
1276 prefix(src, dst); | |
1277 emit_byte(0x0F); | |
1278 emit_byte(0x5E); | 1368 emit_byte(0x5E); |
1279 emit_operand(dst, src); | 1369 emit_operand(dst, src); |
1280 } | 1370 } |
1281 | 1371 |
1282 void Assembler::divss(XMMRegister dst, XMMRegister src) { | 1372 void Assembler::divss(XMMRegister dst, XMMRegister src) { |
1283 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1373 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1284 emit_byte(0xF3); | 1374 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1285 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1286 emit_byte(0x0F); | |
1287 emit_byte(0x5E); | 1375 emit_byte(0x5E); |
1288 emit_byte(0xC0 | encode); | 1376 emit_byte(0xC0 | encode); |
1289 } | 1377 } |
1290 | 1378 |
1291 void Assembler::emms() { | 1379 void Assembler::emms() { |
1375 | 1463 |
1376 void Assembler::jccb(Condition cc, Label& L) { | 1464 void Assembler::jccb(Condition cc, Label& L) { |
1377 if (L.is_bound()) { | 1465 if (L.is_bound()) { |
1378 const int short_size = 2; | 1466 const int short_size = 2; |
1379 address entry = target(L); | 1467 address entry = target(L); |
1380 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)), | 1468 #ifdef ASSERT |
1381 "Dispacement too large for a short jmp"); | 1469 intptr_t dist = (intptr_t)entry - ((intptr_t)_code_pos + short_size); |
1470 intptr_t delta = short_branch_delta(); | |
1471 if (delta != 0) { | |
1472 dist += (dist < 0 ? (-delta) :delta); | |
1473 } | |
1474 assert(is8bit(dist), "Dispacement too large for a short jmp"); | |
1475 #endif | |
1382 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; | 1476 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; |
1383 // 0111 tttn #8-bit disp | 1477 // 0111 tttn #8-bit disp |
1384 emit_byte(0x70 | cc); | 1478 emit_byte(0x70 | cc); |
1385 emit_byte((offs - short_size) & 0xFF); | 1479 emit_byte((offs - short_size) & 0xFF); |
1386 } else { | 1480 } else { |
1442 | 1536 |
1443 void Assembler::jmpb(Label& L) { | 1537 void Assembler::jmpb(Label& L) { |
1444 if (L.is_bound()) { | 1538 if (L.is_bound()) { |
1445 const int short_size = 2; | 1539 const int short_size = 2; |
1446 address entry = target(L); | 1540 address entry = target(L); |
1447 assert(is8bit((entry - _code_pos) + short_size), | |
1448 "Dispacement too large for a short jmp"); | |
1449 assert(entry != NULL, "jmp most probably wrong"); | 1541 assert(entry != NULL, "jmp most probably wrong"); |
1542 #ifdef ASSERT | |
1543 intptr_t dist = (intptr_t)entry - ((intptr_t)_code_pos + short_size); | |
1544 intptr_t delta = short_branch_delta(); | |
1545 if (delta != 0) { | |
1546 dist += (dist < 0 ? (-delta) :delta); | |
1547 } | |
1548 assert(is8bit(dist), "Dispacement too large for a short jmp"); | |
1549 #endif | |
1450 intptr_t offs = entry - _code_pos; | 1550 intptr_t offs = entry - _code_pos; |
1451 emit_byte(0xEB); | 1551 emit_byte(0xEB); |
1452 emit_byte((offs - short_size) & 0xFF); | 1552 emit_byte((offs - short_size) & 0xFF); |
1453 } else { | 1553 } else { |
1454 InstructionMark im(this); | 1554 InstructionMark im(this); |
1507 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | 1607 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); |
1508 } | 1608 } |
1509 | 1609 |
1510 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | 1610 void Assembler::movapd(XMMRegister dst, XMMRegister src) { |
1511 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1611 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1512 int dstenc = dst->encoding(); | 1612 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
1513 int srcenc = src->encoding(); | |
1514 emit_byte(0x66); | |
1515 if (dstenc < 8) { | |
1516 if (srcenc >= 8) { | |
1517 prefix(REX_B); | |
1518 srcenc -= 8; | |
1519 } | |
1520 } else { | |
1521 if (srcenc < 8) { | |
1522 prefix(REX_R); | |
1523 } else { | |
1524 prefix(REX_RB); | |
1525 srcenc -= 8; | |
1526 } | |
1527 dstenc -= 8; | |
1528 } | |
1529 emit_byte(0x0F); | |
1530 emit_byte(0x28); | 1613 emit_byte(0x28); |
1531 emit_byte(0xC0 | dstenc << 3 | srcenc); | 1614 emit_byte(0xC0 | encode); |
1532 } | 1615 } |
1533 | 1616 |
1534 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | 1617 void Assembler::movaps(XMMRegister dst, XMMRegister src) { |
1535 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1618 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1536 int dstenc = dst->encoding(); | 1619 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
1537 int srcenc = src->encoding(); | |
1538 if (dstenc < 8) { | |
1539 if (srcenc >= 8) { | |
1540 prefix(REX_B); | |
1541 srcenc -= 8; | |
1542 } | |
1543 } else { | |
1544 if (srcenc < 8) { | |
1545 prefix(REX_R); | |
1546 } else { | |
1547 prefix(REX_RB); | |
1548 srcenc -= 8; | |
1549 } | |
1550 dstenc -= 8; | |
1551 } | |
1552 emit_byte(0x0F); | |
1553 emit_byte(0x28); | 1620 emit_byte(0x28); |
1554 emit_byte(0xC0 | dstenc << 3 | srcenc); | 1621 emit_byte(0xC0 | encode); |
1555 } | 1622 } |
1556 | 1623 |
1557 void Assembler::movb(Register dst, Address src) { | 1624 void Assembler::movb(Register dst, Address src) { |
1558 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | 1625 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); |
1559 InstructionMark im(this); | 1626 InstructionMark im(this); |
1580 emit_operand(src, dst); | 1647 emit_operand(src, dst); |
1581 } | 1648 } |
1582 | 1649 |
1583 void Assembler::movdl(XMMRegister dst, Register src) { | 1650 void Assembler::movdl(XMMRegister dst, Register src) { |
1584 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1651 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1585 emit_byte(0x66); | 1652 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
1586 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1587 emit_byte(0x0F); | |
1588 emit_byte(0x6E); | 1653 emit_byte(0x6E); |
1589 emit_byte(0xC0 | encode); | 1654 emit_byte(0xC0 | encode); |
1590 } | 1655 } |
1591 | 1656 |
1592 void Assembler::movdl(Register dst, XMMRegister src) { | 1657 void Assembler::movdl(Register dst, XMMRegister src) { |
1593 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1658 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1594 emit_byte(0x66); | |
1595 // swap src/dst to get correct prefix | 1659 // swap src/dst to get correct prefix |
1596 int encode = prefix_and_encode(src->encoding(), dst->encoding()); | 1660 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66); |
1597 emit_byte(0x0F); | |
1598 emit_byte(0x7E); | 1661 emit_byte(0x7E); |
1599 emit_byte(0xC0 | encode); | 1662 emit_byte(0xC0 | encode); |
1600 } | 1663 } |
1601 | 1664 |
1602 void Assembler::movdl(XMMRegister dst, Address src) { | 1665 void Assembler::movdl(XMMRegister dst, Address src) { |
1603 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1666 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1604 InstructionMark im(this); | 1667 InstructionMark im(this); |
1605 emit_byte(0x66); | 1668 simd_prefix(dst, src, VEX_SIMD_66); |
1606 prefix(src, dst); | |
1607 emit_byte(0x0F); | |
1608 emit_byte(0x6E); | 1669 emit_byte(0x6E); |
1609 emit_operand(dst, src); | 1670 emit_operand(dst, src); |
1610 } | 1671 } |
1611 | 1672 |
1612 | 1673 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { |
1613 void Assembler::movdqa(XMMRegister dst, Address src) { | |
1614 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1674 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1615 InstructionMark im(this); | 1675 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
1616 emit_byte(0x66); | 1676 emit_byte(0x6F); |
1617 prefix(src, dst); | 1677 emit_byte(0xC0 | encode); |
1618 emit_byte(0x0F); | 1678 } |
1679 | |
1680 void Assembler::movdqu(XMMRegister dst, Address src) { | |
1681 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1682 InstructionMark im(this); | |
1683 simd_prefix(dst, src, VEX_SIMD_F3); | |
1619 emit_byte(0x6F); | 1684 emit_byte(0x6F); |
1620 emit_operand(dst, src); | 1685 emit_operand(dst, src); |
1621 } | 1686 } |
1622 | 1687 |
1623 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { | 1688 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { |
1624 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1689 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1625 emit_byte(0x66); | 1690 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
1626 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
1627 emit_byte(0x0F); | |
1628 emit_byte(0x6F); | 1691 emit_byte(0x6F); |
1629 emit_byte(0xC0 | encode); | 1692 emit_byte(0xC0 | encode); |
1630 } | 1693 } |
1631 | 1694 |
1632 void Assembler::movdqa(Address dst, XMMRegister src) { | |
1633 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1634 InstructionMark im(this); | |
1635 emit_byte(0x66); | |
1636 prefix(dst, src); | |
1637 emit_byte(0x0F); | |
1638 emit_byte(0x7F); | |
1639 emit_operand(src, dst); | |
1640 } | |
1641 | |
1642 void Assembler::movdqu(XMMRegister dst, Address src) { | |
1643 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1644 InstructionMark im(this); | |
1645 emit_byte(0xF3); | |
1646 prefix(src, dst); | |
1647 emit_byte(0x0F); | |
1648 emit_byte(0x6F); | |
1649 emit_operand(dst, src); | |
1650 } | |
1651 | |
1652 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
1653 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1654 emit_byte(0xF3); | |
1655 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
1656 emit_byte(0x0F); | |
1657 emit_byte(0x6F); | |
1658 emit_byte(0xC0 | encode); | |
1659 } | |
1660 | |
1661 void Assembler::movdqu(Address dst, XMMRegister src) { | 1695 void Assembler::movdqu(Address dst, XMMRegister src) { |
1662 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1696 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1663 InstructionMark im(this); | 1697 InstructionMark im(this); |
1664 emit_byte(0xF3); | 1698 simd_prefix(dst, src, VEX_SIMD_F3); |
1665 prefix(dst, src); | |
1666 emit_byte(0x0F); | |
1667 emit_byte(0x7F); | 1699 emit_byte(0x7F); |
1668 emit_operand(src, dst); | 1700 emit_operand(src, dst); |
1669 } | 1701 } |
1670 | 1702 |
1671 // Uses zero extension on 64bit | 1703 // Uses zero extension on 64bit |
1708 // when loading from memory. But for old Opteron use movlpd instead of movsd. | 1740 // when loading from memory. But for old Opteron use movlpd instead of movsd. |
1709 // The selection is done in MacroAssembler::movdbl() and movflt(). | 1741 // The selection is done in MacroAssembler::movdbl() and movflt(). |
1710 void Assembler::movlpd(XMMRegister dst, Address src) { | 1742 void Assembler::movlpd(XMMRegister dst, Address src) { |
1711 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1743 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1712 InstructionMark im(this); | 1744 InstructionMark im(this); |
1713 emit_byte(0x66); | 1745 simd_prefix(dst, dst, src, VEX_SIMD_66); |
1714 prefix(src, dst); | |
1715 emit_byte(0x0F); | |
1716 emit_byte(0x12); | 1746 emit_byte(0x12); |
1717 emit_operand(dst, src); | 1747 emit_operand(dst, src); |
1718 } | 1748 } |
1719 | 1749 |
1720 void Assembler::movq( MMXRegister dst, Address src ) { | 1750 void Assembler::movq( MMXRegister dst, Address src ) { |
1738 } | 1768 } |
1739 | 1769 |
1740 void Assembler::movq(XMMRegister dst, Address src) { | 1770 void Assembler::movq(XMMRegister dst, Address src) { |
1741 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1771 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1742 InstructionMark im(this); | 1772 InstructionMark im(this); |
1743 emit_byte(0xF3); | 1773 simd_prefix(dst, src, VEX_SIMD_F3); |
1744 prefix(src, dst); | |
1745 emit_byte(0x0F); | |
1746 emit_byte(0x7E); | 1774 emit_byte(0x7E); |
1747 emit_operand(dst, src); | 1775 emit_operand(dst, src); |
1748 } | 1776 } |
1749 | 1777 |
1750 void Assembler::movq(Address dst, XMMRegister src) { | 1778 void Assembler::movq(Address dst, XMMRegister src) { |
1751 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1779 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1752 InstructionMark im(this); | 1780 InstructionMark im(this); |
1753 emit_byte(0x66); | 1781 simd_prefix(dst, src, VEX_SIMD_66); |
1754 prefix(dst, src); | |
1755 emit_byte(0x0F); | |
1756 emit_byte(0xD6); | 1782 emit_byte(0xD6); |
1757 emit_operand(src, dst); | 1783 emit_operand(src, dst); |
1758 } | 1784 } |
1759 | 1785 |
1760 void Assembler::movsbl(Register dst, Address src) { // movsxb | 1786 void Assembler::movsbl(Register dst, Address src) { // movsxb |
1773 emit_byte(0xC0 | encode); | 1799 emit_byte(0xC0 | encode); |
1774 } | 1800 } |
1775 | 1801 |
1776 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | 1802 void Assembler::movsd(XMMRegister dst, XMMRegister src) { |
1777 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1803 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1778 emit_byte(0xF2); | 1804 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1779 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1780 emit_byte(0x0F); | |
1781 emit_byte(0x10); | 1805 emit_byte(0x10); |
1782 emit_byte(0xC0 | encode); | 1806 emit_byte(0xC0 | encode); |
1783 } | 1807 } |
1784 | 1808 |
1785 void Assembler::movsd(XMMRegister dst, Address src) { | 1809 void Assembler::movsd(XMMRegister dst, Address src) { |
1786 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1810 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1787 InstructionMark im(this); | 1811 InstructionMark im(this); |
1788 emit_byte(0xF2); | 1812 simd_prefix(dst, src, VEX_SIMD_F2); |
1789 prefix(src, dst); | |
1790 emit_byte(0x0F); | |
1791 emit_byte(0x10); | 1813 emit_byte(0x10); |
1792 emit_operand(dst, src); | 1814 emit_operand(dst, src); |
1793 } | 1815 } |
1794 | 1816 |
1795 void Assembler::movsd(Address dst, XMMRegister src) { | 1817 void Assembler::movsd(Address dst, XMMRegister src) { |
1796 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1818 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1797 InstructionMark im(this); | 1819 InstructionMark im(this); |
1798 emit_byte(0xF2); | 1820 simd_prefix(dst, src, VEX_SIMD_F2); |
1799 prefix(dst, src); | |
1800 emit_byte(0x0F); | |
1801 emit_byte(0x11); | 1821 emit_byte(0x11); |
1802 emit_operand(src, dst); | 1822 emit_operand(src, dst); |
1803 } | 1823 } |
1804 | 1824 |
1805 void Assembler::movss(XMMRegister dst, XMMRegister src) { | 1825 void Assembler::movss(XMMRegister dst, XMMRegister src) { |
1806 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1826 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1807 emit_byte(0xF3); | 1827 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1808 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1809 emit_byte(0x0F); | |
1810 emit_byte(0x10); | 1828 emit_byte(0x10); |
1811 emit_byte(0xC0 | encode); | 1829 emit_byte(0xC0 | encode); |
1812 } | 1830 } |
1813 | 1831 |
1814 void Assembler::movss(XMMRegister dst, Address src) { | 1832 void Assembler::movss(XMMRegister dst, Address src) { |
1815 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1833 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1816 InstructionMark im(this); | 1834 InstructionMark im(this); |
1817 emit_byte(0xF3); | 1835 simd_prefix(dst, src, VEX_SIMD_F3); |
1818 prefix(src, dst); | |
1819 emit_byte(0x0F); | |
1820 emit_byte(0x10); | 1836 emit_byte(0x10); |
1821 emit_operand(dst, src); | 1837 emit_operand(dst, src); |
1822 } | 1838 } |
1823 | 1839 |
1824 void Assembler::movss(Address dst, XMMRegister src) { | 1840 void Assembler::movss(Address dst, XMMRegister src) { |
1825 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1841 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1826 InstructionMark im(this); | 1842 InstructionMark im(this); |
1827 emit_byte(0xF3); | 1843 simd_prefix(dst, src, VEX_SIMD_F3); |
1828 prefix(dst, src); | |
1829 emit_byte(0x0F); | |
1830 emit_byte(0x11); | 1844 emit_byte(0x11); |
1831 emit_operand(src, dst); | 1845 emit_operand(src, dst); |
1832 } | 1846 } |
1833 | 1847 |
1834 void Assembler::movswl(Register dst, Address src) { // movsxw | 1848 void Assembler::movswl(Register dst, Address src) { // movsxw |
1917 } | 1931 } |
1918 | 1932 |
1919 void Assembler::mulsd(XMMRegister dst, Address src) { | 1933 void Assembler::mulsd(XMMRegister dst, Address src) { |
1920 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1934 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1921 InstructionMark im(this); | 1935 InstructionMark im(this); |
1922 emit_byte(0xF2); | 1936 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
1923 prefix(src, dst); | |
1924 emit_byte(0x0F); | |
1925 emit_byte(0x59); | 1937 emit_byte(0x59); |
1926 emit_operand(dst, src); | 1938 emit_operand(dst, src); |
1927 } | 1939 } |
1928 | 1940 |
1929 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | 1941 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { |
1930 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1942 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1931 emit_byte(0xF2); | 1943 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1932 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1933 emit_byte(0x0F); | |
1934 emit_byte(0x59); | 1944 emit_byte(0x59); |
1935 emit_byte(0xC0 | encode); | 1945 emit_byte(0xC0 | encode); |
1936 } | 1946 } |
1937 | 1947 |
1938 void Assembler::mulss(XMMRegister dst, Address src) { | 1948 void Assembler::mulss(XMMRegister dst, Address src) { |
1939 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1949 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1940 InstructionMark im(this); | 1950 InstructionMark im(this); |
1941 emit_byte(0xF3); | 1951 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
1942 prefix(src, dst); | |
1943 emit_byte(0x0F); | |
1944 emit_byte(0x59); | 1952 emit_byte(0x59); |
1945 emit_operand(dst, src); | 1953 emit_operand(dst, src); |
1946 } | 1954 } |
1947 | 1955 |
1948 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | 1956 void Assembler::mulss(XMMRegister dst, XMMRegister src) { |
1949 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1957 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1950 emit_byte(0xF3); | 1958 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1951 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1952 emit_byte(0x0F); | |
1953 emit_byte(0x59); | 1959 emit_byte(0x59); |
1954 emit_byte(0xC0 | encode); | 1960 emit_byte(0xC0 | encode); |
1955 } | 1961 } |
1956 | 1962 |
1957 void Assembler::negl(Register dst) { | 1963 void Assembler::negl(Register dst) { |
2235 void Assembler::orl(Register dst, Register src) { | 2241 void Assembler::orl(Register dst, Register src) { |
2236 (void) prefix_and_encode(dst->encoding(), src->encoding()); | 2242 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
2237 emit_arith(0x0B, 0xC0, dst, src); | 2243 emit_arith(0x0B, 0xC0, dst, src); |
2238 } | 2244 } |
2239 | 2245 |
2246 void Assembler::packuswb(XMMRegister dst, Address src) { | |
2247 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2248 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
2249 InstructionMark im(this); | |
2250 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
2251 emit_byte(0x67); | |
2252 emit_operand(dst, src); | |
2253 } | |
2254 | |
2255 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { | |
2256 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2257 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | |
2258 emit_byte(0x67); | |
2259 emit_byte(0xC0 | encode); | |
2260 } | |
2261 | |
2240 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { | 2262 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
2241 assert(VM_Version::supports_sse4_2(), ""); | 2263 assert(VM_Version::supports_sse4_2(), ""); |
2242 | 2264 InstructionMark im(this); |
2243 InstructionMark im(this); | 2265 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
2244 emit_byte(0x66); | |
2245 prefix(src, dst); | |
2246 emit_byte(0x0F); | |
2247 emit_byte(0x3A); | |
2248 emit_byte(0x61); | 2266 emit_byte(0x61); |
2249 emit_operand(dst, src); | 2267 emit_operand(dst, src); |
2250 emit_byte(imm8); | 2268 emit_byte(imm8); |
2251 } | 2269 } |
2252 | 2270 |
2253 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | 2271 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { |
2254 assert(VM_Version::supports_sse4_2(), ""); | 2272 assert(VM_Version::supports_sse4_2(), ""); |
2255 | 2273 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
2256 emit_byte(0x66); | |
2257 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
2258 emit_byte(0x0F); | |
2259 emit_byte(0x3A); | |
2260 emit_byte(0x61); | 2274 emit_byte(0x61); |
2261 emit_byte(0xC0 | encode); | 2275 emit_byte(0xC0 | encode); |
2262 emit_byte(imm8); | 2276 emit_byte(imm8); |
2277 } | |
2278 | |
2279 void Assembler::pmovzxbw(XMMRegister dst, Address src) { | |
2280 assert(VM_Version::supports_sse4_1(), ""); | |
2281 InstructionMark im(this); | |
2282 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
2283 emit_byte(0x30); | |
2284 emit_operand(dst, src); | |
2285 } | |
2286 | |
2287 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { | |
2288 assert(VM_Version::supports_sse4_1(), ""); | |
2289 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
2290 emit_byte(0x30); | |
2291 emit_byte(0xC0 | encode); | |
2263 } | 2292 } |
2264 | 2293 |
2265 // generic | 2294 // generic |
2266 void Assembler::pop(Register dst) { | 2295 void Assembler::pop(Register dst) { |
2267 int encode = prefix_and_encode(dst->encoding()); | 2296 int encode = prefix_and_encode(dst->encoding()); |
2358 a_byte(p); | 2387 a_byte(p); |
2359 } | 2388 } |
2360 | 2389 |
2361 void Assembler::por(XMMRegister dst, XMMRegister src) { | 2390 void Assembler::por(XMMRegister dst, XMMRegister src) { |
2362 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2391 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2363 | 2392 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
2364 emit_byte(0x66); | |
2365 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2366 emit_byte(0x0F); | |
2367 | |
2368 emit_byte(0xEB); | 2393 emit_byte(0xEB); |
2369 emit_byte(0xC0 | encode); | 2394 emit_byte(0xC0 | encode); |
2395 } | |
2396 | |
2397 void Assembler::por(XMMRegister dst, Address src) { | |
2398 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2399 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
2400 InstructionMark im(this); | |
2401 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
2402 emit_byte(0xEB); | |
2403 emit_operand(dst, src); | |
2370 } | 2404 } |
2371 | 2405 |
2372 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { | 2406 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
2373 assert(isByte(mode), "invalid value"); | 2407 assert(isByte(mode), "invalid value"); |
2374 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2408 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2375 | 2409 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
2376 emit_byte(0x66); | |
2377 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2378 emit_byte(0x0F); | |
2379 emit_byte(0x70); | 2410 emit_byte(0x70); |
2380 emit_byte(0xC0 | encode); | 2411 emit_byte(0xC0 | encode); |
2381 emit_byte(mode & 0xFF); | 2412 emit_byte(mode & 0xFF); |
2382 | 2413 |
2383 } | 2414 } |
2384 | 2415 |
2385 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | 2416 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { |
2386 assert(isByte(mode), "invalid value"); | 2417 assert(isByte(mode), "invalid value"); |
2387 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2418 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2388 | 2419 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2389 InstructionMark im(this); | 2420 InstructionMark im(this); |
2390 emit_byte(0x66); | 2421 simd_prefix(dst, src, VEX_SIMD_66); |
2391 prefix(src, dst); | |
2392 emit_byte(0x0F); | |
2393 emit_byte(0x70); | 2422 emit_byte(0x70); |
2394 emit_operand(dst, src); | 2423 emit_operand(dst, src); |
2395 emit_byte(mode & 0xFF); | 2424 emit_byte(mode & 0xFF); |
2396 } | 2425 } |
2397 | 2426 |
2398 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | 2427 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { |
2399 assert(isByte(mode), "invalid value"); | 2428 assert(isByte(mode), "invalid value"); |
2400 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2429 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2401 | 2430 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
2402 emit_byte(0xF2); | |
2403 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2404 emit_byte(0x0F); | |
2405 emit_byte(0x70); | 2431 emit_byte(0x70); |
2406 emit_byte(0xC0 | encode); | 2432 emit_byte(0xC0 | encode); |
2407 emit_byte(mode & 0xFF); | 2433 emit_byte(mode & 0xFF); |
2408 } | 2434 } |
2409 | 2435 |
2410 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | 2436 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { |
2411 assert(isByte(mode), "invalid value"); | 2437 assert(isByte(mode), "invalid value"); |
2412 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2438 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2413 | 2439 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2414 InstructionMark im(this); | 2440 InstructionMark im(this); |
2415 emit_byte(0xF2); | 2441 simd_prefix(dst, src, VEX_SIMD_F2); |
2416 prefix(src, dst); // QQ new | |
2417 emit_byte(0x0F); | |
2418 emit_byte(0x70); | 2442 emit_byte(0x70); |
2419 emit_operand(dst, src); | 2443 emit_operand(dst, src); |
2420 emit_byte(mode & 0xFF); | 2444 emit_byte(mode & 0xFF); |
2421 } | 2445 } |
2422 | 2446 |
2423 void Assembler::psrlq(XMMRegister dst, int shift) { | 2447 void Assembler::psrlq(XMMRegister dst, int shift) { |
2424 // Shift 64 bit value logically right by specified number of bits. | 2448 // Shift 64 bit value logically right by specified number of bits. |
2425 // HMM Table D-1 says sse2 or mmx. | 2449 // HMM Table D-1 says sse2 or mmx. |
2426 // Do not confuse it with psrldq SSE2 instruction which | 2450 // Do not confuse it with psrldq SSE2 instruction which |
2427 // shifts 128 bit value in xmm register by number of bytes. | 2451 // shifts 128 bit value in xmm register by number of bytes. |
2428 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2452 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2429 | 2453 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
2430 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding()); | |
2431 emit_byte(0x66); | |
2432 emit_byte(0x0F); | |
2433 emit_byte(0x73); | 2454 emit_byte(0x73); |
2434 emit_byte(0xC0 | encode); | 2455 emit_byte(0xC0 | encode); |
2435 emit_byte(shift); | 2456 emit_byte(shift); |
2436 } | 2457 } |
2437 | 2458 |
2438 void Assembler::psrldq(XMMRegister dst, int shift) { | 2459 void Assembler::psrldq(XMMRegister dst, int shift) { |
2439 // Shift 128 bit value in xmm register by number of bytes. | 2460 // Shift 128 bit value in xmm register by number of bytes. |
2440 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2461 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2441 | 2462 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66); |
2442 int encode = prefixq_and_encode(xmm3->encoding(), dst->encoding()); | |
2443 emit_byte(0x66); | |
2444 emit_byte(0x0F); | |
2445 emit_byte(0x73); | 2463 emit_byte(0x73); |
2446 emit_byte(0xC0 | encode); | 2464 emit_byte(0xC0 | encode); |
2447 emit_byte(shift); | 2465 emit_byte(shift); |
2448 } | 2466 } |
2449 | 2467 |
2450 void Assembler::ptest(XMMRegister dst, Address src) { | 2468 void Assembler::ptest(XMMRegister dst, Address src) { |
2451 assert(VM_Version::supports_sse4_1(), ""); | 2469 assert(VM_Version::supports_sse4_1(), ""); |
2452 | 2470 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2453 InstructionMark im(this); | 2471 InstructionMark im(this); |
2454 emit_byte(0x66); | 2472 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
2455 prefix(src, dst); | |
2456 emit_byte(0x0F); | |
2457 emit_byte(0x38); | |
2458 emit_byte(0x17); | 2473 emit_byte(0x17); |
2459 emit_operand(dst, src); | 2474 emit_operand(dst, src); |
2460 } | 2475 } |
2461 | 2476 |
2462 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | 2477 void Assembler::ptest(XMMRegister dst, XMMRegister src) { |
2463 assert(VM_Version::supports_sse4_1(), ""); | 2478 assert(VM_Version::supports_sse4_1(), ""); |
2464 | 2479 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
2465 emit_byte(0x66); | |
2466 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
2467 emit_byte(0x0F); | |
2468 emit_byte(0x38); | |
2469 emit_byte(0x17); | 2480 emit_byte(0x17); |
2470 emit_byte(0xC0 | encode); | 2481 emit_byte(0xC0 | encode); |
2471 } | 2482 } |
2472 | 2483 |
2484 void Assembler::punpcklbw(XMMRegister dst, Address src) { | |
2485 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2486 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
2487 InstructionMark im(this); | |
2488 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
2489 emit_byte(0x60); | |
2490 emit_operand(dst, src); | |
2491 } | |
2492 | |
2473 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { | 2493 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
2474 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2494 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2475 emit_byte(0x66); | 2495 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
2476 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2477 emit_byte(0x0F); | |
2478 emit_byte(0x60); | 2496 emit_byte(0x60); |
2497 emit_byte(0xC0 | encode); | |
2498 } | |
2499 | |
2500 void Assembler::punpckldq(XMMRegister dst, Address src) { | |
2501 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2502 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
2503 InstructionMark im(this); | |
2504 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
2505 emit_byte(0x62); | |
2506 emit_operand(dst, src); | |
2507 } | |
2508 | |
2509 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { | |
2510 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2511 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | |
2512 emit_byte(0x62); | |
2479 emit_byte(0xC0 | encode); | 2513 emit_byte(0xC0 | encode); |
2480 } | 2514 } |
2481 | 2515 |
2482 void Assembler::push(int32_t imm32) { | 2516 void Assembler::push(int32_t imm32) { |
2483 // in 64bits we push 64bits onto the stack but only | 2517 // in 64bits we push 64bits onto the stack but only |
2506 } | 2540 } |
2507 #endif | 2541 #endif |
2508 | 2542 |
2509 void Assembler::pxor(XMMRegister dst, Address src) { | 2543 void Assembler::pxor(XMMRegister dst, Address src) { |
2510 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2544 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2511 InstructionMark im(this); | 2545 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2512 emit_byte(0x66); | 2546 InstructionMark im(this); |
2513 prefix(src, dst); | 2547 simd_prefix(dst, dst, src, VEX_SIMD_66); |
2514 emit_byte(0x0F); | |
2515 emit_byte(0xEF); | 2548 emit_byte(0xEF); |
2516 emit_operand(dst, src); | 2549 emit_operand(dst, src); |
2517 } | 2550 } |
2518 | 2551 |
2519 void Assembler::pxor(XMMRegister dst, XMMRegister src) { | 2552 void Assembler::pxor(XMMRegister dst, XMMRegister src) { |
2520 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2553 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2521 InstructionMark im(this); | 2554 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
2522 emit_byte(0x66); | |
2523 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2524 emit_byte(0x0F); | |
2525 emit_byte(0xEF); | 2555 emit_byte(0xEF); |
2526 emit_byte(0xC0 | encode); | 2556 emit_byte(0xC0 | encode); |
2527 } | 2557 } |
2528 | 2558 |
2529 void Assembler::rcll(Register dst, int imm8) { | 2559 void Assembler::rcll(Register dst, int imm8) { |
2681 void Assembler::smovl() { | 2711 void Assembler::smovl() { |
2682 emit_byte(0xA5); | 2712 emit_byte(0xA5); |
2683 } | 2713 } |
2684 | 2714 |
2685 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { | 2715 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
2686 // HMM Table D-1 says sse2 | |
2687 // NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2688 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2716 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2689 emit_byte(0xF2); | 2717 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
2690 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2691 emit_byte(0x0F); | |
2692 emit_byte(0x51); | 2718 emit_byte(0x51); |
2693 emit_byte(0xC0 | encode); | 2719 emit_byte(0xC0 | encode); |
2694 } | 2720 } |
2695 | 2721 |
2696 void Assembler::sqrtsd(XMMRegister dst, Address src) { | 2722 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
2697 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2723 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2698 InstructionMark im(this); | 2724 InstructionMark im(this); |
2699 emit_byte(0xF2); | 2725 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
2700 prefix(src, dst); | |
2701 emit_byte(0x0F); | |
2702 emit_byte(0x51); | 2726 emit_byte(0x51); |
2703 emit_operand(dst, src); | 2727 emit_operand(dst, src); |
2704 } | 2728 } |
2705 | 2729 |
2706 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | 2730 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { |
2707 // HMM Table D-1 says sse2 | 2731 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2708 // NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2732 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
2709 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2710 emit_byte(0xF3); | |
2711 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2712 emit_byte(0x0F); | |
2713 emit_byte(0x51); | 2733 emit_byte(0x51); |
2714 emit_byte(0xC0 | encode); | 2734 emit_byte(0xC0 | encode); |
2715 } | 2735 } |
2716 | 2736 |
2717 void Assembler::sqrtss(XMMRegister dst, Address src) { | 2737 void Assembler::sqrtss(XMMRegister dst, Address src) { |
2718 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2738 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2719 InstructionMark im(this); | 2739 InstructionMark im(this); |
2720 emit_byte(0xF3); | 2740 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
2721 prefix(src, dst); | |
2722 emit_byte(0x0F); | |
2723 emit_byte(0x51); | 2741 emit_byte(0x51); |
2724 emit_operand(dst, src); | 2742 emit_operand(dst, src); |
2725 } | 2743 } |
2726 | 2744 |
2727 void Assembler::stmxcsr( Address dst) { | 2745 void Assembler::stmxcsr( Address dst) { |
2763 emit_arith(0x2B, 0xC0, dst, src); | 2781 emit_arith(0x2B, 0xC0, dst, src); |
2764 } | 2782 } |
2765 | 2783 |
2766 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | 2784 void Assembler::subsd(XMMRegister dst, XMMRegister src) { |
2767 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2785 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2768 emit_byte(0xF2); | 2786 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
2769 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2770 emit_byte(0x0F); | |
2771 emit_byte(0x5C); | 2787 emit_byte(0x5C); |
2772 emit_byte(0xC0 | encode); | 2788 emit_byte(0xC0 | encode); |
2773 } | 2789 } |
2774 | 2790 |
2775 void Assembler::subsd(XMMRegister dst, Address src) { | 2791 void Assembler::subsd(XMMRegister dst, Address src) { |
2776 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2792 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2777 InstructionMark im(this); | 2793 InstructionMark im(this); |
2778 emit_byte(0xF2); | 2794 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
2779 prefix(src, dst); | |
2780 emit_byte(0x0F); | |
2781 emit_byte(0x5C); | 2795 emit_byte(0x5C); |
2782 emit_operand(dst, src); | 2796 emit_operand(dst, src); |
2783 } | 2797 } |
2784 | 2798 |
2785 void Assembler::subss(XMMRegister dst, XMMRegister src) { | 2799 void Assembler::subss(XMMRegister dst, XMMRegister src) { |
2786 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2800 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2787 emit_byte(0xF3); | 2801 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
2788 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2789 emit_byte(0x0F); | |
2790 emit_byte(0x5C); | 2802 emit_byte(0x5C); |
2791 emit_byte(0xC0 | encode); | 2803 emit_byte(0xC0 | encode); |
2792 } | 2804 } |
2793 | 2805 |
2794 void Assembler::subss(XMMRegister dst, Address src) { | 2806 void Assembler::subss(XMMRegister dst, Address src) { |
2795 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2807 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2796 InstructionMark im(this); | 2808 InstructionMark im(this); |
2797 emit_byte(0xF3); | 2809 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
2798 prefix(src, dst); | |
2799 emit_byte(0x0F); | |
2800 emit_byte(0x5C); | 2810 emit_byte(0x5C); |
2801 emit_operand(dst, src); | 2811 emit_operand(dst, src); |
2802 } | 2812 } |
2803 | 2813 |
2804 void Assembler::testb(Register dst, int imm8) { | 2814 void Assembler::testb(Register dst, int imm8) { |
2834 emit_operand(dst, src); | 2844 emit_operand(dst, src); |
2835 } | 2845 } |
2836 | 2846 |
2837 void Assembler::ucomisd(XMMRegister dst, Address src) { | 2847 void Assembler::ucomisd(XMMRegister dst, Address src) { |
2838 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2848 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2839 emit_byte(0x66); | 2849 InstructionMark im(this); |
2840 ucomiss(dst, src); | 2850 simd_prefix(dst, src, VEX_SIMD_66); |
2851 emit_byte(0x2E); | |
2852 emit_operand(dst, src); | |
2841 } | 2853 } |
2842 | 2854 |
2843 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | 2855 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { |
2844 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2856 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2845 emit_byte(0x66); | 2857 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
2846 ucomiss(dst, src); | 2858 emit_byte(0x2E); |
2859 emit_byte(0xC0 | encode); | |
2847 } | 2860 } |
2848 | 2861 |
2849 void Assembler::ucomiss(XMMRegister dst, Address src) { | 2862 void Assembler::ucomiss(XMMRegister dst, Address src) { |
2850 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2863 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2851 | 2864 InstructionMark im(this); |
2852 InstructionMark im(this); | 2865 simd_prefix(dst, src, VEX_SIMD_NONE); |
2853 prefix(src, dst); | |
2854 emit_byte(0x0F); | |
2855 emit_byte(0x2E); | 2866 emit_byte(0x2E); |
2856 emit_operand(dst, src); | 2867 emit_operand(dst, src); |
2857 } | 2868 } |
2858 | 2869 |
2859 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | 2870 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { |
2860 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2871 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2861 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 2872 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
2862 emit_byte(0x0F); | |
2863 emit_byte(0x2E); | 2873 emit_byte(0x2E); |
2864 emit_byte(0xC0 | encode); | 2874 emit_byte(0xC0 | encode); |
2865 } | 2875 } |
2866 | 2876 |
2867 | 2877 |
2903 emit_arith(0x33, 0xC0, dst, src); | 2913 emit_arith(0x33, 0xC0, dst, src); |
2904 } | 2914 } |
2905 | 2915 |
2906 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { | 2916 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { |
2907 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2917 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2908 emit_byte(0x66); | 2918 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
2909 xorps(dst, src); | 2919 emit_byte(0x57); |
2920 emit_byte(0xC0 | encode); | |
2910 } | 2921 } |
2911 | 2922 |
2912 void Assembler::xorpd(XMMRegister dst, Address src) { | 2923 void Assembler::xorpd(XMMRegister dst, Address src) { |
2913 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2924 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2914 InstructionMark im(this); | 2925 InstructionMark im(this); |
2915 emit_byte(0x66); | 2926 simd_prefix(dst, dst, src, VEX_SIMD_66); |
2916 prefix(src, dst); | |
2917 emit_byte(0x0F); | |
2918 emit_byte(0x57); | 2927 emit_byte(0x57); |
2919 emit_operand(dst, src); | 2928 emit_operand(dst, src); |
2920 } | 2929 } |
2921 | 2930 |
2922 | 2931 |
2923 void Assembler::xorps(XMMRegister dst, XMMRegister src) { | 2932 void Assembler::xorps(XMMRegister dst, XMMRegister src) { |
2924 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2933 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2925 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 2934 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE); |
2926 emit_byte(0x0F); | |
2927 emit_byte(0x57); | 2935 emit_byte(0x57); |
2928 emit_byte(0xC0 | encode); | 2936 emit_byte(0xC0 | encode); |
2929 } | 2937 } |
2930 | 2938 |
2931 void Assembler::xorps(XMMRegister dst, Address src) { | 2939 void Assembler::xorps(XMMRegister dst, Address src) { |
2932 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2940 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2933 InstructionMark im(this); | 2941 InstructionMark im(this); |
2934 prefix(src, dst); | 2942 simd_prefix(dst, dst, src, VEX_SIMD_NONE); |
2935 emit_byte(0x0F); | |
2936 emit_byte(0x57); | 2943 emit_byte(0x57); |
2937 emit_operand(dst, src); | 2944 emit_operand(dst, src); |
2938 } | 2945 } |
2946 | |
2947 // AVX 3-operands non destructive source instructions (encoded with VEX prefix) | |
2948 | |
2949 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { | |
2950 assert(VM_Version::supports_avx(), ""); | |
2951 InstructionMark im(this); | |
2952 vex_prefix(dst, nds, src, VEX_SIMD_F2); | |
2953 emit_byte(0x58); | |
2954 emit_operand(dst, src); | |
2955 } | |
2956 | |
2957 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
2958 assert(VM_Version::supports_avx(), ""); | |
2959 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); | |
2960 emit_byte(0x58); | |
2961 emit_byte(0xC0 | encode); | |
2962 } | |
2963 | |
2964 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { | |
2965 assert(VM_Version::supports_avx(), ""); | |
2966 InstructionMark im(this); | |
2967 vex_prefix(dst, nds, src, VEX_SIMD_F3); | |
2968 emit_byte(0x58); | |
2969 emit_operand(dst, src); | |
2970 } | |
2971 | |
2972 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
2973 assert(VM_Version::supports_avx(), ""); | |
2974 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); | |
2975 emit_byte(0x58); | |
2976 emit_byte(0xC0 | encode); | |
2977 } | |
2978 | |
2979 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src) { | |
2980 assert(VM_Version::supports_avx(), ""); | |
2981 InstructionMark im(this); | |
2982 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector | |
2983 emit_byte(0x54); | |
2984 emit_operand(dst, src); | |
2985 } | |
2986 | |
2987 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src) { | |
2988 assert(VM_Version::supports_avx(), ""); | |
2989 InstructionMark im(this); | |
2990 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector | |
2991 emit_byte(0x54); | |
2992 emit_operand(dst, src); | |
2993 } | |
2994 | |
2995 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { | |
2996 assert(VM_Version::supports_avx(), ""); | |
2997 InstructionMark im(this); | |
2998 vex_prefix(dst, nds, src, VEX_SIMD_F2); | |
2999 emit_byte(0x5E); | |
3000 emit_operand(dst, src); | |
3001 } | |
3002 | |
3003 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3004 assert(VM_Version::supports_avx(), ""); | |
3005 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); | |
3006 emit_byte(0x5E); | |
3007 emit_byte(0xC0 | encode); | |
3008 } | |
3009 | |
3010 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { | |
3011 assert(VM_Version::supports_avx(), ""); | |
3012 InstructionMark im(this); | |
3013 vex_prefix(dst, nds, src, VEX_SIMD_F3); | |
3014 emit_byte(0x5E); | |
3015 emit_operand(dst, src); | |
3016 } | |
3017 | |
3018 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3019 assert(VM_Version::supports_avx(), ""); | |
3020 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); | |
3021 emit_byte(0x5E); | |
3022 emit_byte(0xC0 | encode); | |
3023 } | |
3024 | |
3025 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { | |
3026 assert(VM_Version::supports_avx(), ""); | |
3027 InstructionMark im(this); | |
3028 vex_prefix(dst, nds, src, VEX_SIMD_F2); | |
3029 emit_byte(0x59); | |
3030 emit_operand(dst, src); | |
3031 } | |
3032 | |
3033 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3034 assert(VM_Version::supports_avx(), ""); | |
3035 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); | |
3036 emit_byte(0x59); | |
3037 emit_byte(0xC0 | encode); | |
3038 } | |
3039 | |
3040 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { | |
3041 InstructionMark im(this); | |
3042 vex_prefix(dst, nds, src, VEX_SIMD_F3); | |
3043 emit_byte(0x59); | |
3044 emit_operand(dst, src); | |
3045 } | |
3046 | |
3047 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3048 assert(VM_Version::supports_avx(), ""); | |
3049 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); | |
3050 emit_byte(0x59); | |
3051 emit_byte(0xC0 | encode); | |
3052 } | |
3053 | |
3054 | |
3055 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { | |
3056 assert(VM_Version::supports_avx(), ""); | |
3057 InstructionMark im(this); | |
3058 vex_prefix(dst, nds, src, VEX_SIMD_F2); | |
3059 emit_byte(0x5C); | |
3060 emit_operand(dst, src); | |
3061 } | |
3062 | |
3063 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3064 assert(VM_Version::supports_avx(), ""); | |
3065 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); | |
3066 emit_byte(0x5C); | |
3067 emit_byte(0xC0 | encode); | |
3068 } | |
3069 | |
3070 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { | |
3071 assert(VM_Version::supports_avx(), ""); | |
3072 InstructionMark im(this); | |
3073 vex_prefix(dst, nds, src, VEX_SIMD_F3); | |
3074 emit_byte(0x5C); | |
3075 emit_operand(dst, src); | |
3076 } | |
3077 | |
3078 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3079 assert(VM_Version::supports_avx(), ""); | |
3080 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); | |
3081 emit_byte(0x5C); | |
3082 emit_byte(0xC0 | encode); | |
3083 } | |
3084 | |
3085 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src) { | |
3086 assert(VM_Version::supports_avx(), ""); | |
3087 InstructionMark im(this); | |
3088 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector | |
3089 emit_byte(0x57); | |
3090 emit_operand(dst, src); | |
3091 } | |
3092 | |
3093 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src) { | |
3094 assert(VM_Version::supports_avx(), ""); | |
3095 InstructionMark im(this); | |
3096 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector | |
3097 emit_byte(0x57); | |
3098 emit_operand(dst, src); | |
3099 } | |
3100 | |
2939 | 3101 |
2940 #ifndef _LP64 | 3102 #ifndef _LP64 |
2941 // 32bit only pieces of the assembler | 3103 // 32bit only pieces of the assembler |
2942 | 3104 |
2943 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | 3105 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
3392 void Assembler::fyl2x() { | 3554 void Assembler::fyl2x() { |
3393 emit_byte(0xD9); | 3555 emit_byte(0xD9); |
3394 emit_byte(0xF1); | 3556 emit_byte(0xF1); |
3395 } | 3557 } |
3396 | 3558 |
3559 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. | |
3560 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; | |
3561 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. | |
3562 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; | |
3563 | |
3564 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. | |
3565 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
3566 if (pre > 0) { | |
3567 emit_byte(simd_pre[pre]); | |
3568 } | |
3569 if (rex_w) { | |
3570 prefixq(adr, xreg); | |
3571 } else { | |
3572 prefix(adr, xreg); | |
3573 } | |
3574 if (opc > 0) { | |
3575 emit_byte(0x0F); | |
3576 int opc2 = simd_opc[opc]; | |
3577 if (opc2 > 0) { | |
3578 emit_byte(opc2); | |
3579 } | |
3580 } | |
3581 } | |
3582 | |
3583 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
3584 if (pre > 0) { | |
3585 emit_byte(simd_pre[pre]); | |
3586 } | |
3587 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : | |
3588 prefix_and_encode(dst_enc, src_enc); | |
3589 if (opc > 0) { | |
3590 emit_byte(0x0F); | |
3591 int opc2 = simd_opc[opc]; | |
3592 if (opc2 > 0) { | |
3593 emit_byte(opc2); | |
3594 } | |
3595 } | |
3596 return encode; | |
3597 } | |
3598 | |
3599 | |
3600 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) { | |
3601 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { | |
3602 prefix(VEX_3bytes); | |
3603 | |
3604 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); | |
3605 byte1 = (~byte1) & 0xE0; | |
3606 byte1 |= opc; | |
3607 a_byte(byte1); | |
3608 | |
3609 int byte2 = ((~nds_enc) & 0xf) << 3; | |
3610 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre; | |
3611 emit_byte(byte2); | |
3612 } else { | |
3613 prefix(VEX_2bytes); | |
3614 | |
3615 int byte1 = vex_r ? VEX_R : 0; | |
3616 byte1 = (~byte1) & 0x80; | |
3617 byte1 |= ((~nds_enc) & 0xf) << 3; | |
3618 byte1 |= (vector256 ? 4 : 0) | pre; | |
3619 emit_byte(byte1); | |
3620 } | |
3621 } | |
3622 | |
3623 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){ | |
3624 bool vex_r = (xreg_enc >= 8); | |
3625 bool vex_b = adr.base_needs_rex(); | |
3626 bool vex_x = adr.index_needs_rex(); | |
3627 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
3628 } | |
3629 | |
3630 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) { | |
3631 bool vex_r = (dst_enc >= 8); | |
3632 bool vex_b = (src_enc >= 8); | |
3633 bool vex_x = false; | |
3634 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
3635 return (((dst_enc & 7) << 3) | (src_enc & 7)); | |
3636 } | |
3637 | |
3638 | |
3639 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
3640 if (UseAVX > 0) { | |
3641 int xreg_enc = xreg->encoding(); | |
3642 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
3643 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256); | |
3644 } else { | |
3645 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); | |
3646 rex_prefix(adr, xreg, pre, opc, rex_w); | |
3647 } | |
3648 } | |
3649 | |
3650 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
3651 int dst_enc = dst->encoding(); | |
3652 int src_enc = src->encoding(); | |
3653 if (UseAVX > 0) { | |
3654 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
3655 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256); | |
3656 } else { | |
3657 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); | |
3658 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w); | |
3659 } | |
3660 } | |
3397 | 3661 |
3398 #ifndef _LP64 | 3662 #ifndef _LP64 |
3399 | 3663 |
3400 void Assembler::incl(Register dst) { | 3664 void Assembler::incl(Register dst) { |
3401 // Don't use it directly. Use MacroAssembler::incrementl() instead. | 3665 // Don't use it directly. Use MacroAssembler::incrementl() instead. |
3402 emit_byte(0x40 | dst->encoding()); | 3666 emit_byte(0x40 | dst->encoding()); |
3403 } | 3667 } |
3404 | 3668 |
3405 void Assembler::lea(Register dst, Address src) { | 3669 void Assembler::lea(Register dst, Address src) { |
3406 leal(dst, src); | 3670 leal(dst, src); |
3407 } | 3671 } |
3754 } | 4018 } |
3755 } | 4019 } |
3756 } | 4020 } |
3757 } | 4021 } |
3758 | 4022 |
4023 void Assembler::prefixq(Address adr, XMMRegister src) { | |
4024 if (src->encoding() < 8) { | |
4025 if (adr.base_needs_rex()) { | |
4026 if (adr.index_needs_rex()) { | |
4027 prefix(REX_WXB); | |
4028 } else { | |
4029 prefix(REX_WB); | |
4030 } | |
4031 } else { | |
4032 if (adr.index_needs_rex()) { | |
4033 prefix(REX_WX); | |
4034 } else { | |
4035 prefix(REX_W); | |
4036 } | |
4037 } | |
4038 } else { | |
4039 if (adr.base_needs_rex()) { | |
4040 if (adr.index_needs_rex()) { | |
4041 prefix(REX_WRXB); | |
4042 } else { | |
4043 prefix(REX_WRB); | |
4044 } | |
4045 } else { | |
4046 if (adr.index_needs_rex()) { | |
4047 prefix(REX_WRX); | |
4048 } else { | |
4049 prefix(REX_WR); | |
4050 } | |
4051 } | |
4052 } | |
4053 } | |
4054 | |
3759 void Assembler::adcq(Register dst, int32_t imm32) { | 4055 void Assembler::adcq(Register dst, int32_t imm32) { |
3760 (void) prefixq_and_encode(dst->encoding()); | 4056 (void) prefixq_and_encode(dst->encoding()); |
3761 emit_arith(0x81, 0xD0, dst, imm32); | 4057 emit_arith(0x81, 0xD0, dst, imm32); |
3762 } | 4058 } |
3763 | 4059 |
3916 emit_operand(reg, adr); | 4212 emit_operand(reg, adr); |
3917 } | 4213 } |
3918 | 4214 |
3919 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | 4215 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { |
3920 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 4216 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3921 emit_byte(0xF2); | 4217 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2); |
3922 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3923 emit_byte(0x0F); | |
3924 emit_byte(0x2A); | 4218 emit_byte(0x2A); |
3925 emit_byte(0xC0 | encode); | 4219 emit_byte(0xC0 | encode); |
3926 } | 4220 } |
3927 | 4221 |
4222 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { | |
4223 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4224 InstructionMark im(this); | |
4225 simd_prefix_q(dst, dst, src, VEX_SIMD_F2); | |
4226 emit_byte(0x2A); | |
4227 emit_operand(dst, src); | |
4228 } | |
4229 | |
3928 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { | 4230 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { |
3929 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 4231 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
3930 emit_byte(0xF3); | 4232 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3); |
3931 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3932 emit_byte(0x0F); | |
3933 emit_byte(0x2A); | 4233 emit_byte(0x2A); |
3934 emit_byte(0xC0 | encode); | 4234 emit_byte(0xC0 | encode); |
3935 } | 4235 } |
3936 | 4236 |
4237 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { | |
4238 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4239 InstructionMark im(this); | |
4240 simd_prefix_q(dst, dst, src, VEX_SIMD_F3); | |
4241 emit_byte(0x2A); | |
4242 emit_operand(dst, src); | |
4243 } | |
4244 | |
3937 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { | 4245 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { |
3938 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 4246 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3939 emit_byte(0xF2); | 4247 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2); |
3940 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3941 emit_byte(0x0F); | |
3942 emit_byte(0x2C); | 4248 emit_byte(0x2C); |
3943 emit_byte(0xC0 | encode); | 4249 emit_byte(0xC0 | encode); |
3944 } | 4250 } |
3945 | 4251 |
3946 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | 4252 void Assembler::cvttss2siq(Register dst, XMMRegister src) { |
3947 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 4253 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
3948 emit_byte(0xF3); | 4254 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3); |
3949 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3950 emit_byte(0x0F); | |
3951 emit_byte(0x2C); | 4255 emit_byte(0x2C); |
3952 emit_byte(0xC0 | encode); | 4256 emit_byte(0xC0 | encode); |
3953 } | 4257 } |
3954 | 4258 |
3955 void Assembler::decl(Register dst) { | 4259 void Assembler::decl(Register dst) { |
4105 emit_byte(0xC0 | encode); | 4409 emit_byte(0xC0 | encode); |
4106 } | 4410 } |
4107 | 4411 |
4108 void Assembler::movdq(XMMRegister dst, Register src) { | 4412 void Assembler::movdq(XMMRegister dst, Register src) { |
4109 // table D-1 says MMX/SSE2 | 4413 // table D-1 says MMX/SSE2 |
4110 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | 4414 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4111 emit_byte(0x66); | 4415 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66); |
4112 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4113 emit_byte(0x0F); | |
4114 emit_byte(0x6E); | 4416 emit_byte(0x6E); |
4115 emit_byte(0xC0 | encode); | 4417 emit_byte(0xC0 | encode); |
4116 } | 4418 } |
4117 | 4419 |
4118 void Assembler::movdq(Register dst, XMMRegister src) { | 4420 void Assembler::movdq(Register dst, XMMRegister src) { |
4119 // table D-1 says MMX/SSE2 | 4421 // table D-1 says MMX/SSE2 |
4120 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | 4422 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4121 emit_byte(0x66); | |
4122 // swap src/dst to get correct prefix | 4423 // swap src/dst to get correct prefix |
4123 int encode = prefixq_and_encode(src->encoding(), dst->encoding()); | 4424 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66); |
4124 emit_byte(0x0F); | |
4125 emit_byte(0x7E); | 4425 emit_byte(0x7E); |
4126 emit_byte(0xC0 | encode); | 4426 emit_byte(0xC0 | encode); |
4127 } | 4427 } |
4128 | 4428 |
4129 void Assembler::movq(Register dst, Register src) { | 4429 void Assembler::movq(Register dst, Register src) { |
4630 xorl(swap_reg, tmp_reg); | 4930 xorl(swap_reg, tmp_reg); |
4631 if (swap_reg_contains_mark) { | 4931 if (swap_reg_contains_mark) { |
4632 null_check_offset = offset(); | 4932 null_check_offset = offset(); |
4633 } | 4933 } |
4634 movl(tmp_reg, klass_addr); | 4934 movl(tmp_reg, klass_addr); |
4635 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | 4935 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset())); |
4636 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); | 4936 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); |
4637 if (need_tmp_reg) { | 4937 if (need_tmp_reg) { |
4638 pop(tmp_reg); | 4938 pop(tmp_reg); |
4639 } | 4939 } |
4640 if (counters != NULL) { | 4940 if (counters != NULL) { |
4717 if (need_tmp_reg) { | 5017 if (need_tmp_reg) { |
4718 push(tmp_reg); | 5018 push(tmp_reg); |
4719 } | 5019 } |
4720 get_thread(tmp_reg); | 5020 get_thread(tmp_reg); |
4721 movl(swap_reg, klass_addr); | 5021 movl(swap_reg, klass_addr); |
4722 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | 5022 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset())); |
4723 movl(swap_reg, saved_mark_addr); | 5023 movl(swap_reg, saved_mark_addr); |
4724 if (os::is_MP()) { | 5024 if (os::is_MP()) { |
4725 lock(); | 5025 lock(); |
4726 } | 5026 } |
4727 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | 5027 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); |
4755 movl(swap_reg, saved_mark_addr); | 5055 movl(swap_reg, saved_mark_addr); |
4756 if (need_tmp_reg) { | 5056 if (need_tmp_reg) { |
4757 push(tmp_reg); | 5057 push(tmp_reg); |
4758 } | 5058 } |
4759 movl(tmp_reg, klass_addr); | 5059 movl(tmp_reg, klass_addr); |
4760 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | 5060 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset())); |
4761 if (os::is_MP()) { | 5061 if (os::is_MP()) { |
4762 lock(); | 5062 lock(); |
4763 } | 5063 } |
4764 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | 5064 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); |
4765 if (need_tmp_reg) { | 5065 if (need_tmp_reg) { |
5678 | 5978 |
5679 void MacroAssembler::addptr(Address dst, Register src) { | 5979 void MacroAssembler::addptr(Address dst, Register src) { |
5680 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | 5980 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); |
5681 } | 5981 } |
5682 | 5982 |
5983 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { | |
5984 if (reachable(src)) { | |
5985 Assembler::addsd(dst, as_Address(src)); | |
5986 } else { | |
5987 lea(rscratch1, src); | |
5988 Assembler::addsd(dst, Address(rscratch1, 0)); | |
5989 } | |
5990 } | |
5991 | |
5992 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { | |
5993 if (reachable(src)) { | |
5994 addss(dst, as_Address(src)); | |
5995 } else { | |
5996 lea(rscratch1, src); | |
5997 addss(dst, Address(rscratch1, 0)); | |
5998 } | |
5999 } | |
6000 | |
5683 void MacroAssembler::align(int modulus) { | 6001 void MacroAssembler::align(int modulus) { |
5684 if (offset() % modulus != 0) { | 6002 if (offset() % modulus != 0) { |
5685 nop(modulus - (offset() % modulus)); | 6003 nop(modulus - (offset() % modulus)); |
5686 } | 6004 } |
5687 } | 6005 } |
5688 | 6006 |
5689 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { | 6007 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { |
6008 // Used in sign-masking with aligned address. | |
6009 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
5690 if (reachable(src)) { | 6010 if (reachable(src)) { |
5691 andpd(dst, as_Address(src)); | 6011 Assembler::andpd(dst, as_Address(src)); |
5692 } else { | 6012 } else { |
5693 lea(rscratch1, src); | 6013 lea(rscratch1, src); |
5694 andpd(dst, Address(rscratch1, 0)); | 6014 Assembler::andpd(dst, Address(rscratch1, 0)); |
6015 } | |
6016 } | |
6017 | |
6018 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { | |
6019 // Used in sign-masking with aligned address. | |
6020 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
6021 if (reachable(src)) { | |
6022 Assembler::andps(dst, as_Address(src)); | |
6023 } else { | |
6024 lea(rscratch1, src); | |
6025 Assembler::andps(dst, Address(rscratch1, 0)); | |
5695 } | 6026 } |
5696 } | 6027 } |
5697 | 6028 |
5698 void MacroAssembler::andptr(Register dst, int32_t imm32) { | 6029 void MacroAssembler::andptr(Register dst, int32_t imm32) { |
5699 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); | 6030 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); |
6268 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); | 6599 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); |
6269 } | 6600 } |
6270 | 6601 |
6271 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { | 6602 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { |
6272 if (reachable(src)) { | 6603 if (reachable(src)) { |
6273 comisd(dst, as_Address(src)); | 6604 Assembler::comisd(dst, as_Address(src)); |
6274 } else { | 6605 } else { |
6275 lea(rscratch1, src); | 6606 lea(rscratch1, src); |
6276 comisd(dst, Address(rscratch1, 0)); | 6607 Assembler::comisd(dst, Address(rscratch1, 0)); |
6277 } | 6608 } |
6278 } | 6609 } |
6279 | 6610 |
6280 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { | 6611 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { |
6281 if (reachable(src)) { | 6612 if (reachable(src)) { |
6282 comiss(dst, as_Address(src)); | 6613 Assembler::comiss(dst, as_Address(src)); |
6283 } else { | 6614 } else { |
6284 lea(rscratch1, src); | 6615 lea(rscratch1, src); |
6285 comiss(dst, Address(rscratch1, 0)); | 6616 Assembler::comiss(dst, Address(rscratch1, 0)); |
6286 } | 6617 } |
6287 } | 6618 } |
6288 | 6619 |
6289 | 6620 |
6290 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { | 6621 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { |
6362 addl(reg, offset); | 6693 addl(reg, offset); |
6363 } | 6694 } |
6364 | 6695 |
6365 bind (_is_positive); | 6696 bind (_is_positive); |
6366 sarl(reg, shift_value); | 6697 sarl(reg, shift_value); |
6698 } | |
6699 | |
6700 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { | |
6701 if (reachable(src)) { | |
6702 Assembler::divsd(dst, as_Address(src)); | |
6703 } else { | |
6704 lea(rscratch1, src); | |
6705 Assembler::divsd(dst, Address(rscratch1, 0)); | |
6706 } | |
6707 } | |
6708 | |
6709 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { | |
6710 if (reachable(src)) { | |
6711 Assembler::divss(dst, as_Address(src)); | |
6712 } else { | |
6713 lea(rscratch1, src); | |
6714 Assembler::divss(dst, Address(rscratch1, 0)); | |
6715 } | |
6367 } | 6716 } |
6368 | 6717 |
6369 // !defined(COMPILER2) is because of stupid core builds | 6718 // !defined(COMPILER2) is because of stupid core builds |
6370 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) | 6719 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) |
6371 void MacroAssembler::empty_FPU_stack() { | 6720 void MacroAssembler::empty_FPU_stack() { |
6803 | 7152 |
6804 void MacroAssembler::movptr(Address dst, Register src) { | 7153 void MacroAssembler::movptr(Address dst, Register src) { |
6805 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | 7154 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); |
6806 } | 7155 } |
6807 | 7156 |
7157 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { | |
7158 if (reachable(src)) { | |
7159 Assembler::movsd(dst, as_Address(src)); | |
7160 } else { | |
7161 lea(rscratch1, src); | |
7162 Assembler::movsd(dst, Address(rscratch1, 0)); | |
7163 } | |
7164 } | |
7165 | |
6808 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { | 7166 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { |
6809 if (reachable(src)) { | 7167 if (reachable(src)) { |
6810 movss(dst, as_Address(src)); | 7168 Assembler::movss(dst, as_Address(src)); |
6811 } else { | 7169 } else { |
6812 lea(rscratch1, src); | 7170 lea(rscratch1, src); |
6813 movss(dst, Address(rscratch1, 0)); | 7171 Assembler::movss(dst, Address(rscratch1, 0)); |
7172 } | |
7173 } | |
7174 | |
7175 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { | |
7176 if (reachable(src)) { | |
7177 Assembler::mulsd(dst, as_Address(src)); | |
7178 } else { | |
7179 lea(rscratch1, src); | |
7180 Assembler::mulsd(dst, Address(rscratch1, 0)); | |
7181 } | |
7182 } | |
7183 | |
7184 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { | |
7185 if (reachable(src)) { | |
7186 Assembler::mulss(dst, as_Address(src)); | |
7187 } else { | |
7188 lea(rscratch1, src); | |
7189 Assembler::mulss(dst, Address(rscratch1, 0)); | |
6814 } | 7190 } |
6815 } | 7191 } |
6816 | 7192 |
6817 void MacroAssembler::null_check(Register reg, int offset) { | 7193 void MacroAssembler::null_check(Register reg, int offset) { |
6818 if (needs_explicit_null_check(offset)) { | 7194 if (needs_explicit_null_check(offset)) { |
6989 | 7365 |
6990 void MacroAssembler::testl(Register dst, AddressLiteral src) { | 7366 void MacroAssembler::testl(Register dst, AddressLiteral src) { |
6991 assert(reachable(src), "Address should be reachable"); | 7367 assert(reachable(src), "Address should be reachable"); |
6992 testl(dst, as_Address(src)); | 7368 testl(dst, as_Address(src)); |
6993 } | 7369 } |
7370 | |
7371 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { | |
7372 if (reachable(src)) { | |
7373 Assembler::sqrtsd(dst, as_Address(src)); | |
7374 } else { | |
7375 lea(rscratch1, src); | |
7376 Assembler::sqrtsd(dst, Address(rscratch1, 0)); | |
7377 } | |
7378 } | |
7379 | |
7380 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { | |
7381 if (reachable(src)) { | |
7382 Assembler::sqrtss(dst, as_Address(src)); | |
7383 } else { | |
7384 lea(rscratch1, src); | |
7385 Assembler::sqrtss(dst, Address(rscratch1, 0)); | |
7386 } | |
7387 } | |
7388 | |
7389 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { | |
7390 if (reachable(src)) { | |
7391 Assembler::subsd(dst, as_Address(src)); | |
7392 } else { | |
7393 lea(rscratch1, src); | |
7394 Assembler::subsd(dst, Address(rscratch1, 0)); | |
7395 } | |
7396 } | |
7397 | |
7398 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { | |
7399 if (reachable(src)) { | |
7400 Assembler::subss(dst, as_Address(src)); | |
7401 } else { | |
7402 lea(rscratch1, src); | |
7403 Assembler::subss(dst, Address(rscratch1, 0)); | |
7404 } | |
7405 } | |
7406 | |
7407 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { | |
7408 if (reachable(src)) { | |
7409 Assembler::ucomisd(dst, as_Address(src)); | |
7410 } else { | |
7411 lea(rscratch1, src); | |
7412 Assembler::ucomisd(dst, Address(rscratch1, 0)); | |
7413 } | |
7414 } | |
7415 | |
7416 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { | |
7417 if (reachable(src)) { | |
7418 Assembler::ucomiss(dst, as_Address(src)); | |
7419 } else { | |
7420 lea(rscratch1, src); | |
7421 Assembler::ucomiss(dst, Address(rscratch1, 0)); | |
7422 } | |
7423 } | |
7424 | |
7425 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { | |
7426 // Used in sign-bit flipping with aligned address. | |
7427 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
7428 if (reachable(src)) { | |
7429 Assembler::xorpd(dst, as_Address(src)); | |
7430 } else { | |
7431 lea(rscratch1, src); | |
7432 Assembler::xorpd(dst, Address(rscratch1, 0)); | |
7433 } | |
7434 } | |
7435 | |
7436 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { | |
7437 // Used in sign-bit flipping with aligned address. | |
7438 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
7439 if (reachable(src)) { | |
7440 Assembler::xorps(dst, as_Address(src)); | |
7441 } else { | |
7442 lea(rscratch1, src); | |
7443 Assembler::xorps(dst, Address(rscratch1, 0)); | |
7444 } | |
7445 } | |
7446 | |
7447 // AVX 3-operands instructions | |
7448 | |
7449 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7450 if (reachable(src)) { | |
7451 vaddsd(dst, nds, as_Address(src)); | |
7452 } else { | |
7453 lea(rscratch1, src); | |
7454 vaddsd(dst, nds, Address(rscratch1, 0)); | |
7455 } | |
7456 } | |
7457 | |
7458 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7459 if (reachable(src)) { | |
7460 vaddss(dst, nds, as_Address(src)); | |
7461 } else { | |
7462 lea(rscratch1, src); | |
7463 vaddss(dst, nds, Address(rscratch1, 0)); | |
7464 } | |
7465 } | |
7466 | |
7467 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7468 if (reachable(src)) { | |
7469 vandpd(dst, nds, as_Address(src)); | |
7470 } else { | |
7471 lea(rscratch1, src); | |
7472 vandpd(dst, nds, Address(rscratch1, 0)); | |
7473 } | |
7474 } | |
7475 | |
7476 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7477 if (reachable(src)) { | |
7478 vandps(dst, nds, as_Address(src)); | |
7479 } else { | |
7480 lea(rscratch1, src); | |
7481 vandps(dst, nds, Address(rscratch1, 0)); | |
7482 } | |
7483 } | |
7484 | |
7485 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7486 if (reachable(src)) { | |
7487 vdivsd(dst, nds, as_Address(src)); | |
7488 } else { | |
7489 lea(rscratch1, src); | |
7490 vdivsd(dst, nds, Address(rscratch1, 0)); | |
7491 } | |
7492 } | |
7493 | |
7494 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7495 if (reachable(src)) { | |
7496 vdivss(dst, nds, as_Address(src)); | |
7497 } else { | |
7498 lea(rscratch1, src); | |
7499 vdivss(dst, nds, Address(rscratch1, 0)); | |
7500 } | |
7501 } | |
7502 | |
7503 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7504 if (reachable(src)) { | |
7505 vmulsd(dst, nds, as_Address(src)); | |
7506 } else { | |
7507 lea(rscratch1, src); | |
7508 vmulsd(dst, nds, Address(rscratch1, 0)); | |
7509 } | |
7510 } | |
7511 | |
7512 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7513 if (reachable(src)) { | |
7514 vmulss(dst, nds, as_Address(src)); | |
7515 } else { | |
7516 lea(rscratch1, src); | |
7517 vmulss(dst, nds, Address(rscratch1, 0)); | |
7518 } | |
7519 } | |
7520 | |
7521 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7522 if (reachable(src)) { | |
7523 vsubsd(dst, nds, as_Address(src)); | |
7524 } else { | |
7525 lea(rscratch1, src); | |
7526 vsubsd(dst, nds, Address(rscratch1, 0)); | |
7527 } | |
7528 } | |
7529 | |
7530 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7531 if (reachable(src)) { | |
7532 vsubss(dst, nds, as_Address(src)); | |
7533 } else { | |
7534 lea(rscratch1, src); | |
7535 vsubss(dst, nds, Address(rscratch1, 0)); | |
7536 } | |
7537 } | |
7538 | |
7539 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7540 if (reachable(src)) { | |
7541 vxorpd(dst, nds, as_Address(src)); | |
7542 } else { | |
7543 lea(rscratch1, src); | |
7544 vxorpd(dst, nds, Address(rscratch1, 0)); | |
7545 } | |
7546 } | |
7547 | |
7548 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
7549 if (reachable(src)) { | |
7550 vxorps(dst, nds, as_Address(src)); | |
7551 } else { | |
7552 lea(rscratch1, src); | |
7553 vxorps(dst, nds, Address(rscratch1, 0)); | |
7554 } | |
7555 } | |
7556 | |
6994 | 7557 |
6995 ////////////////////////////////////////////////////////////////////////////////// | 7558 ////////////////////////////////////////////////////////////////////////////////// |
6996 #ifndef SERIALGC | 7559 #ifndef SERIALGC |
6997 | 7560 |
6998 void MacroAssembler::g1_write_barrier_pre(Register obj, | 7561 void MacroAssembler::g1_write_barrier_pre(Register obj, |
7683 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } | 8246 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
7684 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } | 8247 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
7685 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } | 8248 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } |
7686 assert(label_nulls <= 1, "at most one NULL in the batch"); | 8249 assert(label_nulls <= 1, "at most one NULL in the batch"); |
7687 | 8250 |
7688 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + | 8251 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); |
7689 Klass::secondary_super_cache_offset_in_bytes()); | 8252 int sco_offset = in_bytes(Klass::super_check_offset_offset()); |
7690 int sco_offset = (klassOopDesc::header_size() * HeapWordSize + | |
7691 Klass::super_check_offset_offset_in_bytes()); | |
7692 Address super_check_offset_addr(super_klass, sco_offset); | 8253 Address super_check_offset_addr(super_klass, sco_offset); |
7693 | 8254 |
7694 // Hacked jcc, which "knows" that L_fallthrough, at least, is in | 8255 // Hacked jcc, which "knows" that L_fallthrough, at least, is in |
7695 // range of a jccb. If this routine grows larger, reconsider at | 8256 // range of a jccb. If this routine grows larger, reconsider at |
7696 // least some of these. | 8257 // least some of these. |
7784 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } | 8345 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
7785 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } | 8346 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
7786 assert(label_nulls <= 1, "at most one NULL in the batch"); | 8347 assert(label_nulls <= 1, "at most one NULL in the batch"); |
7787 | 8348 |
7788 // a couple of useful fields in sub_klass: | 8349 // a couple of useful fields in sub_klass: |
7789 int ss_offset = (klassOopDesc::header_size() * HeapWordSize + | 8350 int ss_offset = in_bytes(Klass::secondary_supers_offset()); |
7790 Klass::secondary_supers_offset_in_bytes()); | 8351 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); |
7791 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + | |
7792 Klass::secondary_super_cache_offset_in_bytes()); | |
7793 Address secondary_supers_addr(sub_klass, ss_offset); | 8352 Address secondary_supers_addr(sub_klass, ss_offset); |
7794 Address super_cache_addr( sub_klass, sc_offset); | 8353 Address super_cache_addr( sub_klass, sc_offset); |
7795 | 8354 |
7796 // Do a linear scan of the secondary super-klass chain. | 8355 // Do a linear scan of the secondary super-klass chain. |
7797 // This code is rarely used, so simplicity is a virtue here. | 8356 // This code is rarely used, so simplicity is a virtue here. |
7873 #undef IS_A_TEMP | 8432 #undef IS_A_TEMP |
7874 | 8433 |
7875 bind(L_fallthrough); | 8434 bind(L_fallthrough); |
7876 } | 8435 } |
7877 | 8436 |
7878 | |
7879 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { | |
7880 ucomisd(dst, as_Address(src)); | |
7881 } | |
7882 | |
7883 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { | |
7884 ucomiss(dst, as_Address(src)); | |
7885 } | |
7886 | |
7887 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { | |
7888 if (reachable(src)) { | |
7889 xorpd(dst, as_Address(src)); | |
7890 } else { | |
7891 lea(rscratch1, src); | |
7892 xorpd(dst, Address(rscratch1, 0)); | |
7893 } | |
7894 } | |
7895 | |
7896 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { | |
7897 if (reachable(src)) { | |
7898 xorps(dst, as_Address(src)); | |
7899 } else { | |
7900 lea(rscratch1, src); | |
7901 xorps(dst, Address(rscratch1, 0)); | |
7902 } | |
7903 } | |
7904 | 8437 |
7905 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { | 8438 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { |
7906 if (VM_Version::supports_cmov()) { | 8439 if (VM_Version::supports_cmov()) { |
7907 cmovl(cc, dst, src); | 8440 cmovl(cc, dst, src); |
7908 } else { | 8441 } else { |
8485 assert (Universe::heap() != NULL, "java heap should be initialized"); | 9018 assert (Universe::heap() != NULL, "java heap should be initialized"); |
8486 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); | 9019 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
8487 if (Universe::narrow_oop_shift() != 0) { | 9020 if (Universe::narrow_oop_shift() != 0) { |
8488 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); | 9021 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
8489 if (LogMinObjAlignmentInBytes == Address::times_8) { | 9022 if (LogMinObjAlignmentInBytes == Address::times_8) { |
8490 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | 9023 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset())); |
8491 } else { | 9024 } else { |
8492 // OK to use shift since we don't need to preserve flags. | 9025 // OK to use shift since we don't need to preserve flags. |
8493 shlq(dst, LogMinObjAlignmentInBytes); | 9026 shlq(dst, LogMinObjAlignmentInBytes); |
8494 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | 9027 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset())); |
8495 } | 9028 } |
8496 } else { | 9029 } else { |
8497 movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | 9030 movq(dst, Address(dst, Klass::prototype_header_offset())); |
8498 } | 9031 } |
8499 } else | 9032 } else |
8500 #endif | 9033 #endif |
8501 { | 9034 { |
8502 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); | 9035 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
8503 movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | 9036 movptr(dst, Address(dst, Klass::prototype_header_offset())); |
8504 } | 9037 } |
8505 } | 9038 } |
8506 | 9039 |
8507 void MacroAssembler::store_klass(Register dst, Register src) { | 9040 void MacroAssembler::store_klass(Register dst, Register src) { |
8508 #ifdef _LP64 | 9041 #ifdef _LP64 |
8759 // which don't need to be loaded through stack. | 9292 // which don't need to be loaded through stack. |
8760 void MacroAssembler::string_indexofC8(Register str1, Register str2, | 9293 void MacroAssembler::string_indexofC8(Register str1, Register str2, |
8761 Register cnt1, Register cnt2, | 9294 Register cnt1, Register cnt2, |
8762 int int_cnt2, Register result, | 9295 int int_cnt2, Register result, |
8763 XMMRegister vec, Register tmp) { | 9296 XMMRegister vec, Register tmp) { |
9297 ShortBranchVerifier sbv(this); | |
8764 assert(UseSSE42Intrinsics, "SSE4.2 is required"); | 9298 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
8765 | 9299 |
8766 // This method uses pcmpestri inxtruction with bound registers | 9300 // This method uses pcmpestri inxtruction with bound registers |
8767 // inputs: | 9301 // inputs: |
8768 // xmm - substring | 9302 // xmm - substring |
8888 addptr(tmp, cnt2); | 9422 addptr(tmp, cnt2); |
8889 movdqu(vec, Address(str2, tmp, Address::times_2, 0)); | 9423 movdqu(vec, Address(str2, tmp, Address::times_2, 0)); |
8890 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d); | 9424 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d); |
8891 } | 9425 } |
8892 // Need to reload strings pointers if not matched whole vector | 9426 // Need to reload strings pointers if not matched whole vector |
8893 jccb(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 | 9427 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 |
8894 addptr(cnt2, 8); | 9428 addptr(cnt2, 8); |
8895 jccb(Assembler::negative, SCAN_SUBSTR); | 9429 jcc(Assembler::negative, SCAN_SUBSTR); |
8896 // Fall through if found full substring | 9430 // Fall through if found full substring |
8897 | 9431 |
8898 } // (int_cnt2 > 8) | 9432 } // (int_cnt2 > 8) |
8899 | 9433 |
8900 bind(RET_FOUND); | 9434 bind(RET_FOUND); |
8909 // Small strings are loaded through stack if they cross page boundary. | 9443 // Small strings are loaded through stack if they cross page boundary. |
8910 void MacroAssembler::string_indexof(Register str1, Register str2, | 9444 void MacroAssembler::string_indexof(Register str1, Register str2, |
8911 Register cnt1, Register cnt2, | 9445 Register cnt1, Register cnt2, |
8912 int int_cnt2, Register result, | 9446 int int_cnt2, Register result, |
8913 XMMRegister vec, Register tmp) { | 9447 XMMRegister vec, Register tmp) { |
9448 ShortBranchVerifier sbv(this); | |
8914 assert(UseSSE42Intrinsics, "SSE4.2 is required"); | 9449 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
8915 // | 9450 // |
8916 // int_cnt2 is length of small (< 8 chars) constant substring | 9451 // int_cnt2 is length of small (< 8 chars) constant substring |
8917 // or (-1) for non constant substring in which case its length | 9452 // or (-1) for non constant substring in which case its length |
8918 // is in cnt2 register. | 9453 // is in cnt2 register. |
9170 | 9705 |
9171 // Compare strings. | 9706 // Compare strings. |
9172 void MacroAssembler::string_compare(Register str1, Register str2, | 9707 void MacroAssembler::string_compare(Register str1, Register str2, |
9173 Register cnt1, Register cnt2, Register result, | 9708 Register cnt1, Register cnt2, Register result, |
9174 XMMRegister vec1) { | 9709 XMMRegister vec1) { |
9710 ShortBranchVerifier sbv(this); | |
9175 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; | 9711 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; |
9176 | 9712 |
9177 // Compute the minimum of the string lengths and the | 9713 // Compute the minimum of the string lengths and the |
9178 // difference of the string lengths (stack). | 9714 // difference of the string lengths (stack). |
9179 // Do the conditional move stuff | 9715 // Do the conditional move stuff |
9306 | 9842 |
9307 // Compare char[] arrays aligned to 4 bytes or substrings. | 9843 // Compare char[] arrays aligned to 4 bytes or substrings. |
9308 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, | 9844 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
9309 Register limit, Register result, Register chr, | 9845 Register limit, Register result, Register chr, |
9310 XMMRegister vec1, XMMRegister vec2) { | 9846 XMMRegister vec1, XMMRegister vec2) { |
9847 ShortBranchVerifier sbv(this); | |
9311 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; | 9848 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; |
9312 | 9849 |
9313 int length_offset = arrayOopDesc::length_offset_in_bytes(); | 9850 int length_offset = arrayOopDesc::length_offset_in_bytes(); |
9314 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | 9851 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); |
9315 | 9852 |
9425 | 9962 |
9426 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") | 9963 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") |
9427 void MacroAssembler::generate_fill(BasicType t, bool aligned, | 9964 void MacroAssembler::generate_fill(BasicType t, bool aligned, |
9428 Register to, Register value, Register count, | 9965 Register to, Register value, Register count, |
9429 Register rtmp, XMMRegister xtmp) { | 9966 Register rtmp, XMMRegister xtmp) { |
9967 ShortBranchVerifier sbv(this); | |
9430 assert_different_registers(to, value, count, rtmp); | 9968 assert_different_registers(to, value, count, rtmp); |
9431 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; | 9969 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; |
9432 Label L_fill_2_bytes, L_fill_4_bytes; | 9970 Label L_fill_2_bytes, L_fill_4_bytes; |
9433 | 9971 |
9434 int shift = -1; | 9972 int shift = -1; |