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7119644: Increase superword's vector size up to 256 bits Summary: Increase vector size up to 256-bits for YMM AVX registers on x86. Reviewed-by: never, twisti, roland
author kvn
date Fri, 15 Jun 2012 01:25:19 -0700
parents 8b0a4867acf0
children 006050192a5a
comparison
equal deleted inserted replaced
6146:eba1d5bce9e8 6179:8c92982cbbc4
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76 76
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
79
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the 77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings. 78 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); 79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); 80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst 81 // Ok so here's the trick FPR1 is really st(0) except in the midst
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); 100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); 101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); 102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); 103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
107 104
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
128
129 // Specify priority of register selection within phases of register 105 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to 106 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine 107 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as 108 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list). 109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, 112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, 113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, 114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H ); 115 FPR6L, FPR6H, FPR7L, FPR7H );
140 116
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
149
150 117
151 //----------Architecture Description Register Classes-------------------------- 118 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in 119 // Several register classes are automatically defined based upon information in
153 // this architecture description. 120 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) 121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 // 125 //
159 // Class for all registers 126 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); 127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers 128 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); 129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95 130 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp, 131 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); 132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers 133 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX); 134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset. 135 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset. 136 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock 137 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX); 138 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX 139 // Class for general registers not including ECX
191 reg_class ebp_reg(EBP); 158 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer 159 // Singleton class for stack pointer
193 reg_class sp_reg(ESP); 160 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer 161 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP); 162 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs 163 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); 164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention 165 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX ); 166 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX ); 167 reg_class ebcx_reg( ECX,EBX );
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); 169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
205 170
206 // Floating point registers. Notice FPR0 is not a choice. 171 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake 172 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack. 173 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); 174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
210 175
211 // make a register class for SSE registers 176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a); 177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
213 178 FPR7L,FPR7H );
214 // make a double register class for SSE2 registers 179
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b, 180 reg_class fp_flt_reg0( FPR1L );
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b ); 181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
217 182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, 183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, 184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
220 FPR7L,FPR7H ); 185
221
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
227
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %} 186 %}
233 187
234 188
235 //----------SOURCE BLOCK------------------------------------------------------- 189 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and 190 // This is a block of C++ code which provides values, functions, and
410 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 364 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
411 emit_d32(cbuf, disp); // Displacement // R/M byte 365 emit_d32(cbuf, disp); // Displacement // R/M byte
412 } 366 }
413 } 367 }
414 368
415 // eRegI ereg, memory mem) %{ // emit_reg_mem 369 // rRegI ereg, memory mem) %{ // emit_reg_mem
416 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) { 370 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
417 // There is no index & no scale, use form without SIB byte 371 // There is no index & no scale, use form without SIB byte
418 if ((index == 0x4) && 372 if ((index == 0x4) &&
419 (scale == 0) && (base != ESP_enc)) { 373 (scale == 0) && (base != ESP_enc)) {
420 // If no displacement, mode is 0x0; unless base is [EBP] 374 // If no displacement, mode is 0x0; unless base is [EBP]
785 offset, Matcher::regName[reg_lo]); 739 offset, Matcher::regName[reg_lo]);
786 } 740 }
787 #endif 741 #endif
788 } 742 }
789 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 743 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
790 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes. 744 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
791 return size+5+offset_size; 745 return size+5+offset_size;
792 } 746 }
793 747
794 748
795 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, 749 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
819 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 773 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
820 } 774 }
821 } 775 }
822 #endif 776 #endif
823 } 777 }
824 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes. 778 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
825 // Only MOVAPS SSE prefix uses 1 byte. 779 // Only MOVAPS SSE prefix uses 1 byte.
826 int sz = 4; 780 int sz = 4;
827 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) && 781 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
828 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3; 782 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
829 return size + sz; 783 return size + sz;
901 } 855 }
902 856
903 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); 857 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
904 } 858 }
905 859
860 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
861 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
862 int src_hi, int dst_hi, uint ireg, outputStream* st);
863
864 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
865 int stack_offset, int reg, uint ireg, outputStream* st);
866
867 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
868 int dst_offset, uint ireg, outputStream* st) {
869 int calc_size = 0;
870 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
871 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
872 switch (ireg) {
873 case Op_VecS:
874 calc_size = 3+src_offset_size + 3+dst_offset_size;
875 break;
876 case Op_VecD:
877 calc_size = 3+src_offset_size + 3+dst_offset_size;
878 src_offset += 4;
879 dst_offset += 4;
880 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
881 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
882 calc_size += 3+src_offset_size + 3+dst_offset_size;
883 break;
884 case Op_VecX:
885 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
886 break;
887 case Op_VecY:
888 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
889 break;
890 default:
891 ShouldNotReachHere();
892 }
893 if (cbuf) {
894 MacroAssembler _masm(cbuf);
895 int offset = __ offset();
896 switch (ireg) {
897 case Op_VecS:
898 __ pushl(Address(rsp, src_offset));
899 __ popl (Address(rsp, dst_offset));
900 break;
901 case Op_VecD:
902 __ pushl(Address(rsp, src_offset));
903 __ popl (Address(rsp, dst_offset));
904 __ pushl(Address(rsp, src_offset+4));
905 __ popl (Address(rsp, dst_offset+4));
906 break;
907 case Op_VecX:
908 __ movdqu(Address(rsp, -16), xmm0);
909 __ movdqu(xmm0, Address(rsp, src_offset));
910 __ movdqu(Address(rsp, dst_offset), xmm0);
911 __ movdqu(xmm0, Address(rsp, -16));
912 break;
913 case Op_VecY:
914 __ vmovdqu(Address(rsp, -32), xmm0);
915 __ vmovdqu(xmm0, Address(rsp, src_offset));
916 __ vmovdqu(Address(rsp, dst_offset), xmm0);
917 __ vmovdqu(xmm0, Address(rsp, -32));
918 break;
919 default:
920 ShouldNotReachHere();
921 }
922 int size = __ offset() - offset;
923 assert(size == calc_size, "incorrect size calculattion");
924 return size;
925 #ifndef PRODUCT
926 } else if (!do_size) {
927 switch (ireg) {
928 case Op_VecS:
929 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
930 "popl [rsp + #%d]",
931 src_offset, dst_offset);
932 break;
933 case Op_VecD:
934 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
935 "popq [rsp + #%d]\n\t"
936 "pushl [rsp + #%d]\n\t"
937 "popq [rsp + #%d]",
938 src_offset, dst_offset, src_offset+4, dst_offset+4);
939 break;
940 case Op_VecX:
941 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
942 "movdqu xmm0, [rsp + #%d]\n\t"
943 "movdqu [rsp + #%d], xmm0\n\t"
944 "movdqu xmm0, [rsp - #16]",
945 src_offset, dst_offset);
946 break;
947 case Op_VecY:
948 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
949 "vmovdqu xmm0, [rsp + #%d]\n\t"
950 "vmovdqu [rsp + #%d], xmm0\n\t"
951 "vmovdqu xmm0, [rsp - #32]",
952 src_offset, dst_offset);
953 break;
954 default:
955 ShouldNotReachHere();
956 }
957 #endif
958 }
959 return calc_size;
960 }
961
906 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { 962 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
907 // Get registers to move 963 // Get registers to move
908 OptoReg::Name src_second = ra_->get_reg_second(in(1)); 964 OptoReg::Name src_second = ra_->get_reg_second(in(1));
909 OptoReg::Name src_first = ra_->get_reg_first(in(1)); 965 OptoReg::Name src_first = ra_->get_reg_first(in(1));
910 OptoReg::Name dst_second = ra_->get_reg_second(this ); 966 OptoReg::Name dst_second = ra_->get_reg_second(this );
920 // Generate spill code! 976 // Generate spill code!
921 int size = 0; 977 int size = 0;
922 978
923 if( src_first == dst_first && src_second == dst_second ) 979 if( src_first == dst_first && src_second == dst_second )
924 return size; // Self copy, no move 980 return size; // Self copy, no move
981
982 if (bottom_type()->isa_vect() != NULL) {
983 uint ireg = ideal_reg();
984 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
985 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
986 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
987 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
988 // mem -> mem
989 int src_offset = ra_->reg2offset(src_first);
990 int dst_offset = ra_->reg2offset(dst_first);
991 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
992 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
993 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
994 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
995 int stack_offset = ra_->reg2offset(dst_first);
996 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
997 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
998 int stack_offset = ra_->reg2offset(src_first);
999 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1000 } else {
1001 ShouldNotReachHere();
1002 }
1003 }
925 1004
926 // -------------------------------------- 1005 // --------------------------------------
927 // Check for mem-mem move. push/pop to move. 1006 // Check for mem-mem move. push/pop to move.
928 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 1007 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
929 if( src_second == dst_first ) { // overlapping stack copy ranges 1008 if( src_second == dst_first ) { // overlapping stack copy ranges
1309 } 1388 }
1310 1389
1311 // This is UltraSparc specific, true just means we have fast l2f conversion 1390 // This is UltraSparc specific, true just means we have fast l2f conversion
1312 const bool Matcher::convL2FSupported(void) { 1391 const bool Matcher::convL2FSupported(void) {
1313 return true; 1392 return true;
1314 }
1315
1316 // Vector width in bytes
1317 const uint Matcher::vector_width_in_bytes(void) {
1318 return UseSSE >= 2 ? 8 : 0;
1319 }
1320
1321 // Vector ideal reg
1322 const uint Matcher::vector_ideal_reg(void) {
1323 return Op_RegD;
1324 } 1393 }
1325 1394
1326 // Is this branch offset short enough that a short branch can be used? 1395 // Is this branch offset short enough that a short branch can be used?
1327 // 1396 //
1328 // NOTE: If the platform does not provide any short branch variants, then 1397 // NOTE: If the platform does not provide any short branch variants, then
1450 // function is used on startup to build the trampoline stubs in generateOptoStub. 1519 // function is used on startup to build the trampoline stubs in generateOptoStub.
1451 // Registers not mentioned will be killed by the VM call in the trampoline, and 1520 // Registers not mentioned will be killed by the VM call in the trampoline, and
1452 // arguments in those registers not be available to the callee. 1521 // arguments in those registers not be available to the callee.
1453 bool Matcher::can_be_java_arg( int reg ) { 1522 bool Matcher::can_be_java_arg( int reg ) {
1454 if( reg == ECX_num || reg == EDX_num ) return true; 1523 if( reg == ECX_num || reg == EDX_num ) return true;
1455 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true; 1524 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1456 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; 1525 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1457 return false; 1526 return false;
1458 } 1527 }
1459 1528
1460 bool Matcher::is_spillable_arg( int reg ) { 1529 bool Matcher::is_spillable_arg( int reg ) {
1563 1632
1564 enc_class SizePrefix %{ 1633 enc_class SizePrefix %{
1565 emit_opcode(cbuf,0x66); 1634 emit_opcode(cbuf,0x66);
1566 %} 1635 %}
1567 1636
1568 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) 1637 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1569 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1638 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1570 %} 1639 %}
1571 1640
1572 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many) 1641 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1573 emit_opcode(cbuf,$opcode$$constant); 1642 emit_opcode(cbuf,$opcode$$constant);
1574 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1643 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1575 %} 1644 %}
1576 1645
1577 enc_class mov_r32_imm0( eRegI dst ) %{ 1646 enc_class mov_r32_imm0( rRegI dst ) %{
1578 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 1647 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1579 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 1648 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1580 %} 1649 %}
1581 1650
1582 enc_class cdq_enc %{ 1651 enc_class cdq_enc %{
1619 // idiv (note: must be emitted by the user of this rule) 1688 // idiv (note: must be emitted by the user of this rule)
1620 // normal: 1689 // normal:
1621 %} 1690 %}
1622 1691
1623 // Dense encoding for older common ops 1692 // Dense encoding for older common ops
1624 enc_class Opc_plus(immI opcode, eRegI reg) %{ 1693 enc_class Opc_plus(immI opcode, rRegI reg) %{
1625 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); 1694 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1626 %} 1695 %}
1627 1696
1628 1697
1629 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension 1698 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1635 else { // If 32-bit immediate 1704 else { // If 32-bit immediate
1636 emit_opcode(cbuf, $primary); 1705 emit_opcode(cbuf, $primary);
1637 } 1706 }
1638 %} 1707 %}
1639 1708
1640 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m 1709 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1641 // Emit primary opcode and set sign-extend bit 1710 // Emit primary opcode and set sign-extend bit
1642 // Check for 8-bit immediate, and set sign extend bit in opcode 1711 // Check for 8-bit immediate, and set sign extend bit in opcode
1643 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1712 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1644 emit_opcode(cbuf, $primary | 0x02); } 1713 emit_opcode(cbuf, $primary | 0x02); }
1645 else { // If 32-bit immediate 1714 else { // If 32-bit immediate
1680 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); 1749 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1681 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); 1750 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1682 else emit_d32(cbuf,con); 1751 else emit_d32(cbuf,con);
1683 %} 1752 %}
1684 1753
1685 enc_class OpcSReg (eRegI dst) %{ // BSWAP 1754 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1686 emit_cc(cbuf, $secondary, $dst$$reg ); 1755 emit_cc(cbuf, $secondary, $dst$$reg );
1687 %} 1756 %}
1688 1757
1689 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP 1758 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1690 int destlo = $dst$$reg; 1759 int destlo = $dst$$reg;
1698 // xchg lo and hi 1767 // xchg lo and hi
1699 emit_opcode(cbuf, 0x87); 1768 emit_opcode(cbuf, 0x87);
1700 emit_rm(cbuf, 0x3, destlo, desthi); 1769 emit_rm(cbuf, 0x3, destlo, desthi);
1701 %} 1770 %}
1702 1771
1703 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ... 1772 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1704 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); 1773 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1705 %} 1774 %}
1706 1775
1707 enc_class enc_cmov(cmpOp cop ) %{ // CMOV 1776 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1708 $$$emit8$primary; 1777 $$$emit8$primary;
1889 // $$$emit8$primary; 1958 // $$$emit8$primary;
1890 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4), 1959 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1891 // runtime_call_Relocation::spec(), RELOC_IMM32 ); 1960 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1892 // %} 1961 // %}
1893 1962
1894 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR 1963 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1895 $$$emit8$primary; 1964 $$$emit8$primary;
1896 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1965 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1897 $$$emit8$shift$$constant; 1966 $$$emit8$shift$$constant;
1898 %} 1967 %}
1899 1968
1900 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate 1969 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1901 // Load immediate does not have a zero or sign extended version 1970 // Load immediate does not have a zero or sign extended version
1902 // for 8-bit immediates 1971 // for 8-bit immediates
1903 emit_opcode(cbuf, 0xB8 + $dst$$reg); 1972 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1904 $$$emit32$src$$constant; 1973 $$$emit32$src$$constant;
1905 %} 1974 %}
1906 1975
1907 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate 1976 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1908 // Load immediate does not have a zero or sign extended version 1977 // Load immediate does not have a zero or sign extended version
1909 // for 8-bit immediates 1978 // for 8-bit immediates
1910 emit_opcode(cbuf, $primary + $dst$$reg); 1979 emit_opcode(cbuf, $primary + $dst$$reg);
1911 $$$emit32$src$$constant; 1980 $$$emit32$src$$constant;
1912 %} 1981 %}
1941 } 2010 }
1942 %} 2011 %}
1943 2012
1944 2013
1945 // Encode a reg-reg copy. If it is useless, then empty encoding. 2014 // Encode a reg-reg copy. If it is useless, then empty encoding.
1946 enc_class enc_Copy( eRegI dst, eRegI src ) %{ 2015 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1947 encode_Copy( cbuf, $dst$$reg, $src$$reg ); 2016 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1948 %} 2017 %}
1949 2018
1950 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{ 2019 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1951 encode_Copy( cbuf, $dst$$reg, $src$$reg ); 2020 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1952 %} 2021 %}
1953 2022
1954 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) 2023 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1955 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2024 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1956 %} 2025 %}
1957 2026
1958 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) 2027 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
1959 $$$emit8$primary; 2028 $$$emit8$primary;
1971 2040
1972 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) 2041 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
1973 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); 2042 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1974 %} 2043 %}
1975 2044
1976 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{ 2045 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
1977 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); 2046 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
1978 %} 2047 %}
1979 2048
1980 enc_class Con32 (immI src) %{ // Con32(storeImmI) 2049 enc_class Con32 (immI src) %{ // Con32(storeImmI)
1981 // Output immediate 2050 // Output immediate
2066 2135
2067 enc_class set_instruction_start( ) %{ 2136 enc_class set_instruction_start( ) %{
2068 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand 2137 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2069 %} 2138 %}
2070 2139
2071 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem 2140 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2072 int reg_encoding = $ereg$$reg; 2141 int reg_encoding = $ereg$$reg;
2073 int base = $mem$$base; 2142 int base = $mem$$base;
2074 int index = $mem$$index; 2143 int index = $mem$$index;
2075 int scale = $mem$$scale; 2144 int scale = $mem$$scale;
2076 int displace = $mem$$disp; 2145 int displace = $mem$$disp;
2130 emit_rm(cbuf, 0x3, r2, r2); 2199 emit_rm(cbuf, 0x3, r2, r2);
2131 %} 2200 %}
2132 2201
2133 // Clone of RegMem but accepts an extra parameter to access each 2202 // Clone of RegMem but accepts an extra parameter to access each
2134 // half of a double in memory; it never needs relocation info. 2203 // half of a double in memory; it never needs relocation info.
2135 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{ 2204 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2136 emit_opcode(cbuf,$opcode$$constant); 2205 emit_opcode(cbuf,$opcode$$constant);
2137 int reg_encoding = $rm_reg$$reg; 2206 int reg_encoding = $rm_reg$$reg;
2138 int base = $mem$$base; 2207 int base = $mem$$base;
2139 int index = $mem$$index; 2208 int index = $mem$$index;
2140 int scale = $mem$$scale; 2209 int scale = $mem$$scale;
2166 int displace = $mem$$disp; 2235 int displace = $mem$$disp;
2167 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 2236 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2168 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 2237 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2169 %} 2238 %}
2170 2239
2171 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea 2240 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2172 int reg_encoding = $dst$$reg; 2241 int reg_encoding = $dst$$reg;
2173 int base = $src0$$reg; // 0xFFFFFFFF indicates no base 2242 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2174 int index = 0x04; // 0x04 indicates no index 2243 int index = 0x04; // 0x04 indicates no index
2175 int scale = 0x00; // 0x00 indicates no scale 2244 int scale = 0x00; // 0x00 indicates no scale
2176 int displace = $src1$$constant; // 0x00 indicates no displacement 2245 int displace = $src1$$constant; // 0x00 indicates no displacement
2177 bool disp_is_oop = false; 2246 bool disp_is_oop = false;
2178 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2247 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2179 %} 2248 %}
2180 2249
2181 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN 2250 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2182 // Compare dst,src 2251 // Compare dst,src
2183 emit_opcode(cbuf,0x3B); 2252 emit_opcode(cbuf,0x3B);
2184 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2253 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2185 // jmp dst < src around move 2254 // jmp dst < src around move
2186 emit_opcode(cbuf,0x7C); 2255 emit_opcode(cbuf,0x7C);
2188 // move dst,src 2257 // move dst,src
2189 emit_opcode(cbuf,0x8B); 2258 emit_opcode(cbuf,0x8B);
2190 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2259 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2191 %} 2260 %}
2192 2261
2193 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX 2262 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2194 // Compare dst,src 2263 // Compare dst,src
2195 emit_opcode(cbuf,0x3B); 2264 emit_opcode(cbuf,0x3B);
2196 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2265 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2197 // jmp dst > src around move 2266 // jmp dst > src around move
2198 emit_opcode(cbuf,0x7F); 2267 emit_opcode(cbuf,0x7F);
2219 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand 2288 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2220 emit_opcode(cbuf,$primary); 2289 emit_opcode(cbuf,$primary);
2221 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2290 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2222 %} 2291 %}
2223 2292
2224 enc_class neg_reg(eRegI dst) %{ 2293 enc_class neg_reg(rRegI dst) %{
2225 // NEG $dst 2294 // NEG $dst
2226 emit_opcode(cbuf,0xF7); 2295 emit_opcode(cbuf,0xF7);
2227 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); 2296 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2228 %} 2297 %}
2229 2298
2249 // ADD $p,$tmp 2318 // ADD $p,$tmp
2250 emit_opcode(cbuf,0x03); 2319 emit_opcode(cbuf,0x03);
2251 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); 2320 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2252 %} 2321 %}
2253 2322
2254 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT 2323 enc_class enc_cmpLTP_mem(rRegI p, rRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2255 int tmpReg = $tmp$$reg; 2324 int tmpReg = $tmp$$reg;
2256 2325
2257 // SUB $p,$q 2326 // SUB $p,$q
2258 emit_opcode(cbuf,0x2B); 2327 emit_opcode(cbuf,0x2B);
2259 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); 2328 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2388 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 2457 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2389 emit_opcode( cbuf, 0xC8+$dst$$reg ); 2458 emit_opcode( cbuf, 0xC8+$dst$$reg );
2390 %} 2459 %}
2391 2460
2392 // Special case for moving an integer register to a stack slot. 2461 // Special case for moving an integer register to a stack slot.
2393 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS 2462 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2394 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); 2463 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2395 %} 2464 %}
2396 2465
2397 // Special case for moving a register to a stack slot. 2466 // Special case for moving a register to a stack slot.
2398 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS 2467 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2399 // Opcode already emitted 2468 // Opcode already emitted
2400 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte 2469 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2401 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 2470 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2402 emit_d32(cbuf, $dst$$disp); // Displacement 2471 emit_d32(cbuf, $dst$$disp); // Displacement
2403 %} 2472 %}
2638 // less_result = 1; 2707 // less_result = 1;
2639 // greater_result = -1; 2708 // greater_result = -1;
2640 // equal_result = 0; 2709 // equal_result = 0;
2641 // nan_result = -1; 2710 // nan_result = -1;
2642 2711
2643 enc_class CmpF_Result(eRegI dst) %{ 2712 enc_class CmpF_Result(rRegI dst) %{
2644 // fnstsw_ax(); 2713 // fnstsw_ax();
2645 emit_opcode( cbuf, 0xDF); 2714 emit_opcode( cbuf, 0xDF);
2646 emit_opcode( cbuf, 0xE0); 2715 emit_opcode( cbuf, 0xE0);
2647 // sahf 2716 // sahf
2648 emit_opcode( cbuf, 0x9E); 2717 emit_opcode( cbuf, 0x9E);
2683 emit_opcode( cbuf, 0x3B ); 2752 emit_opcode( cbuf, 0x3B );
2684 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 2753 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2685 // done: 2754 // done:
2686 %} 2755 %}
2687 2756
2688 enc_class convert_int_long( regL dst, eRegI src ) %{ 2757 enc_class convert_int_long( regL dst, rRegI src ) %{
2689 // mov $dst.lo,$src 2758 // mov $dst.lo,$src
2690 int dst_encoding = $dst$$reg; 2759 int dst_encoding = $dst$$reg;
2691 int src_encoding = $src$$reg; 2760 int src_encoding = $src$$reg;
2692 encode_Copy( cbuf, dst_encoding , src_encoding ); 2761 encode_Copy( cbuf, dst_encoding , src_encoding );
2693 // mov $dst.hi,$src 2762 // mov $dst.hi,$src
2752 // MUL EDX:EAX, src 2821 // MUL EDX:EAX, src
2753 emit_opcode( cbuf, 0xF7 ); 2822 emit_opcode( cbuf, 0xF7 );
2754 emit_rm( cbuf, 0x3, 0x4, $src$$reg); 2823 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2755 %} 2824 %}
2756 2825
2757 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{ 2826 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2758 // Basic idea: lo(result) = lo(x_lo * y_lo) 2827 // Basic idea: lo(result) = lo(x_lo * y_lo)
2759 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 2828 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2760 // MOV $tmp,$src.lo 2829 // MOV $tmp,$src.lo
2761 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); 2830 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2762 // IMUL $tmp,EDX 2831 // IMUL $tmp,EDX
2778 // ADD EDX,ESI 2847 // ADD EDX,ESI
2779 emit_opcode( cbuf, 0x03 ); 2848 emit_opcode( cbuf, 0x03 );
2780 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); 2849 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2781 %} 2850 %}
2782 2851
2783 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{ 2852 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2784 // Basic idea: lo(result) = lo(src * y_lo) 2853 // Basic idea: lo(result) = lo(src * y_lo)
2785 // hi(result) = hi(src * y_lo) + lo(src * y_hi) 2854 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2786 // IMUL $tmp,EDX,$src 2855 // IMUL $tmp,EDX,$src
2787 emit_opcode( cbuf, 0x6B ); 2856 emit_opcode( cbuf, 0x6B );
2788 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 2857 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2834 emit_opcode(cbuf, 0x83); // add SP, #framesize 2903 emit_opcode(cbuf, 0x83); // add SP, #framesize
2835 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 2904 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2836 emit_d8(cbuf, 4*4); 2905 emit_d8(cbuf, 4*4);
2837 %} 2906 %}
2838 2907
2839 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{ 2908 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2840 // MOV $tmp,$src.lo 2909 // MOV $tmp,$src.lo
2841 emit_opcode(cbuf, 0x8B); 2910 emit_opcode(cbuf, 0x8B);
2842 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); 2911 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2843 // OR $tmp,$src.hi 2912 // OR $tmp,$src.hi
2844 emit_opcode(cbuf, 0x0B); 2913 emit_opcode(cbuf, 0x0B);
2855 // CMP $src1.hi,$src2.hi 2924 // CMP $src1.hi,$src2.hi
2856 emit_opcode( cbuf, 0x3B ); 2925 emit_opcode( cbuf, 0x3B );
2857 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); 2926 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2858 %} 2927 %}
2859 2928
2860 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{ 2929 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2861 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits 2930 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2862 emit_opcode( cbuf, 0x3B ); 2931 emit_opcode( cbuf, 0x3B );
2863 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 2932 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2864 // MOV $tmp,$src1.hi 2933 // MOV $tmp,$src1.hi
2865 emit_opcode( cbuf, 0x8B ); 2934 emit_opcode( cbuf, 0x8B );
2867 // SBB $tmp,$src2.hi\t! Compute flags for long compare 2936 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2868 emit_opcode( cbuf, 0x1B ); 2937 emit_opcode( cbuf, 0x1B );
2869 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); 2938 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2870 %} 2939 %}
2871 2940
2872 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{ 2941 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2873 // XOR $tmp,$tmp 2942 // XOR $tmp,$tmp
2874 emit_opcode(cbuf,0x33); // XOR 2943 emit_opcode(cbuf,0x33); // XOR
2875 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); 2944 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2876 // CMP $tmp,$src.lo 2945 // CMP $tmp,$src.lo
2877 emit_opcode( cbuf, 0x3B ); 2946 emit_opcode( cbuf, 0x3B );
3760 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; 3829 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3761 3830
3762 // in SSE2+ mode we want to keep the FPU stack clean so pretend 3831 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3763 // that C functions return float and double results in XMM0. 3832 // that C functions return float and double results in XMM0.
3764 if( ideal_reg == Op_RegD && UseSSE>=2 ) 3833 if( ideal_reg == Op_RegD && UseSSE>=2 )
3765 return OptoRegPair(XMM0b_num,XMM0a_num); 3834 return OptoRegPair(XMM0b_num,XMM0_num);
3766 if( ideal_reg == Op_RegF && UseSSE>=2 ) 3835 if( ideal_reg == Op_RegF && UseSSE>=2 )
3767 return OptoRegPair(OptoReg::Bad,XMM0a_num); 3836 return OptoRegPair(OptoReg::Bad,XMM0_num);
3768 3837
3769 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); 3838 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3770 %} 3839 %}
3771 3840
3772 // Location of return values 3841 // Location of return values
3773 return_value %{ 3842 return_value %{
3774 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3843 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3775 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; 3844 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3776 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; 3845 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3777 if( ideal_reg == Op_RegD && UseSSE>=2 ) 3846 if( ideal_reg == Op_RegD && UseSSE>=2 )
3778 return OptoRegPair(XMM0b_num,XMM0a_num); 3847 return OptoRegPair(XMM0b_num,XMM0_num);
3779 if( ideal_reg == Op_RegF && UseSSE>=1 ) 3848 if( ideal_reg == Op_RegF && UseSSE>=1 )
3780 return OptoRegPair(OptoReg::Bad,XMM0a_num); 3849 return OptoRegPair(OptoReg::Bad,XMM0_num);
3781 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); 3850 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3782 %} 3851 %}
3783 3852
3784 %} 3853 %}
3785 3854
4145 interface(CONST_INTER); 4214 interface(CONST_INTER);
4146 %} 4215 %}
4147 4216
4148 // Register Operands 4217 // Register Operands
4149 // Integer Register 4218 // Integer Register
4150 operand eRegI() %{ 4219 operand rRegI() %{
4151 constraint(ALLOC_IN_RC(e_reg)); 4220 constraint(ALLOC_IN_RC(int_reg));
4152 match(RegI); 4221 match(RegI);
4153 match(xRegI); 4222 match(xRegI);
4154 match(eAXRegI); 4223 match(eAXRegI);
4155 match(eBXRegI); 4224 match(eBXRegI);
4156 match(eCXRegI); 4225 match(eCXRegI);
4161 format %{ %} 4230 format %{ %}
4162 interface(REG_INTER); 4231 interface(REG_INTER);
4163 %} 4232 %}
4164 4233
4165 // Subset of Integer Register 4234 // Subset of Integer Register
4166 operand xRegI(eRegI reg) %{ 4235 operand xRegI(rRegI reg) %{
4167 constraint(ALLOC_IN_RC(x_reg)); 4236 constraint(ALLOC_IN_RC(int_x_reg));
4168 match(reg); 4237 match(reg);
4169 match(eAXRegI); 4238 match(eAXRegI);
4170 match(eBXRegI); 4239 match(eBXRegI);
4171 match(eCXRegI); 4240 match(eCXRegI);
4172 match(eDXRegI); 4241 match(eDXRegI);
4177 4246
4178 // Special Registers 4247 // Special Registers
4179 operand eAXRegI(xRegI reg) %{ 4248 operand eAXRegI(xRegI reg) %{
4180 constraint(ALLOC_IN_RC(eax_reg)); 4249 constraint(ALLOC_IN_RC(eax_reg));
4181 match(reg); 4250 match(reg);
4182 match(eRegI); 4251 match(rRegI);
4183 4252
4184 format %{ "EAX" %} 4253 format %{ "EAX" %}
4185 interface(REG_INTER); 4254 interface(REG_INTER);
4186 %} 4255 %}
4187 4256
4188 // Special Registers 4257 // Special Registers
4189 operand eBXRegI(xRegI reg) %{ 4258 operand eBXRegI(xRegI reg) %{
4190 constraint(ALLOC_IN_RC(ebx_reg)); 4259 constraint(ALLOC_IN_RC(ebx_reg));
4191 match(reg); 4260 match(reg);
4192 match(eRegI); 4261 match(rRegI);
4193 4262
4194 format %{ "EBX" %} 4263 format %{ "EBX" %}
4195 interface(REG_INTER); 4264 interface(REG_INTER);
4196 %} 4265 %}
4197 4266
4198 operand eCXRegI(xRegI reg) %{ 4267 operand eCXRegI(xRegI reg) %{
4199 constraint(ALLOC_IN_RC(ecx_reg)); 4268 constraint(ALLOC_IN_RC(ecx_reg));
4200 match(reg); 4269 match(reg);
4201 match(eRegI); 4270 match(rRegI);
4202 4271
4203 format %{ "ECX" %} 4272 format %{ "ECX" %}
4204 interface(REG_INTER); 4273 interface(REG_INTER);
4205 %} 4274 %}
4206 4275
4207 operand eDXRegI(xRegI reg) %{ 4276 operand eDXRegI(xRegI reg) %{
4208 constraint(ALLOC_IN_RC(edx_reg)); 4277 constraint(ALLOC_IN_RC(edx_reg));
4209 match(reg); 4278 match(reg);
4210 match(eRegI); 4279 match(rRegI);
4211 4280
4212 format %{ "EDX" %} 4281 format %{ "EDX" %}
4213 interface(REG_INTER); 4282 interface(REG_INTER);
4214 %} 4283 %}
4215 4284
4216 operand eDIRegI(xRegI reg) %{ 4285 operand eDIRegI(xRegI reg) %{
4217 constraint(ALLOC_IN_RC(edi_reg)); 4286 constraint(ALLOC_IN_RC(edi_reg));
4218 match(reg); 4287 match(reg);
4219 match(eRegI); 4288 match(rRegI);
4220 4289
4221 format %{ "EDI" %} 4290 format %{ "EDI" %}
4222 interface(REG_INTER); 4291 interface(REG_INTER);
4223 %} 4292 %}
4224 4293
4261 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg 4330 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4262 // // 4331 // //
4263 operand eSIRegI(xRegI reg) %{ 4332 operand eSIRegI(xRegI reg) %{
4264 constraint(ALLOC_IN_RC(esi_reg)); 4333 constraint(ALLOC_IN_RC(esi_reg));
4265 match(reg); 4334 match(reg);
4266 match(eRegI); 4335 match(rRegI);
4267 4336
4268 format %{ "ESI" %} 4337 format %{ "ESI" %}
4269 interface(REG_INTER); 4338 interface(REG_INTER);
4270 %} 4339 %}
4271 4340
4282 format %{ %} 4351 format %{ %}
4283 interface(REG_INTER); 4352 interface(REG_INTER);
4284 %} 4353 %}
4285 4354
4286 operand eRegP() %{ 4355 operand eRegP() %{
4287 constraint(ALLOC_IN_RC(e_reg)); 4356 constraint(ALLOC_IN_RC(int_reg));
4288 match(RegP); 4357 match(RegP);
4289 match(eAXRegP); 4358 match(eAXRegP);
4290 match(eBXRegP); 4359 match(eBXRegP);
4291 match(eCXRegP); 4360 match(eCXRegP);
4292 match(eDIRegP); 4361 match(eDIRegP);
4295 interface(REG_INTER); 4364 interface(REG_INTER);
4296 %} 4365 %}
4297 4366
4298 // On windows95, EBP is not safe to use for implicit null tests. 4367 // On windows95, EBP is not safe to use for implicit null tests.
4299 operand eRegP_no_EBP() %{ 4368 operand eRegP_no_EBP() %{
4300 constraint(ALLOC_IN_RC(e_reg_no_rbp)); 4369 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4301 match(RegP); 4370 match(RegP);
4302 match(eAXRegP); 4371 match(eAXRegP);
4303 match(eBXRegP); 4372 match(eBXRegP);
4304 match(eCXRegP); 4373 match(eCXRegP);
4305 match(eDIRegP); 4374 match(eDIRegP);
4475 %} 4544 %}
4476 4545
4477 // Float register operands 4546 // Float register operands
4478 operand regDPR() %{ 4547 operand regDPR() %{
4479 predicate( UseSSE < 2 ); 4548 predicate( UseSSE < 2 );
4480 constraint(ALLOC_IN_RC(dbl_reg)); 4549 constraint(ALLOC_IN_RC(fp_dbl_reg));
4481 match(RegD); 4550 match(RegD);
4482 match(regDPR1); 4551 match(regDPR1);
4483 match(regDPR2); 4552 match(regDPR2);
4484 format %{ %} 4553 format %{ %}
4485 interface(REG_INTER); 4554 interface(REG_INTER);
4486 %} 4555 %}
4487 4556
4488 operand regDPR1(regDPR reg) %{ 4557 operand regDPR1(regDPR reg) %{
4489 predicate( UseSSE < 2 ); 4558 predicate( UseSSE < 2 );
4490 constraint(ALLOC_IN_RC(dbl_reg0)); 4559 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4491 match(reg); 4560 match(reg);
4492 format %{ "FPR1" %} 4561 format %{ "FPR1" %}
4493 interface(REG_INTER); 4562 interface(REG_INTER);
4494 %} 4563 %}
4495 4564
4496 operand regDPR2(regDPR reg) %{ 4565 operand regDPR2(regDPR reg) %{
4497 predicate( UseSSE < 2 ); 4566 predicate( UseSSE < 2 );
4498 constraint(ALLOC_IN_RC(dbl_reg1)); 4567 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4499 match(reg); 4568 match(reg);
4500 format %{ "FPR2" %} 4569 format %{ "FPR2" %}
4501 interface(REG_INTER); 4570 interface(REG_INTER);
4502 %} 4571 %}
4503 4572
4504 operand regnotDPR1(regDPR reg) %{ 4573 operand regnotDPR1(regDPR reg) %{
4505 predicate( UseSSE < 2 ); 4574 predicate( UseSSE < 2 );
4506 constraint(ALLOC_IN_RC(dbl_notreg0)); 4575 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4507 match(reg); 4576 match(reg);
4508 format %{ %} 4577 format %{ %}
4509 interface(REG_INTER); 4578 interface(REG_INTER);
4510 %} 4579 %}
4511 4580
4512 // XMM Double register operands
4513 operand regD() %{
4514 predicate( UseSSE>=2 );
4515 constraint(ALLOC_IN_RC(xdb_reg));
4516 match(RegD);
4517 match(regD6);
4518 match(regD7);
4519 format %{ %}
4520 interface(REG_INTER);
4521 %}
4522
4523 // XMM6 double register operands
4524 operand regD6(regD reg) %{
4525 predicate( UseSSE>=2 );
4526 constraint(ALLOC_IN_RC(xdb_reg6));
4527 match(reg);
4528 format %{ "XMM6" %}
4529 interface(REG_INTER);
4530 %}
4531
4532 // XMM7 double register operands
4533 operand regD7(regD reg) %{
4534 predicate( UseSSE>=2 );
4535 constraint(ALLOC_IN_RC(xdb_reg7));
4536 match(reg);
4537 format %{ "XMM7" %}
4538 interface(REG_INTER);
4539 %}
4540
4541 // Float register operands 4581 // Float register operands
4542 operand regFPR() %{ 4582 operand regFPR() %{
4543 predicate( UseSSE < 2 ); 4583 predicate( UseSSE < 2 );
4544 constraint(ALLOC_IN_RC(flt_reg)); 4584 constraint(ALLOC_IN_RC(fp_flt_reg));
4545 match(RegF); 4585 match(RegF);
4546 match(regFPR1); 4586 match(regFPR1);
4547 format %{ %} 4587 format %{ %}
4548 interface(REG_INTER); 4588 interface(REG_INTER);
4549 %} 4589 %}
4550 4590
4551 // Float register operands 4591 // Float register operands
4552 operand regFPR1(regFPR reg) %{ 4592 operand regFPR1(regFPR reg) %{
4553 predicate( UseSSE < 2 ); 4593 predicate( UseSSE < 2 );
4554 constraint(ALLOC_IN_RC(flt_reg0)); 4594 constraint(ALLOC_IN_RC(fp_flt_reg0));
4555 match(reg); 4595 match(reg);
4556 format %{ "FPR1" %} 4596 format %{ "FPR1" %}
4557 interface(REG_INTER); 4597 interface(REG_INTER);
4558 %} 4598 %}
4559 4599
4560 // XMM register operands 4600 // XMM Float register operands
4561 operand regF() %{ 4601 operand regF() %{
4562 predicate( UseSSE>=1 ); 4602 predicate( UseSSE>=1 );
4563 constraint(ALLOC_IN_RC(xmm_reg)); 4603 constraint(ALLOC_IN_RC(float_reg));
4564 match(RegF); 4604 match(RegF);
4605 format %{ %}
4606 interface(REG_INTER);
4607 %}
4608
4609 // XMM Double register operands
4610 operand regD() %{
4611 predicate( UseSSE>=2 );
4612 constraint(ALLOC_IN_RC(double_reg));
4613 match(RegD);
4565 format %{ %} 4614 format %{ %}
4566 interface(REG_INTER); 4615 interface(REG_INTER);
4567 %} 4616 %}
4568 4617
4569 4618
4581 %} 4630 %}
4582 %} 4631 %}
4583 4632
4584 // Indirect Memory Operand 4633 // Indirect Memory Operand
4585 operand indirect(eRegP reg) %{ 4634 operand indirect(eRegP reg) %{
4586 constraint(ALLOC_IN_RC(e_reg)); 4635 constraint(ALLOC_IN_RC(int_reg));
4587 match(reg); 4636 match(reg);
4588 4637
4589 format %{ "[$reg]" %} 4638 format %{ "[$reg]" %}
4590 interface(MEMORY_INTER) %{ 4639 interface(MEMORY_INTER) %{
4591 base($reg); 4640 base($reg);
4620 disp($off); 4669 disp($off);
4621 %} 4670 %}
4622 %} 4671 %}
4623 4672
4624 // Indirect Memory Plus Long Offset Operand 4673 // Indirect Memory Plus Long Offset Operand
4625 operand indOffset32X(eRegI reg, immP off) %{ 4674 operand indOffset32X(rRegI reg, immP off) %{
4626 match(AddP off reg); 4675 match(AddP off reg);
4627 4676
4628 format %{ "[$reg + $off]" %} 4677 format %{ "[$reg + $off]" %}
4629 interface(MEMORY_INTER) %{ 4678 interface(MEMORY_INTER) %{
4630 base($reg); 4679 base($reg);
4633 disp($off); 4682 disp($off);
4634 %} 4683 %}
4635 %} 4684 %}
4636 4685
4637 // Indirect Memory Plus Index Register Plus Offset Operand 4686 // Indirect Memory Plus Index Register Plus Offset Operand
4638 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{ 4687 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4639 match(AddP (AddP reg ireg) off); 4688 match(AddP (AddP reg ireg) off);
4640 4689
4641 op_cost(10); 4690 op_cost(10);
4642 format %{"[$reg + $off + $ireg]" %} 4691 format %{"[$reg + $off + $ireg]" %}
4643 interface(MEMORY_INTER) %{ 4692 interface(MEMORY_INTER) %{
4647 disp($off); 4696 disp($off);
4648 %} 4697 %}
4649 %} 4698 %}
4650 4699
4651 // Indirect Memory Plus Index Register Plus Offset Operand 4700 // Indirect Memory Plus Index Register Plus Offset Operand
4652 operand indIndex(eRegP reg, eRegI ireg) %{ 4701 operand indIndex(eRegP reg, rRegI ireg) %{
4653 match(AddP reg ireg); 4702 match(AddP reg ireg);
4654 4703
4655 op_cost(10); 4704 op_cost(10);
4656 format %{"[$reg + $ireg]" %} 4705 format %{"[$reg + $ireg]" %}
4657 interface(MEMORY_INTER) %{ 4706 interface(MEMORY_INTER) %{
4665 // // ------------------------------------------------------------------------- 4714 // // -------------------------------------------------------------------------
4666 // // 486 architecture doesn't support "scale * index + offset" with out a base 4715 // // 486 architecture doesn't support "scale * index + offset" with out a base
4667 // // ------------------------------------------------------------------------- 4716 // // -------------------------------------------------------------------------
4668 // // Scaled Memory Operands 4717 // // Scaled Memory Operands
4669 // // Indirect Memory Times Scale Plus Offset Operand 4718 // // Indirect Memory Times Scale Plus Offset Operand
4670 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{ 4719 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4671 // match(AddP off (LShiftI ireg scale)); 4720 // match(AddP off (LShiftI ireg scale));
4672 // 4721 //
4673 // op_cost(10); 4722 // op_cost(10);
4674 // format %{"[$off + $ireg << $scale]" %} 4723 // format %{"[$off + $ireg << $scale]" %}
4675 // interface(MEMORY_INTER) %{ 4724 // interface(MEMORY_INTER) %{
4679 // disp($off); 4728 // disp($off);
4680 // %} 4729 // %}
4681 // %} 4730 // %}
4682 4731
4683 // Indirect Memory Times Scale Plus Index Register 4732 // Indirect Memory Times Scale Plus Index Register
4684 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{ 4733 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4685 match(AddP reg (LShiftI ireg scale)); 4734 match(AddP reg (LShiftI ireg scale));
4686 4735
4687 op_cost(10); 4736 op_cost(10);
4688 format %{"[$reg + $ireg << $scale]" %} 4737 format %{"[$reg + $ireg << $scale]" %}
4689 interface(MEMORY_INTER) %{ 4738 interface(MEMORY_INTER) %{
4693 disp(0x0); 4742 disp(0x0);
4694 %} 4743 %}
4695 %} 4744 %}
4696 4745
4697 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand 4746 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4698 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{ 4747 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4699 match(AddP (AddP reg (LShiftI ireg scale)) off); 4748 match(AddP (AddP reg (LShiftI ireg scale)) off);
4700 4749
4701 op_cost(10); 4750 op_cost(10);
4702 format %{"[$reg + $off + $ireg << $scale]" %} 4751 format %{"[$reg + $off + $ireg << $scale]" %}
4703 interface(MEMORY_INTER) %{ 4752 interface(MEMORY_INTER) %{
4821 4870
4822 //----------Memory Operands - Win95 Implicit Null Variants---------------- 4871 //----------Memory Operands - Win95 Implicit Null Variants----------------
4823 // Indirect Memory Operand 4872 // Indirect Memory Operand
4824 operand indirect_win95_safe(eRegP_no_EBP reg) 4873 operand indirect_win95_safe(eRegP_no_EBP reg)
4825 %{ 4874 %{
4826 constraint(ALLOC_IN_RC(e_reg)); 4875 constraint(ALLOC_IN_RC(int_reg));
4827 match(reg); 4876 match(reg);
4828 4877
4829 op_cost(100); 4878 op_cost(100);
4830 format %{ "[$reg]" %} 4879 format %{ "[$reg]" %}
4831 interface(MEMORY_INTER) %{ 4880 interface(MEMORY_INTER) %{
4865 disp($off); 4914 disp($off);
4866 %} 4915 %}
4867 %} 4916 %}
4868 4917
4869 // Indirect Memory Plus Index Register Plus Offset Operand 4918 // Indirect Memory Plus Index Register Plus Offset Operand
4870 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off) 4919 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4871 %{ 4920 %{
4872 match(AddP (AddP reg ireg) off); 4921 match(AddP (AddP reg ireg) off);
4873 4922
4874 op_cost(100); 4923 op_cost(100);
4875 format %{"[$reg + $off + $ireg]" %} 4924 format %{"[$reg + $off + $ireg]" %}
4880 disp($off); 4929 disp($off);
4881 %} 4930 %}
4882 %} 4931 %}
4883 4932
4884 // Indirect Memory Times Scale Plus Index Register 4933 // Indirect Memory Times Scale Plus Index Register
4885 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale) 4934 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4886 %{ 4935 %{
4887 match(AddP reg (LShiftI ireg scale)); 4936 match(AddP reg (LShiftI ireg scale));
4888 4937
4889 op_cost(100); 4938 op_cost(100);
4890 format %{"[$reg + $ireg << $scale]" %} 4939 format %{"[$reg + $ireg << $scale]" %}
4895 disp(0x0); 4944 disp(0x0);
4896 %} 4945 %}
4897 %} 4946 %}
4898 4947
4899 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand 4948 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4900 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale) 4949 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4901 %{ 4950 %{
4902 match(AddP (AddP reg (LShiftI ireg scale)) off); 4951 match(AddP (AddP reg (LShiftI ireg scale)) off);
4903 4952
4904 op_cost(100); 4953 op_cost(100);
4905 format %{"[$reg + $off + $ireg << $scale]" %} 4954 format %{"[$reg + $off + $ireg << $scale]" %}
5084 // Then: _long if it's a pair of instructions implementing a long 5133 // Then: _long if it's a pair of instructions implementing a long
5085 // Then: _fat if it requires the big decoder 5134 // Then: _fat if it requires the big decoder
5086 // Or: _mem if it requires the big decoder and a memory unit. 5135 // Or: _mem if it requires the big decoder and a memory unit.
5087 5136
5088 // Integer ALU reg operation 5137 // Integer ALU reg operation
5089 pipe_class ialu_reg(eRegI dst) %{ 5138 pipe_class ialu_reg(rRegI dst) %{
5090 single_instruction; 5139 single_instruction;
5091 dst : S4(write); 5140 dst : S4(write);
5092 dst : S3(read); 5141 dst : S3(read);
5093 DECODE : S0; // any decoder 5142 DECODE : S0; // any decoder
5094 ALU : S3; // any alu 5143 ALU : S3; // any alu
5102 DECODE : S0(2); // any 2 decoders 5151 DECODE : S0(2); // any 2 decoders
5103 ALU : S3(2); // both alus 5152 ALU : S3(2); // both alus
5104 %} 5153 %}
5105 5154
5106 // Integer ALU reg operation using big decoder 5155 // Integer ALU reg operation using big decoder
5107 pipe_class ialu_reg_fat(eRegI dst) %{ 5156 pipe_class ialu_reg_fat(rRegI dst) %{
5108 single_instruction; 5157 single_instruction;
5109 dst : S4(write); 5158 dst : S4(write);
5110 dst : S3(read); 5159 dst : S3(read);
5111 D0 : S0; // big decoder only 5160 D0 : S0; // big decoder only
5112 ALU : S3; // any alu 5161 ALU : S3; // any alu
5120 D0 : S0(2); // big decoder only; twice 5169 D0 : S0(2); // big decoder only; twice
5121 ALU : S3(2); // any 2 alus 5170 ALU : S3(2); // any 2 alus
5122 %} 5171 %}
5123 5172
5124 // Integer ALU reg-reg operation 5173 // Integer ALU reg-reg operation
5125 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{ 5174 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5126 single_instruction; 5175 single_instruction;
5127 dst : S4(write); 5176 dst : S4(write);
5128 src : S3(read); 5177 src : S3(read);
5129 DECODE : S0; // any decoder 5178 DECODE : S0; // any decoder
5130 ALU : S3; // any alu 5179 ALU : S3; // any alu
5138 DECODE : S0(2); // any 2 decoders 5187 DECODE : S0(2); // any 2 decoders
5139 ALU : S3(2); // both alus 5188 ALU : S3(2); // both alus
5140 %} 5189 %}
5141 5190
5142 // Integer ALU reg-reg operation 5191 // Integer ALU reg-reg operation
5143 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{ 5192 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5144 single_instruction; 5193 single_instruction;
5145 dst : S4(write); 5194 dst : S4(write);
5146 src : S3(read); 5195 src : S3(read);
5147 D0 : S0; // big decoder only 5196 D0 : S0; // big decoder only
5148 ALU : S3; // any alu 5197 ALU : S3; // any alu
5156 D0 : S0(2); // big decoder only; twice 5205 D0 : S0(2); // big decoder only; twice
5157 ALU : S3(2); // both alus 5206 ALU : S3(2); // both alus
5158 %} 5207 %}
5159 5208
5160 // Integer ALU reg-mem operation 5209 // Integer ALU reg-mem operation
5161 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{ 5210 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5162 single_instruction; 5211 single_instruction;
5163 dst : S5(write); 5212 dst : S5(write);
5164 mem : S3(read); 5213 mem : S3(read);
5165 D0 : S0; // big decoder only 5214 D0 : S0; // big decoder only
5166 ALU : S4; // any alu 5215 ALU : S4; // any alu
5185 D0 : S0; // big decoder only 5234 D0 : S0; // big decoder only
5186 MEM : S3; // any mem 5235 MEM : S3; // any mem
5187 %} 5236 %}
5188 5237
5189 // Integer Store to Memory 5238 // Integer Store to Memory
5190 pipe_class ialu_mem_reg(memory mem, eRegI src) %{ 5239 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5191 single_instruction; 5240 single_instruction;
5192 mem : S3(read); 5241 mem : S3(read);
5193 src : S5(read); 5242 src : S5(read);
5194 D0 : S0; // big decoder only 5243 D0 : S0; // big decoder only
5195 ALU : S4; // any alu 5244 ALU : S4; // any alu
5214 ALU : S4; // any alu 5263 ALU : S4; // any alu
5215 MEM : S3; 5264 MEM : S3;
5216 %} 5265 %}
5217 5266
5218 // Integer ALU0 reg-reg operation 5267 // Integer ALU0 reg-reg operation
5219 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{ 5268 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5220 single_instruction; 5269 single_instruction;
5221 dst : S4(write); 5270 dst : S4(write);
5222 src : S3(read); 5271 src : S3(read);
5223 D0 : S0; // Big decoder only 5272 D0 : S0; // Big decoder only
5224 ALU0 : S3; // only alu0 5273 ALU0 : S3; // only alu0
5225 %} 5274 %}
5226 5275
5227 // Integer ALU0 reg-mem operation 5276 // Integer ALU0 reg-mem operation
5228 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{ 5277 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5229 single_instruction; 5278 single_instruction;
5230 dst : S5(write); 5279 dst : S5(write);
5231 mem : S3(read); 5280 mem : S3(read);
5232 D0 : S0; // big decoder only 5281 D0 : S0; // big decoder only
5233 ALU0 : S4; // ALU0 only 5282 ALU0 : S4; // ALU0 only
5234 MEM : S3; // any mem 5283 MEM : S3; // any mem
5235 %} 5284 %}
5236 5285
5237 // Integer ALU reg-reg operation 5286 // Integer ALU reg-reg operation
5238 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{ 5287 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5239 single_instruction; 5288 single_instruction;
5240 cr : S4(write); 5289 cr : S4(write);
5241 src1 : S3(read); 5290 src1 : S3(read);
5242 src2 : S3(read); 5291 src2 : S3(read);
5243 DECODE : S0; // any decoder 5292 DECODE : S0; // any decoder
5244 ALU : S3; // any alu 5293 ALU : S3; // any alu
5245 %} 5294 %}
5246 5295
5247 // Integer ALU reg-imm operation 5296 // Integer ALU reg-imm operation
5248 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{ 5297 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5249 single_instruction; 5298 single_instruction;
5250 cr : S4(write); 5299 cr : S4(write);
5251 src1 : S3(read); 5300 src1 : S3(read);
5252 DECODE : S0; // any decoder 5301 DECODE : S0; // any decoder
5253 ALU : S3; // any alu 5302 ALU : S3; // any alu
5254 %} 5303 %}
5255 5304
5256 // Integer ALU reg-mem operation 5305 // Integer ALU reg-mem operation
5257 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{ 5306 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5258 single_instruction; 5307 single_instruction;
5259 cr : S4(write); 5308 cr : S4(write);
5260 src1 : S3(read); 5309 src1 : S3(read);
5261 src2 : S3(read); 5310 src2 : S3(read);
5262 D0 : S0; // big decoder only 5311 D0 : S0; // big decoder only
5263 ALU : S4; // any alu 5312 ALU : S4; // any alu
5264 MEM : S3; 5313 MEM : S3;
5265 %} 5314 %}
5266 5315
5267 // Conditional move reg-reg 5316 // Conditional move reg-reg
5268 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{ 5317 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5269 instruction_count(4); 5318 instruction_count(4);
5270 y : S4(read); 5319 y : S4(read);
5271 q : S3(read); 5320 q : S3(read);
5272 p : S3(read); 5321 p : S3(read);
5273 DECODE : S0(4); // any decoder 5322 DECODE : S0(4); // any decoder
5274 %} 5323 %}
5275 5324
5276 // Conditional move reg-reg 5325 // Conditional move reg-reg
5277 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{ 5326 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5278 single_instruction; 5327 single_instruction;
5279 dst : S4(write); 5328 dst : S4(write);
5280 src : S3(read); 5329 src : S3(read);
5281 cr : S3(read); 5330 cr : S3(read);
5282 DECODE : S0; // any decoder 5331 DECODE : S0; // any decoder
5283 %} 5332 %}
5284 5333
5285 // Conditional move reg-mem 5334 // Conditional move reg-mem
5286 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{ 5335 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5287 single_instruction; 5336 single_instruction;
5288 dst : S4(write); 5337 dst : S4(write);
5289 src : S3(read); 5338 src : S3(read);
5290 cr : S3(read); 5339 cr : S3(read);
5291 DECODE : S0; // any decoder 5340 DECODE : S0; // any decoder
5532 // ins_encode -- A list of encode classes with parameters. The encode class 5581 // ins_encode -- A list of encode classes with parameters. The encode class
5533 // name must have been defined in an 'enc_class' specification 5582 // name must have been defined in an 'enc_class' specification
5534 // in the encode section of the architecture description. 5583 // in the encode section of the architecture description.
5535 5584
5536 //----------BSWAP-Instruction-------------------------------------------------- 5585 //----------BSWAP-Instruction--------------------------------------------------
5537 instruct bytes_reverse_int(eRegI dst) %{ 5586 instruct bytes_reverse_int(rRegI dst) %{
5538 match(Set dst (ReverseBytesI dst)); 5587 match(Set dst (ReverseBytesI dst));
5539 5588
5540 format %{ "BSWAP $dst" %} 5589 format %{ "BSWAP $dst" %}
5541 opcode(0x0F, 0xC8); 5590 opcode(0x0F, 0xC8);
5542 ins_encode( OpcP, OpcSReg(dst) ); 5591 ins_encode( OpcP, OpcSReg(dst) );
5553 ins_cost(125); 5602 ins_cost(125);
5554 ins_encode( bswap_long_bytes(dst) ); 5603 ins_encode( bswap_long_bytes(dst) );
5555 ins_pipe( ialu_reg_reg); 5604 ins_pipe( ialu_reg_reg);
5556 %} 5605 %}
5557 5606
5558 instruct bytes_reverse_unsigned_short(eRegI dst, eFlagsReg cr) %{ 5607 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5559 match(Set dst (ReverseBytesUS dst)); 5608 match(Set dst (ReverseBytesUS dst));
5560 effect(KILL cr); 5609 effect(KILL cr);
5561 5610
5562 format %{ "BSWAP $dst\n\t" 5611 format %{ "BSWAP $dst\n\t"
5563 "SHR $dst,16\n\t" %} 5612 "SHR $dst,16\n\t" %}
5566 __ shrl($dst$$Register, 16); 5615 __ shrl($dst$$Register, 16);
5567 %} 5616 %}
5568 ins_pipe( ialu_reg ); 5617 ins_pipe( ialu_reg );
5569 %} 5618 %}
5570 5619
5571 instruct bytes_reverse_short(eRegI dst, eFlagsReg cr) %{ 5620 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5572 match(Set dst (ReverseBytesS dst)); 5621 match(Set dst (ReverseBytesS dst));
5573 effect(KILL cr); 5622 effect(KILL cr);
5574 5623
5575 format %{ "BSWAP $dst\n\t" 5624 format %{ "BSWAP $dst\n\t"
5576 "SAR $dst,16\n\t" %} 5625 "SAR $dst,16\n\t" %}
5582 %} 5631 %}
5583 5632
5584 5633
5585 //---------- Zeros Count Instructions ------------------------------------------ 5634 //---------- Zeros Count Instructions ------------------------------------------
5586 5635
5587 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{ 5636 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5588 predicate(UseCountLeadingZerosInstruction); 5637 predicate(UseCountLeadingZerosInstruction);
5589 match(Set dst (CountLeadingZerosI src)); 5638 match(Set dst (CountLeadingZerosI src));
5590 effect(KILL cr); 5639 effect(KILL cr);
5591 5640
5592 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} 5641 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5594 __ lzcntl($dst$$Register, $src$$Register); 5643 __ lzcntl($dst$$Register, $src$$Register);
5595 %} 5644 %}
5596 ins_pipe(ialu_reg); 5645 ins_pipe(ialu_reg);
5597 %} 5646 %}
5598 5647
5599 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{ 5648 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5600 predicate(!UseCountLeadingZerosInstruction); 5649 predicate(!UseCountLeadingZerosInstruction);
5601 match(Set dst (CountLeadingZerosI src)); 5650 match(Set dst (CountLeadingZerosI src));
5602 effect(KILL cr); 5651 effect(KILL cr);
5603 5652
5604 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t" 5653 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5619 __ addl(Rdst, BitsPerInt - 1); 5668 __ addl(Rdst, BitsPerInt - 1);
5620 %} 5669 %}
5621 ins_pipe(ialu_reg); 5670 ins_pipe(ialu_reg);
5622 %} 5671 %}
5623 5672
5624 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{ 5673 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5625 predicate(UseCountLeadingZerosInstruction); 5674 predicate(UseCountLeadingZerosInstruction);
5626 match(Set dst (CountLeadingZerosL src)); 5675 match(Set dst (CountLeadingZerosL src));
5627 effect(TEMP dst, KILL cr); 5676 effect(TEMP dst, KILL cr);
5628 5677
5629 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" 5678 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5642 __ bind(done); 5691 __ bind(done);
5643 %} 5692 %}
5644 ins_pipe(ialu_reg); 5693 ins_pipe(ialu_reg);
5645 %} 5694 %}
5646 5695
5647 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{ 5696 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5648 predicate(!UseCountLeadingZerosInstruction); 5697 predicate(!UseCountLeadingZerosInstruction);
5649 match(Set dst (CountLeadingZerosL src)); 5698 match(Set dst (CountLeadingZerosL src));
5650 effect(TEMP dst, KILL cr); 5699 effect(TEMP dst, KILL cr);
5651 5700
5652 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t" 5701 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5678 __ addl(Rdst, BitsPerLong - 1); 5727 __ addl(Rdst, BitsPerLong - 1);
5679 %} 5728 %}
5680 ins_pipe(ialu_reg); 5729 ins_pipe(ialu_reg);
5681 %} 5730 %}
5682 5731
5683 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{ 5732 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5684 match(Set dst (CountTrailingZerosI src)); 5733 match(Set dst (CountTrailingZerosI src));
5685 effect(KILL cr); 5734 effect(KILL cr);
5686 5735
5687 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" 5736 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5688 "JNZ done\n\t" 5737 "JNZ done\n\t"
5697 __ bind(done); 5746 __ bind(done);
5698 %} 5747 %}
5699 ins_pipe(ialu_reg); 5748 ins_pipe(ialu_reg);
5700 %} 5749 %}
5701 5750
5702 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{ 5751 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5703 match(Set dst (CountTrailingZerosL src)); 5752 match(Set dst (CountTrailingZerosL src));
5704 effect(TEMP dst, KILL cr); 5753 effect(TEMP dst, KILL cr);
5705 5754
5706 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" 5755 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5707 "JNZ done\n\t" 5756 "JNZ done\n\t"
5729 %} 5778 %}
5730 5779
5731 5780
5732 //---------- Population Count Instructions ------------------------------------- 5781 //---------- Population Count Instructions -------------------------------------
5733 5782
5734 instruct popCountI(eRegI dst, eRegI src, eFlagsReg cr) %{ 5783 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5735 predicate(UsePopCountInstruction); 5784 predicate(UsePopCountInstruction);
5736 match(Set dst (PopCountI src)); 5785 match(Set dst (PopCountI src));
5737 effect(KILL cr); 5786 effect(KILL cr);
5738 5787
5739 format %{ "POPCNT $dst, $src" %} 5788 format %{ "POPCNT $dst, $src" %}
5741 __ popcntl($dst$$Register, $src$$Register); 5790 __ popcntl($dst$$Register, $src$$Register);
5742 %} 5791 %}
5743 ins_pipe(ialu_reg); 5792 ins_pipe(ialu_reg);
5744 %} 5793 %}
5745 5794
5746 instruct popCountI_mem(eRegI dst, memory mem, eFlagsReg cr) %{ 5795 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5747 predicate(UsePopCountInstruction); 5796 predicate(UsePopCountInstruction);
5748 match(Set dst (PopCountI (LoadI mem))); 5797 match(Set dst (PopCountI (LoadI mem)));
5749 effect(KILL cr); 5798 effect(KILL cr);
5750 5799
5751 format %{ "POPCNT $dst, $mem" %} 5800 format %{ "POPCNT $dst, $mem" %}
5754 %} 5803 %}
5755 ins_pipe(ialu_reg); 5804 ins_pipe(ialu_reg);
5756 %} 5805 %}
5757 5806
5758 // Note: Long.bitCount(long) returns an int. 5807 // Note: Long.bitCount(long) returns an int.
5759 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ 5808 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5760 predicate(UsePopCountInstruction); 5809 predicate(UsePopCountInstruction);
5761 match(Set dst (PopCountL src)); 5810 match(Set dst (PopCountL src));
5762 effect(KILL cr, TEMP tmp, TEMP dst); 5811 effect(KILL cr, TEMP tmp, TEMP dst);
5763 5812
5764 format %{ "POPCNT $dst, $src.lo\n\t" 5813 format %{ "POPCNT $dst, $src.lo\n\t"
5771 %} 5820 %}
5772 ins_pipe(ialu_reg); 5821 ins_pipe(ialu_reg);
5773 %} 5822 %}
5774 5823
5775 // Note: Long.bitCount(long) returns an int. 5824 // Note: Long.bitCount(long) returns an int.
5776 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{ 5825 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5777 predicate(UsePopCountInstruction); 5826 predicate(UsePopCountInstruction);
5778 match(Set dst (PopCountL (LoadL mem))); 5827 match(Set dst (PopCountL (LoadL mem)));
5779 effect(KILL cr, TEMP tmp, TEMP dst); 5828 effect(KILL cr, TEMP tmp, TEMP dst);
5780 5829
5781 format %{ "POPCNT $dst, $mem\n\t" 5830 format %{ "POPCNT $dst, $mem\n\t"
5875 %} 5924 %}
5876 ins_pipe(ialu_reg_mem); 5925 ins_pipe(ialu_reg_mem);
5877 %} 5926 %}
5878 5927
5879 // Load Short (16bit signed) 5928 // Load Short (16bit signed)
5880 instruct loadS(eRegI dst, memory mem) %{ 5929 instruct loadS(rRegI dst, memory mem) %{
5881 match(Set dst (LoadS mem)); 5930 match(Set dst (LoadS mem));
5882 5931
5883 ins_cost(125); 5932 ins_cost(125);
5884 format %{ "MOVSX $dst,$mem\t# short" %} 5933 format %{ "MOVSX $dst,$mem\t# short" %}
5885 5934
5889 5938
5890 ins_pipe(ialu_reg_mem); 5939 ins_pipe(ialu_reg_mem);
5891 %} 5940 %}
5892 5941
5893 // Load Short (16 bit signed) to Byte (8 bit signed) 5942 // Load Short (16 bit signed) to Byte (8 bit signed)
5894 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{ 5943 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5895 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 5944 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5896 5945
5897 ins_cost(125); 5946 ins_cost(125);
5898 format %{ "MOVSX $dst, $mem\t# short -> byte" %} 5947 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5899 ins_encode %{ 5948 ins_encode %{
5920 5969
5921 ins_pipe(ialu_reg_mem); 5970 ins_pipe(ialu_reg_mem);
5922 %} 5971 %}
5923 5972
5924 // Load Unsigned Short/Char (16bit unsigned) 5973 // Load Unsigned Short/Char (16bit unsigned)
5925 instruct loadUS(eRegI dst, memory mem) %{ 5974 instruct loadUS(rRegI dst, memory mem) %{
5926 match(Set dst (LoadUS mem)); 5975 match(Set dst (LoadUS mem));
5927 5976
5928 ins_cost(125); 5977 ins_cost(125);
5929 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} 5978 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5930 5979
5934 5983
5935 ins_pipe(ialu_reg_mem); 5984 ins_pipe(ialu_reg_mem);
5936 %} 5985 %}
5937 5986
5938 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 5987 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5939 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{ 5988 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5940 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 5989 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5941 5990
5942 ins_cost(125); 5991 ins_cost(125);
5943 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %} 5992 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5944 ins_encode %{ 5993 ins_encode %{
5995 %} 6044 %}
5996 ins_pipe(ialu_reg_mem); 6045 ins_pipe(ialu_reg_mem);
5997 %} 6046 %}
5998 6047
5999 // Load Integer 6048 // Load Integer
6000 instruct loadI(eRegI dst, memory mem) %{ 6049 instruct loadI(rRegI dst, memory mem) %{
6001 match(Set dst (LoadI mem)); 6050 match(Set dst (LoadI mem));
6002 6051
6003 ins_cost(125); 6052 ins_cost(125);
6004 format %{ "MOV $dst,$mem\t# int" %} 6053 format %{ "MOV $dst,$mem\t# int" %}
6005 6054
6009 6058
6010 ins_pipe(ialu_reg_mem); 6059 ins_pipe(ialu_reg_mem);
6011 %} 6060 %}
6012 6061
6013 // Load Integer (32 bit signed) to Byte (8 bit signed) 6062 // Load Integer (32 bit signed) to Byte (8 bit signed)
6014 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{ 6063 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6015 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 6064 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6016 6065
6017 ins_cost(125); 6066 ins_cost(125);
6018 format %{ "MOVSX $dst, $mem\t# int -> byte" %} 6067 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6019 ins_encode %{ 6068 ins_encode %{
6021 %} 6070 %}
6022 ins_pipe(ialu_reg_mem); 6071 ins_pipe(ialu_reg_mem);
6023 %} 6072 %}
6024 6073
6025 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) 6074 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6026 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{ 6075 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6027 match(Set dst (AndI (LoadI mem) mask)); 6076 match(Set dst (AndI (LoadI mem) mask));
6028 6077
6029 ins_cost(125); 6078 ins_cost(125);
6030 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %} 6079 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6031 ins_encode %{ 6080 ins_encode %{
6033 %} 6082 %}
6034 ins_pipe(ialu_reg_mem); 6083 ins_pipe(ialu_reg_mem);
6035 %} 6084 %}
6036 6085
6037 // Load Integer (32 bit signed) to Short (16 bit signed) 6086 // Load Integer (32 bit signed) to Short (16 bit signed)
6038 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{ 6087 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6039 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 6088 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6040 6089
6041 ins_cost(125); 6090 ins_cost(125);
6042 format %{ "MOVSX $dst, $mem\t# int -> short" %} 6091 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6043 ins_encode %{ 6092 ins_encode %{
6045 %} 6094 %}
6046 ins_pipe(ialu_reg_mem); 6095 ins_pipe(ialu_reg_mem);
6047 %} 6096 %}
6048 6097
6049 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) 6098 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6050 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{ 6099 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6051 match(Set dst (AndI (LoadI mem) mask)); 6100 match(Set dst (AndI (LoadI mem) mask));
6052 6101
6053 ins_cost(125); 6102 ins_cost(125);
6054 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %} 6103 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6055 ins_encode %{ 6104 ins_encode %{
6206 %} 6255 %}
6207 ins_pipe( pipe_slow ); 6256 ins_pipe( pipe_slow );
6208 %} 6257 %}
6209 6258
6210 // Load Range 6259 // Load Range
6211 instruct loadRange(eRegI dst, memory mem) %{ 6260 instruct loadRange(rRegI dst, memory mem) %{
6212 match(Set dst (LoadRange mem)); 6261 match(Set dst (LoadRange mem));
6213 6262
6214 ins_cost(125); 6263 ins_cost(125);
6215 format %{ "MOV $dst,$mem" %} 6264 format %{ "MOV $dst,$mem" %}
6216 opcode(0x8B); 6265 opcode(0x8B);
6303 ins_encode( OpcP, RMopc_Mem(0x00,mem), 6352 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6304 Pop_Reg_FPR(dst) ); 6353 Pop_Reg_FPR(dst) );
6305 ins_pipe( fpu_reg_mem ); 6354 ins_pipe( fpu_reg_mem );
6306 %} 6355 %}
6307 6356
6308 // Load Aligned Packed Byte to XMM register
6309 instruct loadA8B(regD dst, memory mem) %{
6310 predicate(UseSSE>=1);
6311 match(Set dst (Load8B mem));
6312 ins_cost(125);
6313 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6314 ins_encode %{
6315 __ movq($dst$$XMMRegister, $mem$$Address);
6316 %}
6317 ins_pipe( pipe_slow );
6318 %}
6319
6320 // Load Aligned Packed Short to XMM register
6321 instruct loadA4S(regD dst, memory mem) %{
6322 predicate(UseSSE>=1);
6323 match(Set dst (Load4S mem));
6324 ins_cost(125);
6325 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6326 ins_encode %{
6327 __ movq($dst$$XMMRegister, $mem$$Address);
6328 %}
6329 ins_pipe( pipe_slow );
6330 %}
6331
6332 // Load Aligned Packed Char to XMM register
6333 instruct loadA4C(regD dst, memory mem) %{
6334 predicate(UseSSE>=1);
6335 match(Set dst (Load4C mem));
6336 ins_cost(125);
6337 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6338 ins_encode %{
6339 __ movq($dst$$XMMRegister, $mem$$Address);
6340 %}
6341 ins_pipe( pipe_slow );
6342 %}
6343
6344 // Load Aligned Packed Integer to XMM register
6345 instruct load2IU(regD dst, memory mem) %{
6346 predicate(UseSSE>=1);
6347 match(Set dst (Load2I mem));
6348 ins_cost(125);
6349 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6350 ins_encode %{
6351 __ movq($dst$$XMMRegister, $mem$$Address);
6352 %}
6353 ins_pipe( pipe_slow );
6354 %}
6355
6356 // Load Aligned Packed Single to XMM
6357 instruct loadA2F(regD dst, memory mem) %{
6358 predicate(UseSSE>=1);
6359 match(Set dst (Load2F mem));
6360 ins_cost(145);
6361 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6362 ins_encode %{
6363 __ movq($dst$$XMMRegister, $mem$$Address);
6364 %}
6365 ins_pipe( pipe_slow );
6366 %}
6367
6368 // Load Effective Address 6357 // Load Effective Address
6369 instruct leaP8(eRegP dst, indOffset8 mem) %{ 6358 instruct leaP8(eRegP dst, indOffset8 mem) %{
6370 match(Set dst mem); 6359 match(Set dst mem);
6371 6360
6372 ins_cost(110); 6361 ins_cost(110);
6415 ins_encode( OpcP, RegMem(dst,mem)); 6404 ins_encode( OpcP, RegMem(dst,mem));
6416 ins_pipe( ialu_reg_reg_fat ); 6405 ins_pipe( ialu_reg_reg_fat );
6417 %} 6406 %}
6418 6407
6419 // Load Constant 6408 // Load Constant
6420 instruct loadConI(eRegI dst, immI src) %{ 6409 instruct loadConI(rRegI dst, immI src) %{
6421 match(Set dst src); 6410 match(Set dst src);
6422 6411
6423 format %{ "MOV $dst,$src" %} 6412 format %{ "MOV $dst,$src" %}
6424 ins_encode( LdImmI(dst, src) ); 6413 ins_encode( LdImmI(dst, src) );
6425 ins_pipe( ialu_reg_fat ); 6414 ins_pipe( ialu_reg_fat );
6426 %} 6415 %}
6427 6416
6428 // Load Constant zero 6417 // Load Constant zero
6429 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{ 6418 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6430 match(Set dst src); 6419 match(Set dst src);
6431 effect(KILL cr); 6420 effect(KILL cr);
6432 6421
6433 ins_cost(50); 6422 ins_cost(50);
6434 format %{ "XOR $dst,$dst" %} 6423 format %{ "XOR $dst,$dst" %}
6592 %} 6581 %}
6593 ins_pipe( pipe_slow ); 6582 ins_pipe( pipe_slow );
6594 %} 6583 %}
6595 6584
6596 // Load Stack Slot 6585 // Load Stack Slot
6597 instruct loadSSI(eRegI dst, stackSlotI src) %{ 6586 instruct loadSSI(rRegI dst, stackSlotI src) %{
6598 match(Set dst src); 6587 match(Set dst src);
6599 ins_cost(125); 6588 ins_cost(125);
6600 6589
6601 format %{ "MOV $dst,$src" %} 6590 format %{ "MOV $dst,$src" %}
6602 opcode(0x8B); 6591 opcode(0x8B);
6819 ins_encode( OpcP, RegMem( src, mem ) ); 6808 ins_encode( OpcP, RegMem( src, mem ) );
6820 ins_pipe( ialu_mem_reg ); 6809 ins_pipe( ialu_mem_reg );
6821 %} 6810 %}
6822 6811
6823 // Store Char/Short 6812 // Store Char/Short
6824 instruct storeC(memory mem, eRegI src) %{ 6813 instruct storeC(memory mem, rRegI src) %{
6825 match(Set mem (StoreC mem src)); 6814 match(Set mem (StoreC mem src));
6826 6815
6827 ins_cost(125); 6816 ins_cost(125);
6828 format %{ "MOV16 $mem,$src" %} 6817 format %{ "MOV16 $mem,$src" %}
6829 opcode(0x89, 0x66); 6818 opcode(0x89, 0x66);
6830 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); 6819 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6831 ins_pipe( ialu_mem_reg ); 6820 ins_pipe( ialu_mem_reg );
6832 %} 6821 %}
6833 6822
6834 // Store Integer 6823 // Store Integer
6835 instruct storeI(memory mem, eRegI src) %{ 6824 instruct storeI(memory mem, rRegI src) %{
6836 match(Set mem (StoreI mem src)); 6825 match(Set mem (StoreI mem src));
6837 6826
6838 ins_cost(125); 6827 ins_cost(125);
6839 format %{ "MOV $mem,$src" %} 6828 format %{ "MOV $mem,$src" %}
6840 opcode(0x89); 6829 opcode(0x89);
6974 opcode(0xC6); /* C6 /0 */ 6963 opcode(0xC6); /* C6 /0 */
6975 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); 6964 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6976 ins_pipe( ialu_mem_imm ); 6965 ins_pipe( ialu_mem_imm );
6977 %} 6966 %}
6978 6967
6979 // Store Aligned Packed Byte XMM register to memory
6980 instruct storeA8B(memory mem, regD src) %{
6981 predicate(UseSSE>=1);
6982 match(Set mem (Store8B mem src));
6983 ins_cost(145);
6984 format %{ "MOVQ $mem,$src\t! packed8B" %}
6985 ins_encode %{
6986 __ movq($mem$$Address, $src$$XMMRegister);
6987 %}
6988 ins_pipe( pipe_slow );
6989 %}
6990
6991 // Store Aligned Packed Char/Short XMM register to memory
6992 instruct storeA4C(memory mem, regD src) %{
6993 predicate(UseSSE>=1);
6994 match(Set mem (Store4C mem src));
6995 ins_cost(145);
6996 format %{ "MOVQ $mem,$src\t! packed4C" %}
6997 ins_encode %{
6998 __ movq($mem$$Address, $src$$XMMRegister);
6999 %}
7000 ins_pipe( pipe_slow );
7001 %}
7002
7003 // Store Aligned Packed Integer XMM register to memory
7004 instruct storeA2I(memory mem, regD src) %{
7005 predicate(UseSSE>=1);
7006 match(Set mem (Store2I mem src));
7007 ins_cost(145);
7008 format %{ "MOVQ $mem,$src\t! packed2I" %}
7009 ins_encode %{
7010 __ movq($mem$$Address, $src$$XMMRegister);
7011 %}
7012 ins_pipe( pipe_slow );
7013 %}
7014
7015 // Store CMS card-mark Immediate 6968 // Store CMS card-mark Immediate
7016 instruct storeImmCM(memory mem, immI8 src) %{ 6969 instruct storeImmCM(memory mem, immI8 src) %{
7017 match(Set mem (StoreCM mem src)); 6970 match(Set mem (StoreCM mem src));
7018 6971
7019 ins_cost(150); 6972 ins_cost(150);
7071 __ movflt($mem$$Address, $src$$XMMRegister); 7024 __ movflt($mem$$Address, $src$$XMMRegister);
7072 %} 7025 %}
7073 ins_pipe( pipe_slow ); 7026 ins_pipe( pipe_slow );
7074 %} 7027 %}
7075 7028
7076 // Store Aligned Packed Single Float XMM register to memory
7077 instruct storeA2F(memory mem, regD src) %{
7078 predicate(UseSSE>=1);
7079 match(Set mem (Store2F mem src));
7080 ins_cost(145);
7081 format %{ "MOVQ $mem,$src\t! packed2F" %}
7082 ins_encode %{
7083 __ movq($mem$$Address, $src$$XMMRegister);
7084 %}
7085 ins_pipe( pipe_slow );
7086 %}
7087
7088 // Store Float 7029 // Store Float
7089 instruct storeFPR( memory mem, regFPR1 src) %{ 7030 instruct storeFPR( memory mem, regFPR1 src) %{
7090 predicate(UseSSE==0); 7031 predicate(UseSSE==0);
7091 match(Set mem (StoreF mem src)); 7032 match(Set mem (StoreF mem src));
7092 7033
7144 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); 7085 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7145 ins_pipe( ialu_mem_imm ); 7086 ins_pipe( ialu_mem_imm );
7146 %} 7087 %}
7147 7088
7148 // Store Integer to stack slot 7089 // Store Integer to stack slot
7149 instruct storeSSI(stackSlotI dst, eRegI src) %{ 7090 instruct storeSSI(stackSlotI dst, rRegI src) %{
7150 match(Set dst src); 7091 match(Set dst src);
7151 7092
7152 ins_cost(100); 7093 ins_cost(100);
7153 format %{ "MOV $dst,$src" %} 7094 format %{ "MOV $dst,$src" %}
7154 opcode(0x89); 7095 opcode(0x89);
7269 ins_encode( /*empty encoding*/ ); 7210 ins_encode( /*empty encoding*/ );
7270 ins_cost(0); 7211 ins_cost(0);
7271 ins_pipe(empty); 7212 ins_pipe(empty);
7272 %} 7213 %}
7273 7214
7274 instruct castP2X(eRegI dst, eRegP src ) %{ 7215 instruct castP2X(rRegI dst, eRegP src ) %{
7275 match(Set dst (CastP2X src)); 7216 match(Set dst (CastP2X src));
7276 ins_cost(50); 7217 ins_cost(50);
7277 format %{ "MOV $dst, $src\t# CastP2X" %} 7218 format %{ "MOV $dst, $src\t# CastP2X" %}
7278 ins_encode( enc_Copy( dst, src) ); 7219 ins_encode( enc_Copy( dst, src) );
7279 ins_pipe( ialu_reg_reg ); 7220 ins_pipe( ialu_reg_reg );
7280 %} 7221 %}
7281 7222
7282 //----------Conditional Move--------------------------------------------------- 7223 //----------Conditional Move---------------------------------------------------
7283 // Conditional move 7224 // Conditional move
7284 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, eRegI dst, eRegI src) %{ 7225 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7285 predicate(!VM_Version::supports_cmov() ); 7226 predicate(!VM_Version::supports_cmov() );
7286 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7227 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7287 ins_cost(200); 7228 ins_cost(200);
7288 format %{ "J$cop,us skip\t# signed cmove\n\t" 7229 format %{ "J$cop,us skip\t# signed cmove\n\t"
7289 "MOV $dst,$src\n" 7230 "MOV $dst,$src\n"
7296 __ bind(Lskip); 7237 __ bind(Lskip);
7297 %} 7238 %}
7298 ins_pipe( pipe_cmov_reg ); 7239 ins_pipe( pipe_cmov_reg );
7299 %} 7240 %}
7300 7241
7301 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src) %{ 7242 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7302 predicate(!VM_Version::supports_cmov() ); 7243 predicate(!VM_Version::supports_cmov() );
7303 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7244 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7304 ins_cost(200); 7245 ins_cost(200);
7305 format %{ "J$cop,us skip\t# unsigned cmove\n\t" 7246 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7306 "MOV $dst,$src\n" 7247 "MOV $dst,$src\n"
7313 __ bind(Lskip); 7254 __ bind(Lskip);
7314 %} 7255 %}
7315 ins_pipe( pipe_cmov_reg ); 7256 ins_pipe( pipe_cmov_reg );
7316 %} 7257 %}
7317 7258
7318 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{ 7259 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7319 predicate(VM_Version::supports_cmov() ); 7260 predicate(VM_Version::supports_cmov() );
7320 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7261 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7321 ins_cost(200); 7262 ins_cost(200);
7322 format %{ "CMOV$cop $dst,$src" %} 7263 format %{ "CMOV$cop $dst,$src" %}
7323 opcode(0x0F,0x40); 7264 opcode(0x0F,0x40);
7324 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7265 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7325 ins_pipe( pipe_cmov_reg ); 7266 ins_pipe( pipe_cmov_reg );
7326 %} 7267 %}
7327 7268
7328 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{ 7269 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7329 predicate(VM_Version::supports_cmov() ); 7270 predicate(VM_Version::supports_cmov() );
7330 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7271 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7331 ins_cost(200); 7272 ins_cost(200);
7332 format %{ "CMOV$cop $dst,$src" %} 7273 format %{ "CMOV$cop $dst,$src" %}
7333 opcode(0x0F,0x40); 7274 opcode(0x0F,0x40);
7334 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7275 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7335 ins_pipe( pipe_cmov_reg ); 7276 ins_pipe( pipe_cmov_reg );
7336 %} 7277 %}
7337 7278
7338 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{ 7279 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7339 predicate(VM_Version::supports_cmov() ); 7280 predicate(VM_Version::supports_cmov() );
7340 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7281 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7341 ins_cost(200); 7282 ins_cost(200);
7342 expand %{ 7283 expand %{
7343 cmovI_regU(cop, cr, dst, src); 7284 cmovI_regU(cop, cr, dst, src);
7344 %} 7285 %}
7345 %} 7286 %}
7346 7287
7347 // Conditional move 7288 // Conditional move
7348 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{ 7289 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7349 predicate(VM_Version::supports_cmov() ); 7290 predicate(VM_Version::supports_cmov() );
7350 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 7291 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7351 ins_cost(250); 7292 ins_cost(250);
7352 format %{ "CMOV$cop $dst,$src" %} 7293 format %{ "CMOV$cop $dst,$src" %}
7353 opcode(0x0F,0x40); 7294 opcode(0x0F,0x40);
7354 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7295 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7355 ins_pipe( pipe_cmov_mem ); 7296 ins_pipe( pipe_cmov_mem );
7356 %} 7297 %}
7357 7298
7358 // Conditional move 7299 // Conditional move
7359 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{ 7300 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7360 predicate(VM_Version::supports_cmov() ); 7301 predicate(VM_Version::supports_cmov() );
7361 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 7302 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7362 ins_cost(250); 7303 ins_cost(250);
7363 format %{ "CMOV$cop $dst,$src" %} 7304 format %{ "CMOV$cop $dst,$src" %}
7364 opcode(0x0F,0x40); 7305 opcode(0x0F,0x40);
7365 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7306 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7366 ins_pipe( pipe_cmov_mem ); 7307 ins_pipe( pipe_cmov_mem );
7367 %} 7308 %}
7368 7309
7369 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{ 7310 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7370 predicate(VM_Version::supports_cmov() ); 7311 predicate(VM_Version::supports_cmov() );
7371 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 7312 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7372 ins_cost(250); 7313 ins_cost(250);
7373 expand %{ 7314 expand %{
7374 cmovI_memU(cop, cr, dst, src); 7315 cmovI_memU(cop, cr, dst, src);
7618 %} 7559 %}
7619 7560
7620 //----------Arithmetic Instructions-------------------------------------------- 7561 //----------Arithmetic Instructions--------------------------------------------
7621 //----------Addition Instructions---------------------------------------------- 7562 //----------Addition Instructions----------------------------------------------
7622 // Integer Addition Instructions 7563 // Integer Addition Instructions
7623 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 7564 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7624 match(Set dst (AddI dst src)); 7565 match(Set dst (AddI dst src));
7625 effect(KILL cr); 7566 effect(KILL cr);
7626 7567
7627 size(2); 7568 size(2);
7628 format %{ "ADD $dst,$src" %} 7569 format %{ "ADD $dst,$src" %}
7629 opcode(0x03); 7570 opcode(0x03);
7630 ins_encode( OpcP, RegReg( dst, src) ); 7571 ins_encode( OpcP, RegReg( dst, src) );
7631 ins_pipe( ialu_reg_reg ); 7572 ins_pipe( ialu_reg_reg );
7632 %} 7573 %}
7633 7574
7634 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 7575 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7635 match(Set dst (AddI dst src)); 7576 match(Set dst (AddI dst src));
7636 effect(KILL cr); 7577 effect(KILL cr);
7637 7578
7638 format %{ "ADD $dst,$src" %} 7579 format %{ "ADD $dst,$src" %}
7639 opcode(0x81, 0x00); /* /0 id */ 7580 opcode(0x81, 0x00); /* /0 id */
7640 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 7581 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7641 ins_pipe( ialu_reg ); 7582 ins_pipe( ialu_reg );
7642 %} 7583 %}
7643 7584
7644 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 7585 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7645 predicate(UseIncDec); 7586 predicate(UseIncDec);
7646 match(Set dst (AddI dst src)); 7587 match(Set dst (AddI dst src));
7647 effect(KILL cr); 7588 effect(KILL cr);
7648 7589
7649 size(1); 7590 size(1);
7651 opcode(0x40); /* */ 7592 opcode(0x40); /* */
7652 ins_encode( Opc_plus( primary, dst ) ); 7593 ins_encode( Opc_plus( primary, dst ) );
7653 ins_pipe( ialu_reg ); 7594 ins_pipe( ialu_reg );
7654 %} 7595 %}
7655 7596
7656 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{ 7597 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7657 match(Set dst (AddI src0 src1)); 7598 match(Set dst (AddI src0 src1));
7658 ins_cost(110); 7599 ins_cost(110);
7659 7600
7660 format %{ "LEA $dst,[$src0 + $src1]" %} 7601 format %{ "LEA $dst,[$src0 + $src1]" %}
7661 opcode(0x8D); /* 0x8D /r */ 7602 opcode(0x8D); /* 0x8D /r */
7671 opcode(0x8D); /* 0x8D /r */ 7612 opcode(0x8D); /* 0x8D /r */
7672 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); 7613 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7673 ins_pipe( ialu_reg_reg ); 7614 ins_pipe( ialu_reg_reg );
7674 %} 7615 %}
7675 7616
7676 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{ 7617 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7677 predicate(UseIncDec); 7618 predicate(UseIncDec);
7678 match(Set dst (AddI dst src)); 7619 match(Set dst (AddI dst src));
7679 effect(KILL cr); 7620 effect(KILL cr);
7680 7621
7681 size(1); 7622 size(1);
7683 opcode(0x48); /* */ 7624 opcode(0x48); /* */
7684 ins_encode( Opc_plus( primary, dst ) ); 7625 ins_encode( Opc_plus( primary, dst ) );
7685 ins_pipe( ialu_reg ); 7626 ins_pipe( ialu_reg );
7686 %} 7627 %}
7687 7628
7688 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{ 7629 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7689 match(Set dst (AddP dst src)); 7630 match(Set dst (AddP dst src));
7690 effect(KILL cr); 7631 effect(KILL cr);
7691 7632
7692 size(2); 7633 size(2);
7693 format %{ "ADD $dst,$src" %} 7634 format %{ "ADD $dst,$src" %}
7705 // ins_encode( RegImm( dst, src) ); 7646 // ins_encode( RegImm( dst, src) );
7706 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 7647 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7707 ins_pipe( ialu_reg ); 7648 ins_pipe( ialu_reg );
7708 %} 7649 %}
7709 7650
7710 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 7651 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7711 match(Set dst (AddI dst (LoadI src))); 7652 match(Set dst (AddI dst (LoadI src)));
7712 effect(KILL cr); 7653 effect(KILL cr);
7713 7654
7714 ins_cost(125); 7655 ins_cost(125);
7715 format %{ "ADD $dst,$src" %} 7656 format %{ "ADD $dst,$src" %}
7716 opcode(0x03); 7657 opcode(0x03);
7717 ins_encode( OpcP, RegMem( dst, src) ); 7658 ins_encode( OpcP, RegMem( dst, src) );
7718 ins_pipe( ialu_reg_mem ); 7659 ins_pipe( ialu_reg_mem );
7719 %} 7660 %}
7720 7661
7721 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 7662 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7722 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7663 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7723 effect(KILL cr); 7664 effect(KILL cr);
7724 7665
7725 ins_cost(150); 7666 ins_cost(150);
7726 format %{ "ADD $dst,$src" %} 7667 format %{ "ADD $dst,$src" %}
7778 format %{ "#castPP of $dst" %} 7719 format %{ "#castPP of $dst" %}
7779 ins_encode( /*empty encoding*/ ); 7720 ins_encode( /*empty encoding*/ );
7780 ins_pipe( empty ); 7721 ins_pipe( empty );
7781 %} 7722 %}
7782 7723
7783 instruct castII( eRegI dst ) %{ 7724 instruct castII( rRegI dst ) %{
7784 match(Set dst (CastII dst)); 7725 match(Set dst (CastII dst));
7785 format %{ "#castII of $dst" %} 7726 format %{ "#castII of $dst" %}
7786 ins_encode( /*empty encoding*/ ); 7727 ins_encode( /*empty encoding*/ );
7787 ins_cost(0); 7728 ins_cost(0);
7788 ins_pipe( empty ); 7729 ins_pipe( empty );
7812 ins_pipe( pipe_cmpxchg ); 7753 ins_pipe( pipe_cmpxchg );
7813 %} 7754 %}
7814 7755
7815 // Conditional-store of an int value. 7756 // Conditional-store of an int value.
7816 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. 7757 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7817 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{ 7758 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7818 match(Set cr (StoreIConditional mem (Binary oldval newval))); 7759 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7819 effect(KILL oldval); 7760 effect(KILL oldval);
7820 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} 7761 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7821 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); 7762 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7822 ins_pipe( pipe_cmpxchg ); 7763 ins_pipe( pipe_cmpxchg );
7845 ins_pipe( pipe_cmpxchg ); 7786 ins_pipe( pipe_cmpxchg );
7846 %} 7787 %}
7847 7788
7848 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 7789 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7849 7790
7850 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ 7791 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7851 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 7792 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7852 effect(KILL cr, KILL oldval); 7793 effect(KILL cr, KILL oldval);
7853 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 7794 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7854 "MOV $res,0\n\t" 7795 "MOV $res,0\n\t"
7855 "JNE,s fail\n\t" 7796 "JNE,s fail\n\t"
7858 ins_encode( enc_cmpxchg8(mem_ptr), 7799 ins_encode( enc_cmpxchg8(mem_ptr),
7859 enc_flags_ne_to_boolean(res) ); 7800 enc_flags_ne_to_boolean(res) );
7860 ins_pipe( pipe_cmpxchg ); 7801 ins_pipe( pipe_cmpxchg );
7861 %} 7802 %}
7862 7803
7863 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ 7804 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7864 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 7805 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7865 effect(KILL cr, KILL oldval); 7806 effect(KILL cr, KILL oldval);
7866 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 7807 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7867 "MOV $res,0\n\t" 7808 "MOV $res,0\n\t"
7868 "JNE,s fail\n\t" 7809 "JNE,s fail\n\t"
7870 "fail:" %} 7811 "fail:" %}
7871 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); 7812 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7872 ins_pipe( pipe_cmpxchg ); 7813 ins_pipe( pipe_cmpxchg );
7873 %} 7814 %}
7874 7815
7875 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ 7816 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7876 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 7817 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7877 effect(KILL cr, KILL oldval); 7818 effect(KILL cr, KILL oldval);
7878 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 7819 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7879 "MOV $res,0\n\t" 7820 "MOV $res,0\n\t"
7880 "JNE,s fail\n\t" 7821 "JNE,s fail\n\t"
7884 ins_pipe( pipe_cmpxchg ); 7825 ins_pipe( pipe_cmpxchg );
7885 %} 7826 %}
7886 7827
7887 //----------Subtraction Instructions------------------------------------------- 7828 //----------Subtraction Instructions-------------------------------------------
7888 // Integer Subtraction Instructions 7829 // Integer Subtraction Instructions
7889 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 7830 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7890 match(Set dst (SubI dst src)); 7831 match(Set dst (SubI dst src));
7891 effect(KILL cr); 7832 effect(KILL cr);
7892 7833
7893 size(2); 7834 size(2);
7894 format %{ "SUB $dst,$src" %} 7835 format %{ "SUB $dst,$src" %}
7895 opcode(0x2B); 7836 opcode(0x2B);
7896 ins_encode( OpcP, RegReg( dst, src) ); 7837 ins_encode( OpcP, RegReg( dst, src) );
7897 ins_pipe( ialu_reg_reg ); 7838 ins_pipe( ialu_reg_reg );
7898 %} 7839 %}
7899 7840
7900 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 7841 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7901 match(Set dst (SubI dst src)); 7842 match(Set dst (SubI dst src));
7902 effect(KILL cr); 7843 effect(KILL cr);
7903 7844
7904 format %{ "SUB $dst,$src" %} 7845 format %{ "SUB $dst,$src" %}
7905 opcode(0x81,0x05); /* Opcode 81 /5 */ 7846 opcode(0x81,0x05); /* Opcode 81 /5 */
7906 // ins_encode( RegImm( dst, src) ); 7847 // ins_encode( RegImm( dst, src) );
7907 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 7848 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7908 ins_pipe( ialu_reg ); 7849 ins_pipe( ialu_reg );
7909 %} 7850 %}
7910 7851
7911 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 7852 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7912 match(Set dst (SubI dst (LoadI src))); 7853 match(Set dst (SubI dst (LoadI src)));
7913 effect(KILL cr); 7854 effect(KILL cr);
7914 7855
7915 ins_cost(125); 7856 ins_cost(125);
7916 format %{ "SUB $dst,$src" %} 7857 format %{ "SUB $dst,$src" %}
7917 opcode(0x2B); 7858 opcode(0x2B);
7918 ins_encode( OpcP, RegMem( dst, src) ); 7859 ins_encode( OpcP, RegMem( dst, src) );
7919 ins_pipe( ialu_reg_mem ); 7860 ins_pipe( ialu_reg_mem );
7920 %} 7861 %}
7921 7862
7922 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 7863 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7923 match(Set dst (StoreI dst (SubI (LoadI dst) src))); 7864 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7924 effect(KILL cr); 7865 effect(KILL cr);
7925 7866
7926 ins_cost(150); 7867 ins_cost(150);
7927 format %{ "SUB $dst,$src" %} 7868 format %{ "SUB $dst,$src" %}
7929 ins_encode( OpcP, RegMem( src, dst ) ); 7870 ins_encode( OpcP, RegMem( src, dst ) );
7930 ins_pipe( ialu_mem_reg ); 7871 ins_pipe( ialu_mem_reg );
7931 %} 7872 %}
7932 7873
7933 // Subtract from a pointer 7874 // Subtract from a pointer
7934 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{ 7875 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7935 match(Set dst (AddP dst (SubI zero src))); 7876 match(Set dst (AddP dst (SubI zero src)));
7936 effect(KILL cr); 7877 effect(KILL cr);
7937 7878
7938 size(2); 7879 size(2);
7939 format %{ "SUB $dst,$src" %} 7880 format %{ "SUB $dst,$src" %}
7940 opcode(0x2B); 7881 opcode(0x2B);
7941 ins_encode( OpcP, RegReg( dst, src) ); 7882 ins_encode( OpcP, RegReg( dst, src) );
7942 ins_pipe( ialu_reg_reg ); 7883 ins_pipe( ialu_reg_reg );
7943 %} 7884 %}
7944 7885
7945 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{ 7886 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7946 match(Set dst (SubI zero dst)); 7887 match(Set dst (SubI zero dst));
7947 effect(KILL cr); 7888 effect(KILL cr);
7948 7889
7949 size(2); 7890 size(2);
7950 format %{ "NEG $dst" %} 7891 format %{ "NEG $dst" %}
7955 7896
7956 7897
7957 //----------Multiplication/Division Instructions------------------------------- 7898 //----------Multiplication/Division Instructions-------------------------------
7958 // Integer Multiplication Instructions 7899 // Integer Multiplication Instructions
7959 // Multiply Register 7900 // Multiply Register
7960 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 7901 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7961 match(Set dst (MulI dst src)); 7902 match(Set dst (MulI dst src));
7962 effect(KILL cr); 7903 effect(KILL cr);
7963 7904
7964 size(3); 7905 size(3);
7965 ins_cost(300); 7906 ins_cost(300);
7968 ins_encode( OpcS, OpcP, RegReg( dst, src) ); 7909 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7969 ins_pipe( ialu_reg_reg_alu0 ); 7910 ins_pipe( ialu_reg_reg_alu0 );
7970 %} 7911 %}
7971 7912
7972 // Multiply 32-bit Immediate 7913 // Multiply 32-bit Immediate
7973 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{ 7914 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7974 match(Set dst (MulI src imm)); 7915 match(Set dst (MulI src imm));
7975 effect(KILL cr); 7916 effect(KILL cr);
7976 7917
7977 ins_cost(300); 7918 ins_cost(300);
7978 format %{ "IMUL $dst,$src,$imm" %} 7919 format %{ "IMUL $dst,$src,$imm" %}
8024 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); 7965 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8025 ins_pipe( pipe_slow ); 7966 ins_pipe( pipe_slow );
8026 %} 7967 %}
8027 7968
8028 // Multiply Memory 32-bit Immediate 7969 // Multiply Memory 32-bit Immediate
8029 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{ 7970 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
8030 match(Set dst (MulI (LoadI src) imm)); 7971 match(Set dst (MulI (LoadI src) imm));
8031 effect(KILL cr); 7972 effect(KILL cr);
8032 7973
8033 ins_cost(300); 7974 ins_cost(300);
8034 format %{ "IMUL $dst,$src,$imm" %} 7975 format %{ "IMUL $dst,$src,$imm" %}
8036 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); 7977 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8037 ins_pipe( ialu_reg_mem_alu0 ); 7978 ins_pipe( ialu_reg_mem_alu0 );
8038 %} 7979 %}
8039 7980
8040 // Multiply Memory 7981 // Multiply Memory
8041 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{ 7982 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
8042 match(Set dst (MulI dst (LoadI src))); 7983 match(Set dst (MulI dst (LoadI src)));
8043 effect(KILL cr); 7984 effect(KILL cr);
8044 7985
8045 ins_cost(350); 7986 ins_cost(350);
8046 format %{ "IMUL $dst,$src" %} 7987 format %{ "IMUL $dst,$src" %}
8073 ins_encode( long_uint_multiply(dst, src1) ); 8014 ins_encode( long_uint_multiply(dst, src1) );
8074 ins_pipe( ialu_reg_reg_alu0 ); 8015 ins_pipe( ialu_reg_reg_alu0 );
8075 %} 8016 %}
8076 8017
8077 // Multiply Register Long 8018 // Multiply Register Long
8078 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ 8019 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8079 match(Set dst (MulL dst src)); 8020 match(Set dst (MulL dst src));
8080 effect(KILL cr, TEMP tmp); 8021 effect(KILL cr, TEMP tmp);
8081 ins_cost(4*100+3*400); 8022 ins_cost(4*100+3*400);
8082 // Basic idea: lo(result) = lo(x_lo * y_lo) 8023 // Basic idea: lo(result) = lo(x_lo * y_lo)
8083 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 8024 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8091 ins_encode( long_multiply( dst, src, tmp ) ); 8032 ins_encode( long_multiply( dst, src, tmp ) );
8092 ins_pipe( pipe_slow ); 8033 ins_pipe( pipe_slow );
8093 %} 8034 %}
8094 8035
8095 // Multiply Register Long where the left operand's high 32 bits are zero 8036 // Multiply Register Long where the left operand's high 32 bits are zero
8096 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ 8037 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8097 predicate(is_operand_hi32_zero(n->in(1))); 8038 predicate(is_operand_hi32_zero(n->in(1)));
8098 match(Set dst (MulL dst src)); 8039 match(Set dst (MulL dst src));
8099 effect(KILL cr, TEMP tmp); 8040 effect(KILL cr, TEMP tmp);
8100 ins_cost(2*100+2*400); 8041 ins_cost(2*100+2*400);
8101 // Basic idea: lo(result) = lo(x_lo * y_lo) 8042 // Basic idea: lo(result) = lo(x_lo * y_lo)
8112 %} 8053 %}
8113 ins_pipe( pipe_slow ); 8054 ins_pipe( pipe_slow );
8114 %} 8055 %}
8115 8056
8116 // Multiply Register Long where the right operand's high 32 bits are zero 8057 // Multiply Register Long where the right operand's high 32 bits are zero
8117 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ 8058 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8118 predicate(is_operand_hi32_zero(n->in(2))); 8059 predicate(is_operand_hi32_zero(n->in(2)));
8119 match(Set dst (MulL dst src)); 8060 match(Set dst (MulL dst src));
8120 effect(KILL cr, TEMP tmp); 8061 effect(KILL cr, TEMP tmp);
8121 ins_cost(2*100+2*400); 8062 ins_cost(2*100+2*400);
8122 // Basic idea: lo(result) = lo(x_lo * y_lo) 8063 // Basic idea: lo(result) = lo(x_lo * y_lo)
8148 %} 8089 %}
8149 ins_pipe( pipe_slow ); 8090 ins_pipe( pipe_slow );
8150 %} 8091 %}
8151 8092
8152 // Multiply Register Long by small constant 8093 // Multiply Register Long by small constant
8153 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{ 8094 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8154 match(Set dst (MulL dst src)); 8095 match(Set dst (MulL dst src));
8155 effect(KILL cr, TEMP tmp); 8096 effect(KILL cr, TEMP tmp);
8156 ins_cost(2*100+2*400); 8097 ins_cost(2*100+2*400);
8157 size(12); 8098 size(12);
8158 // Basic idea: lo(result) = lo(src * EAX) 8099 // Basic idea: lo(result) = lo(src * EAX)
8246 ins_encode( long_mod(src1,src2) ); 8187 ins_encode( long_mod(src1,src2) );
8247 ins_pipe( pipe_slow ); 8188 ins_pipe( pipe_slow );
8248 %} 8189 %}
8249 8190
8250 // Divide Register Long (no special case since divisor != -1) 8191 // Divide Register Long (no special case since divisor != -1)
8251 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{ 8192 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8252 match(Set dst (DivL dst imm)); 8193 match(Set dst (DivL dst imm));
8253 effect( TEMP tmp, TEMP tmp2, KILL cr ); 8194 effect( TEMP tmp, TEMP tmp2, KILL cr );
8254 ins_cost(1000); 8195 ins_cost(1000);
8255 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t" 8196 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8256 "XOR $tmp2,$tmp2\n\t" 8197 "XOR $tmp2,$tmp2\n\t"
8317 %} 8258 %}
8318 ins_pipe( pipe_slow ); 8259 ins_pipe( pipe_slow );
8319 %} 8260 %}
8320 8261
8321 // Remainder Register Long (remainder fit into 32 bits) 8262 // Remainder Register Long (remainder fit into 32 bits)
8322 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{ 8263 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8323 match(Set dst (ModL dst imm)); 8264 match(Set dst (ModL dst imm));
8324 effect( TEMP tmp, TEMP tmp2, KILL cr ); 8265 effect( TEMP tmp, TEMP tmp2, KILL cr );
8325 ins_cost(1000); 8266 ins_cost(1000);
8326 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t" 8267 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8327 "CMP $tmp,EDX\n\t" 8268 "CMP $tmp,EDX\n\t"
8385 ins_pipe( pipe_slow ); 8326 ins_pipe( pipe_slow );
8386 %} 8327 %}
8387 8328
8388 // Integer Shift Instructions 8329 // Integer Shift Instructions
8389 // Shift Left by one 8330 // Shift Left by one
8390 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8331 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8391 match(Set dst (LShiftI dst shift)); 8332 match(Set dst (LShiftI dst shift));
8392 effect(KILL cr); 8333 effect(KILL cr);
8393 8334
8394 size(2); 8335 size(2);
8395 format %{ "SHL $dst,$shift" %} 8336 format %{ "SHL $dst,$shift" %}
8397 ins_encode( OpcP, RegOpc( dst ) ); 8338 ins_encode( OpcP, RegOpc( dst ) );
8398 ins_pipe( ialu_reg ); 8339 ins_pipe( ialu_reg );
8399 %} 8340 %}
8400 8341
8401 // Shift Left by 8-bit immediate 8342 // Shift Left by 8-bit immediate
8402 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8343 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8403 match(Set dst (LShiftI dst shift)); 8344 match(Set dst (LShiftI dst shift));
8404 effect(KILL cr); 8345 effect(KILL cr);
8405 8346
8406 size(3); 8347 size(3);
8407 format %{ "SHL $dst,$shift" %} 8348 format %{ "SHL $dst,$shift" %}
8409 ins_encode( RegOpcImm( dst, shift) ); 8350 ins_encode( RegOpcImm( dst, shift) );
8410 ins_pipe( ialu_reg ); 8351 ins_pipe( ialu_reg );
8411 %} 8352 %}
8412 8353
8413 // Shift Left by variable 8354 // Shift Left by variable
8414 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8355 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8415 match(Set dst (LShiftI dst shift)); 8356 match(Set dst (LShiftI dst shift));
8416 effect(KILL cr); 8357 effect(KILL cr);
8417 8358
8418 size(2); 8359 size(2);
8419 format %{ "SHL $dst,$shift" %} 8360 format %{ "SHL $dst,$shift" %}
8421 ins_encode( OpcP, RegOpc( dst ) ); 8362 ins_encode( OpcP, RegOpc( dst ) );
8422 ins_pipe( ialu_reg_reg ); 8363 ins_pipe( ialu_reg_reg );
8423 %} 8364 %}
8424 8365
8425 // Arithmetic shift right by one 8366 // Arithmetic shift right by one
8426 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8367 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8427 match(Set dst (RShiftI dst shift)); 8368 match(Set dst (RShiftI dst shift));
8428 effect(KILL cr); 8369 effect(KILL cr);
8429 8370
8430 size(2); 8371 size(2);
8431 format %{ "SAR $dst,$shift" %} 8372 format %{ "SAR $dst,$shift" %}
8443 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); 8384 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8444 ins_pipe( ialu_mem_imm ); 8385 ins_pipe( ialu_mem_imm );
8445 %} 8386 %}
8446 8387
8447 // Arithmetic Shift Right by 8-bit immediate 8388 // Arithmetic Shift Right by 8-bit immediate
8448 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8389 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8449 match(Set dst (RShiftI dst shift)); 8390 match(Set dst (RShiftI dst shift));
8450 effect(KILL cr); 8391 effect(KILL cr);
8451 8392
8452 size(3); 8393 size(3);
8453 format %{ "SAR $dst,$shift" %} 8394 format %{ "SAR $dst,$shift" %}
8466 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); 8407 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8467 ins_pipe( ialu_mem_imm ); 8408 ins_pipe( ialu_mem_imm );
8468 %} 8409 %}
8469 8410
8470 // Arithmetic Shift Right by variable 8411 // Arithmetic Shift Right by variable
8471 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8412 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8472 match(Set dst (RShiftI dst shift)); 8413 match(Set dst (RShiftI dst shift));
8473 effect(KILL cr); 8414 effect(KILL cr);
8474 8415
8475 size(2); 8416 size(2);
8476 format %{ "SAR $dst,$shift" %} 8417 format %{ "SAR $dst,$shift" %}
8478 ins_encode( OpcP, RegOpc( dst ) ); 8419 ins_encode( OpcP, RegOpc( dst ) );
8479 ins_pipe( ialu_reg_reg ); 8420 ins_pipe( ialu_reg_reg );
8480 %} 8421 %}
8481 8422
8482 // Logical shift right by one 8423 // Logical shift right by one
8483 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8424 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8484 match(Set dst (URShiftI dst shift)); 8425 match(Set dst (URShiftI dst shift));
8485 effect(KILL cr); 8426 effect(KILL cr);
8486 8427
8487 size(2); 8428 size(2);
8488 format %{ "SHR $dst,$shift" %} 8429 format %{ "SHR $dst,$shift" %}
8490 ins_encode( OpcP, RegOpc( dst ) ); 8431 ins_encode( OpcP, RegOpc( dst ) );
8491 ins_pipe( ialu_reg ); 8432 ins_pipe( ialu_reg );
8492 %} 8433 %}
8493 8434
8494 // Logical Shift Right by 8-bit immediate 8435 // Logical Shift Right by 8-bit immediate
8495 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8436 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8496 match(Set dst (URShiftI dst shift)); 8437 match(Set dst (URShiftI dst shift));
8497 effect(KILL cr); 8438 effect(KILL cr);
8498 8439
8499 size(3); 8440 size(3);
8500 format %{ "SHR $dst,$shift" %} 8441 format %{ "SHR $dst,$shift" %}
8504 %} 8445 %}
8505 8446
8506 8447
8507 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. 8448 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8508 // This idiom is used by the compiler for the i2b bytecode. 8449 // This idiom is used by the compiler for the i2b bytecode.
8509 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{ 8450 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8510 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); 8451 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8511 8452
8512 size(3); 8453 size(3);
8513 format %{ "MOVSX $dst,$src :8" %} 8454 format %{ "MOVSX $dst,$src :8" %}
8514 ins_encode %{ 8455 ins_encode %{
8517 ins_pipe(ialu_reg_reg); 8458 ins_pipe(ialu_reg_reg);
8518 %} 8459 %}
8519 8460
8520 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. 8461 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8521 // This idiom is used by the compiler the i2s bytecode. 8462 // This idiom is used by the compiler the i2s bytecode.
8522 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{ 8463 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8523 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); 8464 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8524 8465
8525 size(3); 8466 size(3);
8526 format %{ "MOVSX $dst,$src :16" %} 8467 format %{ "MOVSX $dst,$src :16" %}
8527 ins_encode %{ 8468 ins_encode %{
8530 ins_pipe(ialu_reg_reg); 8471 ins_pipe(ialu_reg_reg);
8531 %} 8472 %}
8532 8473
8533 8474
8534 // Logical Shift Right by variable 8475 // Logical Shift Right by variable
8535 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8476 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8536 match(Set dst (URShiftI dst shift)); 8477 match(Set dst (URShiftI dst shift));
8537 effect(KILL cr); 8478 effect(KILL cr);
8538 8479
8539 size(2); 8480 size(2);
8540 format %{ "SHR $dst,$shift" %} 8481 format %{ "SHR $dst,$shift" %}
8546 8487
8547 //----------Logical Instructions----------------------------------------------- 8488 //----------Logical Instructions-----------------------------------------------
8548 //----------Integer Logical Instructions--------------------------------------- 8489 //----------Integer Logical Instructions---------------------------------------
8549 // And Instructions 8490 // And Instructions
8550 // And Register with Register 8491 // And Register with Register
8551 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8492 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8552 match(Set dst (AndI dst src)); 8493 match(Set dst (AndI dst src));
8553 effect(KILL cr); 8494 effect(KILL cr);
8554 8495
8555 size(2); 8496 size(2);
8556 format %{ "AND $dst,$src" %} 8497 format %{ "AND $dst,$src" %}
8558 ins_encode( OpcP, RegReg( dst, src) ); 8499 ins_encode( OpcP, RegReg( dst, src) );
8559 ins_pipe( ialu_reg_reg ); 8500 ins_pipe( ialu_reg_reg );
8560 %} 8501 %}
8561 8502
8562 // And Register with Immediate 8503 // And Register with Immediate
8563 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 8504 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8564 match(Set dst (AndI dst src)); 8505 match(Set dst (AndI dst src));
8565 effect(KILL cr); 8506 effect(KILL cr);
8566 8507
8567 format %{ "AND $dst,$src" %} 8508 format %{ "AND $dst,$src" %}
8568 opcode(0x81,0x04); /* Opcode 81 /4 */ 8509 opcode(0x81,0x04); /* Opcode 81 /4 */
8570 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8511 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8571 ins_pipe( ialu_reg ); 8512 ins_pipe( ialu_reg );
8572 %} 8513 %}
8573 8514
8574 // And Register with Memory 8515 // And Register with Memory
8575 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 8516 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8576 match(Set dst (AndI dst (LoadI src))); 8517 match(Set dst (AndI dst (LoadI src)));
8577 effect(KILL cr); 8518 effect(KILL cr);
8578 8519
8579 ins_cost(125); 8520 ins_cost(125);
8580 format %{ "AND $dst,$src" %} 8521 format %{ "AND $dst,$src" %}
8582 ins_encode( OpcP, RegMem( dst, src) ); 8523 ins_encode( OpcP, RegMem( dst, src) );
8583 ins_pipe( ialu_reg_mem ); 8524 ins_pipe( ialu_reg_mem );
8584 %} 8525 %}
8585 8526
8586 // And Memory with Register 8527 // And Memory with Register
8587 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 8528 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8588 match(Set dst (StoreI dst (AndI (LoadI dst) src))); 8529 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8589 effect(KILL cr); 8530 effect(KILL cr);
8590 8531
8591 ins_cost(150); 8532 ins_cost(150);
8592 format %{ "AND $dst,$src" %} 8533 format %{ "AND $dst,$src" %}
8608 ins_pipe( ialu_mem_imm ); 8549 ins_pipe( ialu_mem_imm );
8609 %} 8550 %}
8610 8551
8611 // Or Instructions 8552 // Or Instructions
8612 // Or Register with Register 8553 // Or Register with Register
8613 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8554 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8614 match(Set dst (OrI dst src)); 8555 match(Set dst (OrI dst src));
8615 effect(KILL cr); 8556 effect(KILL cr);
8616 8557
8617 size(2); 8558 size(2);
8618 format %{ "OR $dst,$src" %} 8559 format %{ "OR $dst,$src" %}
8619 opcode(0x0B); 8560 opcode(0x0B);
8620 ins_encode( OpcP, RegReg( dst, src) ); 8561 ins_encode( OpcP, RegReg( dst, src) );
8621 ins_pipe( ialu_reg_reg ); 8562 ins_pipe( ialu_reg_reg );
8622 %} 8563 %}
8623 8564
8624 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{ 8565 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8625 match(Set dst (OrI dst (CastP2X src))); 8566 match(Set dst (OrI dst (CastP2X src)));
8626 effect(KILL cr); 8567 effect(KILL cr);
8627 8568
8628 size(2); 8569 size(2);
8629 format %{ "OR $dst,$src" %} 8570 format %{ "OR $dst,$src" %}
8632 ins_pipe( ialu_reg_reg ); 8573 ins_pipe( ialu_reg_reg );
8633 %} 8574 %}
8634 8575
8635 8576
8636 // Or Register with Immediate 8577 // Or Register with Immediate
8637 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 8578 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8638 match(Set dst (OrI dst src)); 8579 match(Set dst (OrI dst src));
8639 effect(KILL cr); 8580 effect(KILL cr);
8640 8581
8641 format %{ "OR $dst,$src" %} 8582 format %{ "OR $dst,$src" %}
8642 opcode(0x81,0x01); /* Opcode 81 /1 id */ 8583 opcode(0x81,0x01); /* Opcode 81 /1 id */
8644 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8585 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8645 ins_pipe( ialu_reg ); 8586 ins_pipe( ialu_reg );
8646 %} 8587 %}
8647 8588
8648 // Or Register with Memory 8589 // Or Register with Memory
8649 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 8590 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8650 match(Set dst (OrI dst (LoadI src))); 8591 match(Set dst (OrI dst (LoadI src)));
8651 effect(KILL cr); 8592 effect(KILL cr);
8652 8593
8653 ins_cost(125); 8594 ins_cost(125);
8654 format %{ "OR $dst,$src" %} 8595 format %{ "OR $dst,$src" %}
8656 ins_encode( OpcP, RegMem( dst, src) ); 8597 ins_encode( OpcP, RegMem( dst, src) );
8657 ins_pipe( ialu_reg_mem ); 8598 ins_pipe( ialu_reg_mem );
8658 %} 8599 %}
8659 8600
8660 // Or Memory with Register 8601 // Or Memory with Register
8661 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 8602 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8662 match(Set dst (StoreI dst (OrI (LoadI dst) src))); 8603 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8663 effect(KILL cr); 8604 effect(KILL cr);
8664 8605
8665 ins_cost(150); 8606 ins_cost(150);
8666 format %{ "OR $dst,$src" %} 8607 format %{ "OR $dst,$src" %}
8682 ins_pipe( ialu_mem_imm ); 8623 ins_pipe( ialu_mem_imm );
8683 %} 8624 %}
8684 8625
8685 // ROL/ROR 8626 // ROL/ROR
8686 // ROL expand 8627 // ROL expand
8687 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8628 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8688 effect(USE_DEF dst, USE shift, KILL cr); 8629 effect(USE_DEF dst, USE shift, KILL cr);
8689 8630
8690 format %{ "ROL $dst, $shift" %} 8631 format %{ "ROL $dst, $shift" %}
8691 opcode(0xD1, 0x0); /* Opcode D1 /0 */ 8632 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8692 ins_encode( OpcP, RegOpc( dst )); 8633 ins_encode( OpcP, RegOpc( dst ));
8693 ins_pipe( ialu_reg ); 8634 ins_pipe( ialu_reg );
8694 %} 8635 %}
8695 8636
8696 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8637 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8697 effect(USE_DEF dst, USE shift, KILL cr); 8638 effect(USE_DEF dst, USE shift, KILL cr);
8698 8639
8699 format %{ "ROL $dst, $shift" %} 8640 format %{ "ROL $dst, $shift" %}
8700 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ 8641 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8701 ins_encode( RegOpcImm(dst, shift) ); 8642 ins_encode( RegOpcImm(dst, shift) );
8711 ins_pipe( ialu_reg_reg ); 8652 ins_pipe( ialu_reg_reg );
8712 %} 8653 %}
8713 // end of ROL expand 8654 // end of ROL expand
8714 8655
8715 // ROL 32bit by one once 8656 // ROL 32bit by one once
8716 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ 8657 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8717 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); 8658 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8718 8659
8719 expand %{ 8660 expand %{
8720 rolI_eReg_imm1(dst, lshift, cr); 8661 rolI_eReg_imm1(dst, lshift, cr);
8721 %} 8662 %}
8722 %} 8663 %}
8723 8664
8724 // ROL 32bit var by imm8 once 8665 // ROL 32bit var by imm8 once
8725 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ 8666 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8726 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8667 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8727 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); 8668 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8728 8669
8729 expand %{ 8670 expand %{
8730 rolI_eReg_imm8(dst, lshift, cr); 8671 rolI_eReg_imm8(dst, lshift, cr);
8748 rolI_eReg_CL(dst, shift, cr); 8689 rolI_eReg_CL(dst, shift, cr);
8749 %} 8690 %}
8750 %} 8691 %}
8751 8692
8752 // ROR expand 8693 // ROR expand
8753 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8694 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8754 effect(USE_DEF dst, USE shift, KILL cr); 8695 effect(USE_DEF dst, USE shift, KILL cr);
8755 8696
8756 format %{ "ROR $dst, $shift" %} 8697 format %{ "ROR $dst, $shift" %}
8757 opcode(0xD1,0x1); /* Opcode D1 /1 */ 8698 opcode(0xD1,0x1); /* Opcode D1 /1 */
8758 ins_encode( OpcP, RegOpc( dst ) ); 8699 ins_encode( OpcP, RegOpc( dst ) );
8759 ins_pipe( ialu_reg ); 8700 ins_pipe( ialu_reg );
8760 %} 8701 %}
8761 8702
8762 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8703 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8763 effect (USE_DEF dst, USE shift, KILL cr); 8704 effect (USE_DEF dst, USE shift, KILL cr);
8764 8705
8765 format %{ "ROR $dst, $shift" %} 8706 format %{ "ROR $dst, $shift" %}
8766 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ 8707 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8767 ins_encode( RegOpcImm(dst, shift) ); 8708 ins_encode( RegOpcImm(dst, shift) );
8777 ins_pipe( ialu_reg_reg ); 8718 ins_pipe( ialu_reg_reg );
8778 %} 8719 %}
8779 // end of ROR expand 8720 // end of ROR expand
8780 8721
8781 // ROR right once 8722 // ROR right once
8782 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ 8723 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8783 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); 8724 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8784 8725
8785 expand %{ 8726 expand %{
8786 rorI_eReg_imm1(dst, rshift, cr); 8727 rorI_eReg_imm1(dst, rshift, cr);
8787 %} 8728 %}
8788 %} 8729 %}
8789 8730
8790 // ROR 32bit by immI8 once 8731 // ROR 32bit by immI8 once
8791 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ 8732 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8792 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8733 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8793 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); 8734 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8794 8735
8795 expand %{ 8736 expand %{
8796 rorI_eReg_imm8(dst, rshift, cr); 8737 rorI_eReg_imm8(dst, rshift, cr);
8815 %} 8756 %}
8816 %} 8757 %}
8817 8758
8818 // Xor Instructions 8759 // Xor Instructions
8819 // Xor Register with Register 8760 // Xor Register with Register
8820 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8761 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8821 match(Set dst (XorI dst src)); 8762 match(Set dst (XorI dst src));
8822 effect(KILL cr); 8763 effect(KILL cr);
8823 8764
8824 size(2); 8765 size(2);
8825 format %{ "XOR $dst,$src" %} 8766 format %{ "XOR $dst,$src" %}
8827 ins_encode( OpcP, RegReg( dst, src) ); 8768 ins_encode( OpcP, RegReg( dst, src) );
8828 ins_pipe( ialu_reg_reg ); 8769 ins_pipe( ialu_reg_reg );
8829 %} 8770 %}
8830 8771
8831 // Xor Register with Immediate -1 8772 // Xor Register with Immediate -1
8832 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{ 8773 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8833 match(Set dst (XorI dst imm)); 8774 match(Set dst (XorI dst imm));
8834 8775
8835 size(2); 8776 size(2);
8836 format %{ "NOT $dst" %} 8777 format %{ "NOT $dst" %}
8837 ins_encode %{ 8778 ins_encode %{
8839 %} 8780 %}
8840 ins_pipe( ialu_reg ); 8781 ins_pipe( ialu_reg );
8841 %} 8782 %}
8842 8783
8843 // Xor Register with Immediate 8784 // Xor Register with Immediate
8844 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 8785 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8845 match(Set dst (XorI dst src)); 8786 match(Set dst (XorI dst src));
8846 effect(KILL cr); 8787 effect(KILL cr);
8847 8788
8848 format %{ "XOR $dst,$src" %} 8789 format %{ "XOR $dst,$src" %}
8849 opcode(0x81,0x06); /* Opcode 81 /6 id */ 8790 opcode(0x81,0x06); /* Opcode 81 /6 id */
8851 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8792 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8852 ins_pipe( ialu_reg ); 8793 ins_pipe( ialu_reg );
8853 %} 8794 %}
8854 8795
8855 // Xor Register with Memory 8796 // Xor Register with Memory
8856 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 8797 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8857 match(Set dst (XorI dst (LoadI src))); 8798 match(Set dst (XorI dst (LoadI src)));
8858 effect(KILL cr); 8799 effect(KILL cr);
8859 8800
8860 ins_cost(125); 8801 ins_cost(125);
8861 format %{ "XOR $dst,$src" %} 8802 format %{ "XOR $dst,$src" %}
8863 ins_encode( OpcP, RegMem(dst, src) ); 8804 ins_encode( OpcP, RegMem(dst, src) );
8864 ins_pipe( ialu_reg_mem ); 8805 ins_pipe( ialu_reg_mem );
8865 %} 8806 %}
8866 8807
8867 // Xor Memory with Register 8808 // Xor Memory with Register
8868 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 8809 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8869 match(Set dst (StoreI dst (XorI (LoadI dst) src))); 8810 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8870 effect(KILL cr); 8811 effect(KILL cr);
8871 8812
8872 ins_cost(150); 8813 ins_cost(150);
8873 format %{ "XOR $dst,$src" %} 8814 format %{ "XOR $dst,$src" %}
8888 ins_pipe( ialu_mem_imm ); 8829 ins_pipe( ialu_mem_imm );
8889 %} 8830 %}
8890 8831
8891 //----------Convert Int to Boolean--------------------------------------------- 8832 //----------Convert Int to Boolean---------------------------------------------
8892 8833
8893 instruct movI_nocopy(eRegI dst, eRegI src) %{ 8834 instruct movI_nocopy(rRegI dst, rRegI src) %{
8894 effect( DEF dst, USE src ); 8835 effect( DEF dst, USE src );
8895 format %{ "MOV $dst,$src" %} 8836 format %{ "MOV $dst,$src" %}
8896 ins_encode( enc_Copy( dst, src) ); 8837 ins_encode( enc_Copy( dst, src) );
8897 ins_pipe( ialu_reg_reg ); 8838 ins_pipe( ialu_reg_reg );
8898 %} 8839 %}
8899 8840
8900 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{ 8841 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8901 effect( USE_DEF dst, USE src, KILL cr ); 8842 effect( USE_DEF dst, USE src, KILL cr );
8902 8843
8903 size(4); 8844 size(4);
8904 format %{ "NEG $dst\n\t" 8845 format %{ "NEG $dst\n\t"
8905 "ADC $dst,$src" %} 8846 "ADC $dst,$src" %}
8906 ins_encode( neg_reg(dst), 8847 ins_encode( neg_reg(dst),
8907 OpcRegReg(0x13,dst,src) ); 8848 OpcRegReg(0x13,dst,src) );
8908 ins_pipe( ialu_reg_reg_long ); 8849 ins_pipe( ialu_reg_reg_long );
8909 %} 8850 %}
8910 8851
8911 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{ 8852 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8912 match(Set dst (Conv2B src)); 8853 match(Set dst (Conv2B src));
8913 8854
8914 expand %{ 8855 expand %{
8915 movI_nocopy(dst,src); 8856 movI_nocopy(dst,src);
8916 ci2b(dst,src,cr); 8857 ci2b(dst,src,cr);
8917 %} 8858 %}
8918 %} 8859 %}
8919 8860
8920 instruct movP_nocopy(eRegI dst, eRegP src) %{ 8861 instruct movP_nocopy(rRegI dst, eRegP src) %{
8921 effect( DEF dst, USE src ); 8862 effect( DEF dst, USE src );
8922 format %{ "MOV $dst,$src" %} 8863 format %{ "MOV $dst,$src" %}
8923 ins_encode( enc_Copy( dst, src) ); 8864 ins_encode( enc_Copy( dst, src) );
8924 ins_pipe( ialu_reg_reg ); 8865 ins_pipe( ialu_reg_reg );
8925 %} 8866 %}
8926 8867
8927 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{ 8868 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8928 effect( USE_DEF dst, USE src, KILL cr ); 8869 effect( USE_DEF dst, USE src, KILL cr );
8929 format %{ "NEG $dst\n\t" 8870 format %{ "NEG $dst\n\t"
8930 "ADC $dst,$src" %} 8871 "ADC $dst,$src" %}
8931 ins_encode( neg_reg(dst), 8872 ins_encode( neg_reg(dst),
8932 OpcRegReg(0x13,dst,src) ); 8873 OpcRegReg(0x13,dst,src) );
8933 ins_pipe( ialu_reg_reg_long ); 8874 ins_pipe( ialu_reg_reg_long );
8934 %} 8875 %}
8935 8876
8936 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{ 8877 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8937 match(Set dst (Conv2B src)); 8878 match(Set dst (Conv2B src));
8938 8879
8939 expand %{ 8880 expand %{
8940 movP_nocopy(dst,src); 8881 movP_nocopy(dst,src);
8941 cp2b(dst,src,cr); 8882 cp2b(dst,src,cr);
8956 OpcRegReg(0x3B,p,q), 8897 OpcRegReg(0x3B,p,q),
8957 setLT_reg(dst), neg_reg(dst) ); 8898 setLT_reg(dst), neg_reg(dst) );
8958 ins_pipe( pipe_slow ); 8899 ins_pipe( pipe_slow );
8959 %} 8900 %}
8960 8901
8961 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{ 8902 instruct cmpLTMask0( rRegI dst, immI0 zero, eFlagsReg cr ) %{
8962 match(Set dst (CmpLTMask dst zero)); 8903 match(Set dst (CmpLTMask dst zero));
8963 effect( DEF dst, KILL cr ); 8904 effect( DEF dst, KILL cr );
8964 ins_cost(100); 8905 ins_cost(100);
8965 8906
8966 format %{ "SAR $dst,31" %} 8907 format %{ "SAR $dst,31" %}
9428 fpu_flags); 9369 fpu_flags);
9429 ins_pipe( pipe_slow ); 9370 ins_pipe( pipe_slow );
9430 %} 9371 %}
9431 9372
9432 // Compare vs zero into -1,0,1 9373 // Compare vs zero into -1,0,1
9433 instruct cmpDPR_0(eRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{ 9374 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9434 predicate(UseSSE<=1); 9375 predicate(UseSSE<=1);
9435 match(Set dst (CmpD3 src1 zero)); 9376 match(Set dst (CmpD3 src1 zero));
9436 effect(KILL cr, KILL rax); 9377 effect(KILL cr, KILL rax);
9437 ins_cost(280); 9378 ins_cost(280);
9438 format %{ "FTSTD $dst,$src1" %} 9379 format %{ "FTSTD $dst,$src1" %}
9442 CmpF_Result(dst)); 9383 CmpF_Result(dst));
9443 ins_pipe( pipe_slow ); 9384 ins_pipe( pipe_slow );
9444 %} 9385 %}
9445 9386
9446 // Compare into -1,0,1 9387 // Compare into -1,0,1
9447 instruct cmpDPR_reg(eRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{ 9388 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9448 predicate(UseSSE<=1); 9389 predicate(UseSSE<=1);
9449 match(Set dst (CmpD3 src1 src2)); 9390 match(Set dst (CmpD3 src1 src2));
9450 effect(KILL cr, KILL rax); 9391 effect(KILL cr, KILL rax);
9451 ins_cost(300); 9392 ins_cost(300);
9452 format %{ "FCMPD $dst,$src1,$src2" %} 9393 format %{ "FCMPD $dst,$src1,$src2" %}
10220 fpu_flags); 10161 fpu_flags);
10221 ins_pipe( pipe_slow ); 10162 ins_pipe( pipe_slow );
10222 %} 10163 %}
10223 10164
10224 // Compare vs zero into -1,0,1 10165 // Compare vs zero into -1,0,1
10225 instruct cmpFPR_0(eRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{ 10166 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10226 predicate(UseSSE == 0); 10167 predicate(UseSSE == 0);
10227 match(Set dst (CmpF3 src1 zero)); 10168 match(Set dst (CmpF3 src1 zero));
10228 effect(KILL cr, KILL rax); 10169 effect(KILL cr, KILL rax);
10229 ins_cost(280); 10170 ins_cost(280);
10230 format %{ "FTSTF $dst,$src1" %} 10171 format %{ "FTSTF $dst,$src1" %}
10234 CmpF_Result(dst)); 10175 CmpF_Result(dst));
10235 ins_pipe( pipe_slow ); 10176 ins_pipe( pipe_slow );
10236 %} 10177 %}
10237 10178
10238 // Compare into -1,0,1 10179 // Compare into -1,0,1
10239 instruct cmpFPR_reg(eRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ 10180 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10240 predicate(UseSSE == 0); 10181 predicate(UseSSE == 0);
10241 match(Set dst (CmpF3 src1 src2)); 10182 match(Set dst (CmpF3 src1 src2));
10242 effect(KILL cr, KILL rax); 10183 effect(KILL cr, KILL rax);
10243 ins_cost(300); 10184 ins_cost(300);
10244 format %{ "FCMPF $dst,$src1,$src2" %} 10185 format %{ "FCMPF $dst,$src1,$src2" %}
11154 opcode(0xDB, 0x0); /* DB /0 */ 11095 opcode(0xDB, 0x0); /* DB /0 */
11155 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst)); 11096 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11156 ins_pipe( fpu_reg_mem ); 11097 ins_pipe( fpu_reg_mem );
11157 %} 11098 %}
11158 11099
11159 instruct convI2D_reg(regD dst, eRegI src) %{ 11100 instruct convI2D_reg(regD dst, rRegI src) %{
11160 predicate( UseSSE>=2 && !UseXmmI2D ); 11101 predicate( UseSSE>=2 && !UseXmmI2D );
11161 match(Set dst (ConvI2D src)); 11102 match(Set dst (ConvI2D src));
11162 format %{ "CVTSI2SD $dst,$src" %} 11103 format %{ "CVTSI2SD $dst,$src" %}
11163 ins_encode %{ 11104 ins_encode %{
11164 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); 11105 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11174 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address); 11115 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11175 %} 11116 %}
11176 ins_pipe( pipe_slow ); 11117 ins_pipe( pipe_slow );
11177 %} 11118 %}
11178 11119
11179 instruct convXI2D_reg(regD dst, eRegI src) 11120 instruct convXI2D_reg(regD dst, rRegI src)
11180 %{ 11121 %{
11181 predicate( UseSSE>=2 && UseXmmI2D ); 11122 predicate( UseSSE>=2 && UseXmmI2D );
11182 match(Set dst (ConvI2D src)); 11123 match(Set dst (ConvI2D src));
11183 11124
11184 format %{ "MOVD $dst,$src\n\t" 11125 format %{ "MOVD $dst,$src\n\t"
11262 Pop_Reg_FPR(dst)); 11203 Pop_Reg_FPR(dst));
11263 ins_pipe( fpu_reg_mem ); 11204 ins_pipe( fpu_reg_mem );
11264 %} 11205 %}
11265 11206
11266 // Convert an int to a float in xmm; no rounding step needed. 11207 // Convert an int to a float in xmm; no rounding step needed.
11267 instruct convI2F_reg(regF dst, eRegI src) %{ 11208 instruct convI2F_reg(regF dst, rRegI src) %{
11268 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); 11209 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11269 match(Set dst (ConvI2F src)); 11210 match(Set dst (ConvI2F src));
11270 format %{ "CVTSI2SS $dst, $src" %} 11211 format %{ "CVTSI2SS $dst, $src" %}
11271 ins_encode %{ 11212 ins_encode %{
11272 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); 11213 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11273 %} 11214 %}
11274 ins_pipe( pipe_slow ); 11215 ins_pipe( pipe_slow );
11275 %} 11216 %}
11276 11217
11277 instruct convXI2F_reg(regF dst, eRegI src) 11218 instruct convXI2F_reg(regF dst, rRegI src)
11278 %{ 11219 %{
11279 predicate( UseSSE>=2 && UseXmmI2F ); 11220 predicate( UseSSE>=2 && UseXmmI2F );
11280 match(Set dst (ConvI2F src)); 11221 match(Set dst (ConvI2F src));
11281 11222
11282 format %{ "MOVD $dst,$src\n\t" 11223 format %{ "MOVD $dst,$src\n\t"
11286 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); 11227 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11287 %} 11228 %}
11288 ins_pipe(pipe_slow); // XXX 11229 ins_pipe(pipe_slow); // XXX
11289 %} 11230 %}
11290 11231
11291 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{ 11232 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11292 match(Set dst (ConvI2L src)); 11233 match(Set dst (ConvI2L src));
11293 effect(KILL cr); 11234 effect(KILL cr);
11294 ins_cost(375); 11235 ins_cost(375);
11295 format %{ "MOV $dst.lo,$src\n\t" 11236 format %{ "MOV $dst.lo,$src\n\t"
11296 "MOV $dst.hi,$src\n\t" 11237 "MOV $dst.hi,$src\n\t"
11298 ins_encode(convert_int_long(dst,src)); 11239 ins_encode(convert_int_long(dst,src));
11299 ins_pipe( ialu_reg_reg_long ); 11240 ins_pipe( ialu_reg_reg_long );
11300 %} 11241 %}
11301 11242
11302 // Zero-extend convert int to long 11243 // Zero-extend convert int to long
11303 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{ 11244 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11304 match(Set dst (AndL (ConvI2L src) mask) ); 11245 match(Set dst (AndL (ConvI2L src) mask) );
11305 effect( KILL flags ); 11246 effect( KILL flags );
11306 ins_cost(250); 11247 ins_cost(250);
11307 format %{ "MOV $dst.lo,$src\n\t" 11248 format %{ "MOV $dst.lo,$src\n\t"
11308 "XOR $dst.hi,$dst.hi" %} 11249 "XOR $dst.hi,$dst.hi" %}
11378 opcode(0xDF, 0x5); /* DF /5 */ 11319 opcode(0xDF, 0x5); /* DF /5 */
11379 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst)); 11320 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11380 ins_pipe( pipe_slow ); 11321 ins_pipe( pipe_slow );
11381 %} 11322 %}
11382 11323
11383 instruct convL2I_reg( eRegI dst, eRegL src ) %{ 11324 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11384 match(Set dst (ConvL2I src)); 11325 match(Set dst (ConvL2I src));
11385 effect( DEF dst, USE src ); 11326 effect( DEF dst, USE src );
11386 format %{ "MOV $dst,$src.lo" %} 11327 format %{ "MOV $dst,$src.lo" %}
11387 ins_encode(enc_CopyL_Lo(dst,src)); 11328 ins_encode(enc_CopyL_Lo(dst,src));
11388 ins_pipe( ialu_reg_reg ); 11329 ins_pipe( ialu_reg_reg );
11389 %} 11330 %}
11390 11331
11391 11332
11392 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{ 11333 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11393 match(Set dst (MoveF2I src)); 11334 match(Set dst (MoveF2I src));
11394 effect( DEF dst, USE src ); 11335 effect( DEF dst, USE src );
11395 ins_cost(100); 11336 ins_cost(100);
11396 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} 11337 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11397 ins_encode %{ 11338 ins_encode %{
11422 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); 11363 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11423 %} 11364 %}
11424 ins_pipe( pipe_slow ); 11365 ins_pipe( pipe_slow );
11425 %} 11366 %}
11426 11367
11427 instruct MoveF2I_reg_reg_sse(eRegI dst, regF src) %{ 11368 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11428 predicate(UseSSE>=2); 11369 predicate(UseSSE>=2);
11429 match(Set dst (MoveF2I src)); 11370 match(Set dst (MoveF2I src));
11430 effect( DEF dst, USE src ); 11371 effect( DEF dst, USE src );
11431 ins_cost(85); 11372 ins_cost(85);
11432 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} 11373 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11434 __ movdl($dst$$Register, $src$$XMMRegister); 11375 __ movdl($dst$$Register, $src$$XMMRegister);
11435 %} 11376 %}
11436 ins_pipe( pipe_slow ); 11377 ins_pipe( pipe_slow );
11437 %} 11378 %}
11438 11379
11439 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{ 11380 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11440 match(Set dst (MoveI2F src)); 11381 match(Set dst (MoveI2F src));
11441 effect( DEF dst, USE src ); 11382 effect( DEF dst, USE src );
11442 11383
11443 ins_cost(100); 11384 ins_cost(100);
11444 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} 11385 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11474 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); 11415 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11475 %} 11416 %}
11476 ins_pipe( pipe_slow ); 11417 ins_pipe( pipe_slow );
11477 %} 11418 %}
11478 11419
11479 instruct MoveI2F_reg_reg_sse(regF dst, eRegI src) %{ 11420 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11480 predicate(UseSSE>=2); 11421 predicate(UseSSE>=2);
11481 match(Set dst (MoveI2F src)); 11422 match(Set dst (MoveI2F src));
11482 effect( DEF dst, USE src ); 11423 effect( DEF dst, USE src );
11483 11424
11484 ins_cost(85); 11425 ins_cost(85);
11608 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); 11549 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11609 %} 11550 %}
11610 ins_pipe( pipe_slow ); 11551 ins_pipe( pipe_slow );
11611 %} 11552 %}
11612 11553
11613 // Replicate scalar to packed byte (1 byte) values in xmm
11614 instruct Repl8B_reg(regD dst, regD src) %{
11615 predicate(UseSSE>=2);
11616 match(Set dst (Replicate8B src));
11617 format %{ "MOVDQA $dst,$src\n\t"
11618 "PUNPCKLBW $dst,$dst\n\t"
11619 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11620 ins_encode %{
11621 if ($dst$$reg != $src$$reg) {
11622 __ movdqa($dst$$XMMRegister, $src$$XMMRegister);
11623 }
11624 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
11625 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11626 %}
11627 ins_pipe( pipe_slow );
11628 %}
11629
11630 // Replicate scalar to packed byte (1 byte) values in xmm
11631 instruct Repl8B_eRegI(regD dst, eRegI src) %{
11632 predicate(UseSSE>=2);
11633 match(Set dst (Replicate8B src));
11634 format %{ "MOVD $dst,$src\n\t"
11635 "PUNPCKLBW $dst,$dst\n\t"
11636 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11637 ins_encode %{
11638 __ movdl($dst$$XMMRegister, $src$$Register);
11639 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
11640 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11641 %}
11642 ins_pipe( pipe_slow );
11643 %}
11644
11645 // Replicate scalar zero to packed byte (1 byte) values in xmm
11646 instruct Repl8B_immI0(regD dst, immI0 zero) %{
11647 predicate(UseSSE>=2);
11648 match(Set dst (Replicate8B zero));
11649 format %{ "PXOR $dst,$dst\t! replicate8B" %}
11650 ins_encode %{
11651 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11652 %}
11653 ins_pipe( fpu_reg_reg );
11654 %}
11655
11656 // Replicate scalar to packed shore (2 byte) values in xmm
11657 instruct Repl4S_reg(regD dst, regD src) %{
11658 predicate(UseSSE>=2);
11659 match(Set dst (Replicate4S src));
11660 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
11661 ins_encode %{
11662 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
11663 %}
11664 ins_pipe( fpu_reg_reg );
11665 %}
11666
11667 // Replicate scalar to packed shore (2 byte) values in xmm
11668 instruct Repl4S_eRegI(regD dst, eRegI src) %{
11669 predicate(UseSSE>=2);
11670 match(Set dst (Replicate4S src));
11671 format %{ "MOVD $dst,$src\n\t"
11672 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
11673 ins_encode %{
11674 __ movdl($dst$$XMMRegister, $src$$Register);
11675 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11676 %}
11677 ins_pipe( fpu_reg_reg );
11678 %}
11679
11680 // Replicate scalar zero to packed short (2 byte) values in xmm
11681 instruct Repl4S_immI0(regD dst, immI0 zero) %{
11682 predicate(UseSSE>=2);
11683 match(Set dst (Replicate4S zero));
11684 format %{ "PXOR $dst,$dst\t! replicate4S" %}
11685 ins_encode %{
11686 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11687 %}
11688 ins_pipe( fpu_reg_reg );
11689 %}
11690
11691 // Replicate scalar to packed char (2 byte) values in xmm
11692 instruct Repl4C_reg(regD dst, regD src) %{
11693 predicate(UseSSE>=2);
11694 match(Set dst (Replicate4C src));
11695 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
11696 ins_encode %{
11697 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
11698 %}
11699 ins_pipe( fpu_reg_reg );
11700 %}
11701
11702 // Replicate scalar to packed char (2 byte) values in xmm
11703 instruct Repl4C_eRegI(regD dst, eRegI src) %{
11704 predicate(UseSSE>=2);
11705 match(Set dst (Replicate4C src));
11706 format %{ "MOVD $dst,$src\n\t"
11707 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
11708 ins_encode %{
11709 __ movdl($dst$$XMMRegister, $src$$Register);
11710 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11711 %}
11712 ins_pipe( fpu_reg_reg );
11713 %}
11714
11715 // Replicate scalar zero to packed char (2 byte) values in xmm
11716 instruct Repl4C_immI0(regD dst, immI0 zero) %{
11717 predicate(UseSSE>=2);
11718 match(Set dst (Replicate4C zero));
11719 format %{ "PXOR $dst,$dst\t! replicate4C" %}
11720 ins_encode %{
11721 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11722 %}
11723 ins_pipe( fpu_reg_reg );
11724 %}
11725
11726 // Replicate scalar to packed integer (4 byte) values in xmm
11727 instruct Repl2I_reg(regD dst, regD src) %{
11728 predicate(UseSSE>=2);
11729 match(Set dst (Replicate2I src));
11730 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
11731 ins_encode %{
11732 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00);
11733 %}
11734 ins_pipe( fpu_reg_reg );
11735 %}
11736
11737 // Replicate scalar to packed integer (4 byte) values in xmm
11738 instruct Repl2I_eRegI(regD dst, eRegI src) %{
11739 predicate(UseSSE>=2);
11740 match(Set dst (Replicate2I src));
11741 format %{ "MOVD $dst,$src\n\t"
11742 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
11743 ins_encode %{
11744 __ movdl($dst$$XMMRegister, $src$$Register);
11745 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11746 %}
11747 ins_pipe( fpu_reg_reg );
11748 %}
11749
11750 // Replicate scalar zero to packed integer (2 byte) values in xmm
11751 instruct Repl2I_immI0(regD dst, immI0 zero) %{
11752 predicate(UseSSE>=2);
11753 match(Set dst (Replicate2I zero));
11754 format %{ "PXOR $dst,$dst\t! replicate2I" %}
11755 ins_encode %{
11756 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11757 %}
11758 ins_pipe( fpu_reg_reg );
11759 %}
11760
11761 // Replicate scalar to packed single precision floating point values in xmm
11762 instruct Repl2F_reg(regD dst, regD src) %{
11763 predicate(UseSSE>=2);
11764 match(Set dst (Replicate2F src));
11765 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11766 ins_encode %{
11767 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
11768 %}
11769 ins_pipe( fpu_reg_reg );
11770 %}
11771
11772 // Replicate scalar to packed single precision floating point values in xmm
11773 instruct Repl2F_regF(regD dst, regF src) %{
11774 predicate(UseSSE>=2);
11775 match(Set dst (Replicate2F src));
11776 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11777 ins_encode %{
11778 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
11779 %}
11780 ins_pipe( fpu_reg_reg );
11781 %}
11782
11783 // Replicate scalar to packed single precision floating point values in xmm
11784 instruct Repl2F_immF0(regD dst, immF0 zero) %{
11785 predicate(UseSSE>=2);
11786 match(Set dst (Replicate2F zero));
11787 format %{ "PXOR $dst,$dst\t! replicate2F" %}
11788 ins_encode %{
11789 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11790 %}
11791 ins_pipe( fpu_reg_reg );
11792 %}
11793 11554
11794 // ======================================================================= 11555 // =======================================================================
11795 // fast clearing of an array 11556 // fast clearing of an array
11796 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ 11557 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11797 match(Set dummy (ClearArray cnt base)); 11558 match(Set dummy (ClearArray cnt base));
11896 ins_pipe( pipe_slow ); 11657 ins_pipe( pipe_slow );
11897 %} 11658 %}
11898 11659
11899 //----------Control Flow Instructions------------------------------------------ 11660 //----------Control Flow Instructions------------------------------------------
11900 // Signed compare Instructions 11661 // Signed compare Instructions
11901 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{ 11662 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11902 match(Set cr (CmpI op1 op2)); 11663 match(Set cr (CmpI op1 op2));
11903 effect( DEF cr, USE op1, USE op2 ); 11664 effect( DEF cr, USE op1, USE op2 );
11904 format %{ "CMP $op1,$op2" %} 11665 format %{ "CMP $op1,$op2" %}
11905 opcode(0x3B); /* Opcode 3B /r */ 11666 opcode(0x3B); /* Opcode 3B /r */
11906 ins_encode( OpcP, RegReg( op1, op2) ); 11667 ins_encode( OpcP, RegReg( op1, op2) );
11907 ins_pipe( ialu_cr_reg_reg ); 11668 ins_pipe( ialu_cr_reg_reg );
11908 %} 11669 %}
11909 11670
11910 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{ 11671 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11911 match(Set cr (CmpI op1 op2)); 11672 match(Set cr (CmpI op1 op2));
11912 effect( DEF cr, USE op1 ); 11673 effect( DEF cr, USE op1 );
11913 format %{ "CMP $op1,$op2" %} 11674 format %{ "CMP $op1,$op2" %}
11914 opcode(0x81,0x07); /* Opcode 81 /7 */ 11675 opcode(0x81,0x07); /* Opcode 81 /7 */
11915 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ 11676 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11916 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 11677 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11917 ins_pipe( ialu_cr_reg_imm ); 11678 ins_pipe( ialu_cr_reg_imm );
11918 %} 11679 %}
11919 11680
11920 // Cisc-spilled version of cmpI_eReg 11681 // Cisc-spilled version of cmpI_eReg
11921 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{ 11682 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11922 match(Set cr (CmpI op1 (LoadI op2))); 11683 match(Set cr (CmpI op1 (LoadI op2)));
11923 11684
11924 format %{ "CMP $op1,$op2" %} 11685 format %{ "CMP $op1,$op2" %}
11925 ins_cost(500); 11686 ins_cost(500);
11926 opcode(0x3B); /* Opcode 3B /r */ 11687 opcode(0x3B); /* Opcode 3B /r */
11927 ins_encode( OpcP, RegMem( op1, op2) ); 11688 ins_encode( OpcP, RegMem( op1, op2) );
11928 ins_pipe( ialu_cr_reg_mem ); 11689 ins_pipe( ialu_cr_reg_mem );
11929 %} 11690 %}
11930 11691
11931 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{ 11692 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11932 match(Set cr (CmpI src zero)); 11693 match(Set cr (CmpI src zero));
11933 effect( DEF cr, USE src ); 11694 effect( DEF cr, USE src );
11934 11695
11935 format %{ "TEST $src,$src" %} 11696 format %{ "TEST $src,$src" %}
11936 opcode(0x85); 11697 opcode(0x85);
11937 ins_encode( OpcP, RegReg( src, src ) ); 11698 ins_encode( OpcP, RegReg( src, src ) );
11938 ins_pipe( ialu_cr_reg_imm ); 11699 ins_pipe( ialu_cr_reg_imm );
11939 %} 11700 %}
11940 11701
11941 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{ 11702 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11942 match(Set cr (CmpI (AndI src con) zero)); 11703 match(Set cr (CmpI (AndI src con) zero));
11943 11704
11944 format %{ "TEST $src,$con" %} 11705 format %{ "TEST $src,$con" %}
11945 opcode(0xF7,0x00); 11706 opcode(0xF7,0x00);
11946 ins_encode( OpcP, RegOpc(src), Con32(con) ); 11707 ins_encode( OpcP, RegOpc(src), Con32(con) );
11947 ins_pipe( ialu_cr_reg_imm ); 11708 ins_pipe( ialu_cr_reg_imm );
11948 %} 11709 %}
11949 11710
11950 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{ 11711 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11951 match(Set cr (CmpI (AndI src mem) zero)); 11712 match(Set cr (CmpI (AndI src mem) zero));
11952 11713
11953 format %{ "TEST $src,$mem" %} 11714 format %{ "TEST $src,$mem" %}
11954 opcode(0x85); 11715 opcode(0x85);
11955 ins_encode( OpcP, RegMem( src, mem ) ); 11716 ins_encode( OpcP, RegMem( src, mem ) );
11956 ins_pipe( ialu_cr_reg_mem ); 11717 ins_pipe( ialu_cr_reg_mem );
11957 %} 11718 %}
11958 11719
11959 // Unsigned compare Instructions; really, same as signed except they 11720 // Unsigned compare Instructions; really, same as signed except they
11960 // produce an eFlagsRegU instead of eFlagsReg. 11721 // produce an eFlagsRegU instead of eFlagsReg.
11961 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{ 11722 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11962 match(Set cr (CmpU op1 op2)); 11723 match(Set cr (CmpU op1 op2));
11963 11724
11964 format %{ "CMPu $op1,$op2" %} 11725 format %{ "CMPu $op1,$op2" %}
11965 opcode(0x3B); /* Opcode 3B /r */ 11726 opcode(0x3B); /* Opcode 3B /r */
11966 ins_encode( OpcP, RegReg( op1, op2) ); 11727 ins_encode( OpcP, RegReg( op1, op2) );
11967 ins_pipe( ialu_cr_reg_reg ); 11728 ins_pipe( ialu_cr_reg_reg );
11968 %} 11729 %}
11969 11730
11970 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{ 11731 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11971 match(Set cr (CmpU op1 op2)); 11732 match(Set cr (CmpU op1 op2));
11972 11733
11973 format %{ "CMPu $op1,$op2" %} 11734 format %{ "CMPu $op1,$op2" %}
11974 opcode(0x81,0x07); /* Opcode 81 /7 */ 11735 opcode(0x81,0x07); /* Opcode 81 /7 */
11975 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 11736 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11976 ins_pipe( ialu_cr_reg_imm ); 11737 ins_pipe( ialu_cr_reg_imm );
11977 %} 11738 %}
11978 11739
11979 // // Cisc-spilled version of cmpU_eReg 11740 // // Cisc-spilled version of cmpU_eReg
11980 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{ 11741 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11981 match(Set cr (CmpU op1 (LoadI op2))); 11742 match(Set cr (CmpU op1 (LoadI op2)));
11982 11743
11983 format %{ "CMPu $op1,$op2" %} 11744 format %{ "CMPu $op1,$op2" %}
11984 ins_cost(500); 11745 ins_cost(500);
11985 opcode(0x3B); /* Opcode 3B /r */ 11746 opcode(0x3B); /* Opcode 3B /r */
11986 ins_encode( OpcP, RegMem( op1, op2) ); 11747 ins_encode( OpcP, RegMem( op1, op2) );
11987 ins_pipe( ialu_cr_reg_mem ); 11748 ins_pipe( ialu_cr_reg_mem );
11988 %} 11749 %}
11989 11750
11990 // // Cisc-spilled version of cmpU_eReg 11751 // // Cisc-spilled version of cmpU_eReg
11991 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{ 11752 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11992 // match(Set cr (CmpU (LoadI op1) op2)); 11753 // match(Set cr (CmpU (LoadI op1) op2));
11993 // 11754 //
11994 // format %{ "CMPu $op1,$op2" %} 11755 // format %{ "CMPu $op1,$op2" %}
11995 // ins_cost(500); 11756 // ins_cost(500);
11996 // opcode(0x39); /* Opcode 39 /r */ 11757 // opcode(0x39); /* Opcode 39 /r */
11997 // ins_encode( OpcP, RegMem( op1, op2) ); 11758 // ins_encode( OpcP, RegMem( op1, op2) );
11998 //%} 11759 //%}
11999 11760
12000 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{ 11761 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
12001 match(Set cr (CmpU src zero)); 11762 match(Set cr (CmpU src zero));
12002 11763
12003 format %{ "TESTu $src,$src" %} 11764 format %{ "TESTu $src,$src" %}
12004 opcode(0x85); 11765 opcode(0x85);
12005 ins_encode( OpcP, RegReg( src, src ) ); 11766 ins_encode( OpcP, RegReg( src, src ) );
12091 // Min Instructions 11852 // Min Instructions
12092 //// 11853 ////
12093 // *** Min and Max using the conditional move are slower than the 11854 // *** Min and Max using the conditional move are slower than the
12094 // *** branch version on a Pentium III. 11855 // *** branch version on a Pentium III.
12095 // // Conditional move for min 11856 // // Conditional move for min
12096 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ 11857 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12097 // effect( USE_DEF op2, USE op1, USE cr ); 11858 // effect( USE_DEF op2, USE op1, USE cr );
12098 // format %{ "CMOVlt $op2,$op1\t! min" %} 11859 // format %{ "CMOVlt $op2,$op1\t! min" %}
12099 // opcode(0x4C,0x0F); 11860 // opcode(0x4C,0x0F);
12100 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); 11861 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12101 // ins_pipe( pipe_cmov_reg ); 11862 // ins_pipe( pipe_cmov_reg );
12102 //%} 11863 //%}
12103 // 11864 //
12104 //// Min Register with Register (P6 version) 11865 //// Min Register with Register (P6 version)
12105 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{ 11866 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
12106 // predicate(VM_Version::supports_cmov() ); 11867 // predicate(VM_Version::supports_cmov() );
12107 // match(Set op2 (MinI op1 op2)); 11868 // match(Set op2 (MinI op1 op2));
12108 // ins_cost(200); 11869 // ins_cost(200);
12109 // expand %{ 11870 // expand %{
12110 // eFlagsReg cr; 11871 // eFlagsReg cr;
12112 // cmovI_reg_lt(op2,op1,cr); 11873 // cmovI_reg_lt(op2,op1,cr);
12113 // %} 11874 // %}
12114 //%} 11875 //%}
12115 11876
12116 // Min Register with Register (generic version) 11877 // Min Register with Register (generic version)
12117 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ 11878 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12118 match(Set dst (MinI dst src)); 11879 match(Set dst (MinI dst src));
12119 effect(KILL flags); 11880 effect(KILL flags);
12120 ins_cost(300); 11881 ins_cost(300);
12121 11882
12122 format %{ "MIN $dst,$src" %} 11883 format %{ "MIN $dst,$src" %}
12127 11888
12128 // Max Register with Register 11889 // Max Register with Register
12129 // *** Min and Max using the conditional move are slower than the 11890 // *** Min and Max using the conditional move are slower than the
12130 // *** branch version on a Pentium III. 11891 // *** branch version on a Pentium III.
12131 // // Conditional move for max 11892 // // Conditional move for max
12132 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ 11893 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12133 // effect( USE_DEF op2, USE op1, USE cr ); 11894 // effect( USE_DEF op2, USE op1, USE cr );
12134 // format %{ "CMOVgt $op2,$op1\t! max" %} 11895 // format %{ "CMOVgt $op2,$op1\t! max" %}
12135 // opcode(0x4F,0x0F); 11896 // opcode(0x4F,0x0F);
12136 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); 11897 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12137 // ins_pipe( pipe_cmov_reg ); 11898 // ins_pipe( pipe_cmov_reg );
12138 //%} 11899 //%}
12139 // 11900 //
12140 // // Max Register with Register (P6 version) 11901 // // Max Register with Register (P6 version)
12141 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{ 11902 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
12142 // predicate(VM_Version::supports_cmov() ); 11903 // predicate(VM_Version::supports_cmov() );
12143 // match(Set op2 (MaxI op1 op2)); 11904 // match(Set op2 (MaxI op1 op2));
12144 // ins_cost(200); 11905 // ins_cost(200);
12145 // expand %{ 11906 // expand %{
12146 // eFlagsReg cr; 11907 // eFlagsReg cr;
12148 // cmovI_reg_gt(op2,op1,cr); 11909 // cmovI_reg_gt(op2,op1,cr);
12149 // %} 11910 // %}
12150 //%} 11911 //%}
12151 11912
12152 // Max Register with Register (generic version) 11913 // Max Register with Register (generic version)
12153 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ 11914 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12154 match(Set dst (MaxI dst src)); 11915 match(Set dst (MaxI dst src));
12155 effect(KILL flags); 11916 effect(KILL flags);
12156 ins_cost(300); 11917 ins_cost(300);
12157 11918
12158 format %{ "MAX $dst,$src" %} 11919 format %{ "MAX $dst,$src" %}
12209 %} 11970 %}
12210 11971
12211 // ============================================================================ 11972 // ============================================================================
12212 // Branch Instructions 11973 // Branch Instructions
12213 // Jump Table 11974 // Jump Table
12214 instruct jumpXtnd(eRegI switch_val) %{ 11975 instruct jumpXtnd(rRegI switch_val) %{
12215 match(Jump switch_val); 11976 match(Jump switch_val);
12216 ins_cost(350); 11977 ins_cost(350);
12217 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %} 11978 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12218 ins_encode %{ 11979 ins_encode %{
12219 // Jump to Address(table_base + switch_reg) 11980 // Jump to Address(table_base + switch_reg)
12627 %} 12388 %}
12628 12389
12629 // Manifest a CmpL result in the normal flags. Only good for LT or GE 12390 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12630 // compares. Can be used for LE or GT compares by reversing arguments. 12391 // compares. Can be used for LE or GT compares by reversing arguments.
12631 // NOT GOOD FOR EQ/NE tests. 12392 // NOT GOOD FOR EQ/NE tests.
12632 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{ 12393 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12633 match( Set flags (CmpL src1 src2 )); 12394 match( Set flags (CmpL src1 src2 ));
12634 effect( TEMP tmp ); 12395 effect( TEMP tmp );
12635 ins_cost(300); 12396 ins_cost(300);
12636 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" 12397 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12637 "MOV $tmp,$src1.hi\n\t" 12398 "MOV $tmp,$src1.hi\n\t"
12673 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 12434 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12674 ins_pipe( pipe_cmov_reg_long ); 12435 ins_pipe( pipe_cmov_reg_long );
12675 %} 12436 %}
12676 12437
12677 // Compare 2 longs and CMOVE ints. 12438 // Compare 2 longs and CMOVE ints.
12678 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{ 12439 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12679 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12440 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12680 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 12441 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12681 ins_cost(200); 12442 ins_cost(200);
12682 format %{ "CMOV$cmp $dst,$src" %} 12443 format %{ "CMOV$cmp $dst,$src" %}
12683 opcode(0x0F,0x40); 12444 opcode(0x0F,0x40);
12684 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12445 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12685 ins_pipe( pipe_cmov_reg ); 12446 ins_pipe( pipe_cmov_reg );
12686 %} 12447 %}
12687 12448
12688 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{ 12449 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12689 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12450 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12690 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 12451 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12691 ins_cost(250); 12452 ins_cost(250);
12692 format %{ "CMOV$cmp $dst,$src" %} 12453 format %{ "CMOV$cmp $dst,$src" %}
12693 opcode(0x0F,0x40); 12454 opcode(0x0F,0x40);
12744 %} 12505 %}
12745 %} 12506 %}
12746 12507
12747 //====== 12508 //======
12748 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. 12509 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12749 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{ 12510 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12750 match( Set flags (CmpL src zero )); 12511 match( Set flags (CmpL src zero ));
12751 effect(TEMP tmp); 12512 effect(TEMP tmp);
12752 ins_cost(200); 12513 ins_cost(200);
12753 format %{ "MOV $tmp,$src.lo\n\t" 12514 format %{ "MOV $tmp,$src.lo\n\t"
12754 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} 12515 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12801 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 12562 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12802 ins_pipe( pipe_cmov_reg_long ); 12563 ins_pipe( pipe_cmov_reg_long );
12803 %} 12564 %}
12804 12565
12805 // Compare 2 longs and CMOVE ints. 12566 // Compare 2 longs and CMOVE ints.
12806 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{ 12567 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12807 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12568 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12808 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 12569 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12809 ins_cost(200); 12570 ins_cost(200);
12810 format %{ "CMOV$cmp $dst,$src" %} 12571 format %{ "CMOV$cmp $dst,$src" %}
12811 opcode(0x0F,0x40); 12572 opcode(0x0F,0x40);
12812 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12573 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12813 ins_pipe( pipe_cmov_reg ); 12574 ins_pipe( pipe_cmov_reg );
12814 %} 12575 %}
12815 12576
12816 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{ 12577 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12817 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12578 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12818 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 12579 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12819 ins_cost(250); 12580 ins_cost(250);
12820 format %{ "CMOV$cmp $dst,$src" %} 12581 format %{ "CMOV$cmp $dst,$src" %}
12821 opcode(0x0F,0x40); 12582 opcode(0x0F,0x40);
12873 %} 12634 %}
12874 12635
12875 //====== 12636 //======
12876 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. 12637 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12877 // Same as cmpL_reg_flags_LEGT except must negate src 12638 // Same as cmpL_reg_flags_LEGT except must negate src
12878 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{ 12639 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12879 match( Set flags (CmpL src zero )); 12640 match( Set flags (CmpL src zero ));
12880 effect( TEMP tmp ); 12641 effect( TEMP tmp );
12881 ins_cost(300); 12642 ins_cost(300);
12882 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" 12643 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12883 "CMP $tmp,$src.lo\n\t" 12644 "CMP $tmp,$src.lo\n\t"
12887 %} 12648 %}
12888 12649
12889 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. 12650 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12890 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands 12651 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12891 // requires a commuted test to get the same result. 12652 // requires a commuted test to get the same result.
12892 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{ 12653 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12893 match( Set flags (CmpL src1 src2 )); 12654 match( Set flags (CmpL src1 src2 ));
12894 effect( TEMP tmp ); 12655 effect( TEMP tmp );
12895 ins_cost(300); 12656 ins_cost(300);
12896 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" 12657 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12897 "MOV $tmp,$src2.hi\n\t" 12658 "MOV $tmp,$src2.hi\n\t"
12934 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 12695 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12935 ins_pipe( pipe_cmov_reg_long ); 12696 ins_pipe( pipe_cmov_reg_long );
12936 %} 12697 %}
12937 12698
12938 // Compare 2 longs and CMOVE ints. 12699 // Compare 2 longs and CMOVE ints.
12939 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{ 12700 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12940 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12701 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12941 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 12702 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12942 ins_cost(200); 12703 ins_cost(200);
12943 format %{ "CMOV$cmp $dst,$src" %} 12704 format %{ "CMOV$cmp $dst,$src" %}
12944 opcode(0x0F,0x40); 12705 opcode(0x0F,0x40);
12945 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12706 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12946 ins_pipe( pipe_cmov_reg ); 12707 ins_pipe( pipe_cmov_reg );
12947 %} 12708 %}
12948 12709
12949 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{ 12710 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12950 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12711 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12951 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 12712 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12952 ins_cost(250); 12713 ins_cost(250);
12953 format %{ "CMOV$cmp $dst,$src" %} 12714 format %{ "CMOV$cmp $dst,$src" %}
12954 opcode(0x0F,0x40); 12715 opcode(0x0F,0x40);
13273 // Only one replacement instruction 13034 // Only one replacement instruction
13274 // 13035 //
13275 // ---------EXAMPLE---------------------------------------------------------- 13036 // ---------EXAMPLE----------------------------------------------------------
13276 // 13037 //
13277 // // pertinent parts of existing instructions in architecture description 13038 // // pertinent parts of existing instructions in architecture description
13278 // instruct movI(eRegI dst, eRegI src) %{ 13039 // instruct movI(rRegI dst, rRegI src) %{
13279 // match(Set dst (CopyI src)); 13040 // match(Set dst (CopyI src));
13280 // %} 13041 // %}
13281 // 13042 //
13282 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 13043 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13283 // match(Set dst (AddI dst src)); 13044 // match(Set dst (AddI dst src));
13284 // effect(KILL cr); 13045 // effect(KILL cr);
13285 // %} 13046 // %}
13286 // 13047 //
13287 // // Change (inc mov) to lea 13048 // // Change (inc mov) to lea
13322 // peepconstraint ( 0.dst == 1.dst ); 13083 // peepconstraint ( 0.dst == 1.dst );
13323 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); 13084 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13324 // %} 13085 // %}
13325 13086
13326 // // Change load of spilled value to only a spill 13087 // // Change load of spilled value to only a spill
13327 // instruct storeI(memory mem, eRegI src) %{ 13088 // instruct storeI(memory mem, rRegI src) %{
13328 // match(Set mem (StoreI mem src)); 13089 // match(Set mem (StoreI mem src));
13329 // %} 13090 // %}
13330 // 13091 //
13331 // instruct loadI(eRegI dst, memory mem) %{ 13092 // instruct loadI(rRegI dst, memory mem) %{
13332 // match(Set dst (LoadI mem)); 13093 // match(Set dst (LoadI mem));
13333 // %} 13094 // %}
13334 // 13095 //
13335 peephole %{ 13096 peephole %{
13336 peepmatch ( loadI storeI ); 13097 peepmatch ( loadI storeI );