Mercurial > hg > truffle
comparison src/os_cpu/solaris_sparc/vm/solaris_sparc.s @ 11127:980532a806a5
8016697: Use stubs to implement safefetch
Summary: Implement Safefetch as stub routines. This reduces compiler and os dependencies.
Reviewed-by: twisti, kvn
| author | goetz |
|---|---|
| date | Thu, 20 Jun 2013 15:02:05 +0200 |
| parents | 3be7439273c5 |
| children | de6a9e811145 |
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| 11088:ea4d24c1e0c6 | 11127:980532a806a5 |
|---|---|
| 18 !! | 18 !! |
| 19 !! Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA | 19 !! Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| 20 !! or visit www.oracle.com if you need additional information or have any | 20 !! or visit www.oracle.com if you need additional information or have any |
| 21 !! questions. | 21 !! questions. |
| 22 !! | 22 !! |
| 23 | |
| 24 !! Prototype: int SafeFetch32 (int * adr, int ErrValue) | |
| 25 !! The "ld" at Fetch32 is potentially faulting instruction. | |
| 26 !! If the instruction traps the trap handler will arrange | |
| 27 !! for control to resume at Fetch32Resume. | |
| 28 !! By convention with the trap handler we ensure there is a non-CTI | |
| 29 !! instruction in the trap shadow. | |
| 30 !! | |
| 31 !! The reader might be tempted to move this service to .il. | |
| 32 !! Don't. Sun's CC back-end reads and optimize code emitted | |
| 33 !! by the .il "call", in some cases optimizing the code, completely eliding it, | |
| 34 !! or by moving the code from the "call site". | |
| 35 | |
| 36 !! ASM better know we may use G6 for our own purposes | |
| 37 .register %g6, #ignore | |
| 38 | |
| 39 .globl SafeFetch32 | |
| 40 .align 32 | |
| 41 .global Fetch32PFI, Fetch32Resume | |
| 42 SafeFetch32: | |
| 43 mov %o0, %g1 | |
| 44 mov %o1, %o0 | |
| 45 Fetch32PFI: | |
| 46 ld [%g1], %o0 !! <-- Potentially faulting instruction | |
| 47 Fetch32Resume: | |
| 48 nop | |
| 49 retl | |
| 50 nop | |
| 51 | |
| 52 .globl SafeFetchN | |
| 53 .align 32 | |
| 54 .globl FetchNPFI, FetchNResume | |
| 55 SafeFetchN: | |
| 56 mov %o0, %g1 | |
| 57 mov %o1, %o0 | |
| 58 FetchNPFI: | |
| 59 ldn [%g1], %o0 | |
| 60 FetchNResume: | |
| 61 nop | |
| 62 retl | |
| 63 nop | |
| 64 | 23 |
| 65 !! Possibilities: | 24 !! Possibilities: |
| 66 !! -- membar | 25 !! -- membar |
| 67 !! -- CAS (SP + BIAS, G0, G0) | 26 !! -- CAS (SP + BIAS, G0, G0) |
| 68 !! -- wr %g0, %asi | 27 !! -- wr %g0, %asi |