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8031743: C2: loadI2L_immI broken for negative memory values Summary: Restrict loadI2L_imm optimizations to positive values of mask Reviewed-by: kvn, dlong
author iveresov
date Tue, 21 Jan 2014 20:05:28 -0800
parents f970454708b8
children 89152779163c 51e1bb81df86 f040cf9fc9c0
comparison
equal deleted inserted replaced
17505:f970454708b8 17506:984401824c5e
3353 op_cost(0); 3353 op_cost(0);
3354 format %{ %} 3354 format %{ %}
3355 interface(CONST_INTER); 3355 interface(CONST_INTER);
3356 %} 3356 %}
3357 3357
3358 // Unsigned (positive) Integer Immediate: 13-bit 3358 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3359 operand immU13() %{ 3359 operand immU12() %{
3360 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3360 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3361 match(ConI); 3361 match(ConI);
3362 op_cost(0); 3362 op_cost(0);
3363 3363
3364 format %{ %} 3364 format %{ %}
3385 3385
3386 // Integer Immediate: 5-bit 3386 // Integer Immediate: 5-bit
3387 operand immI5() %{ 3387 operand immI5() %{
3388 predicate(Assembler::is_simm5(n->get_int())); 3388 predicate(Assembler::is_simm5(n->get_int()));
3389 match(ConI); 3389 match(ConI);
3390 op_cost(0);
3391 format %{ %}
3392 interface(CONST_INTER);
3393 %}
3394
3395 // Int Immediate non-negative
3396 operand immU31()
3397 %{
3398 predicate(n->get_int() >= 0);
3399 match(ConI);
3400
3390 op_cost(0); 3401 op_cost(0);
3391 format %{ %} 3402 format %{ %}
3392 interface(CONST_INTER); 3403 interface(CONST_INTER);
3393 %} 3404 %}
3394 3405
5839 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5850 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5840 %} 5851 %}
5841 ins_pipe(iload_mem); 5852 ins_pipe(iload_mem);
5842 %} 5853 %}
5843 5854
5844 // Load Integer with a 13-bit mask into a Long Register 5855 // Load Integer with a 12-bit mask into a Long Register
5845 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5856 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5846 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5857 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5847 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5858 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5848 5859
5849 size(2*4); 5860 size(2*4);
5850 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" 5861 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5851 "AND $dst,$mask,$dst" %} 5862 "AND $dst,$mask,$dst" %}
5852 ins_encode %{ 5863 ins_encode %{
5853 Register Rdst = $dst$$Register; 5864 Register Rdst = $dst$$Register;
5854 __ lduw($mem$$Address, Rdst); 5865 __ lduw($mem$$Address, Rdst);
5855 __ and3(Rdst, $mask$$constant, Rdst); 5866 __ and3(Rdst, $mask$$constant, Rdst);
5856 %} 5867 %}
5857 ins_pipe(iload_mem); 5868 ins_pipe(iload_mem);
5858 %} 5869 %}
5859 5870
5860 // Load Integer with a 32-bit mask into a Long Register 5871 // Load Integer with a 31-bit mask into a Long Register
5861 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5872 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5862 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5873 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5863 effect(TEMP dst, TEMP tmp); 5874 effect(TEMP dst, TEMP tmp);
5864 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5875 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5865 5876
5866 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" 5877 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5867 "SET $mask,$tmp\n\t" 5878 "SET $mask,$tmp\n\t"
5868 "AND $dst,$tmp,$dst" %} 5879 "AND $dst,$tmp,$dst" %}
5869 ins_encode %{ 5880 ins_encode %{
5870 Register Rdst = $dst$$Register; 5881 Register Rdst = $dst$$Register;
5871 Register Rtmp = $tmp$$Register; 5882 Register Rtmp = $tmp$$Register;
8956 opcode(Assembler::andcc_op3, Assembler::arith_op); 8967 opcode(Assembler::andcc_op3, Assembler::arith_op);
8957 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8968 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8958 ins_pipe(ialu_cconly_reg_reg); 8969 ins_pipe(ialu_cconly_reg_reg);
8959 %} 8970 %}
8960 8971
8961 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ 8972 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8962 match(Set icc (CmpU op1 op2)); 8973 match(Set icc (CmpU op1 op2));
8963 8974
8964 size(4); 8975 size(4);
8965 format %{ "CMP $op1,$op2\t! unsigned" %} 8976 format %{ "CMP $op1,$op2\t! unsigned" %}
8966 opcode(Assembler::subcc_op3, Assembler::arith_op); 8977 opcode(Assembler::subcc_op3, Assembler::arith_op);