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comparison src/cpu/sparc/vm/sparc.ad @ 605:98cb887364d3

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6810672: Comment typos Summary: I have collected some typos I have found while looking at the code. Reviewed-by: kvn, never
author twisti
date Fri, 27 Feb 2009 13:27:09 -0800
parents 3b5ac9e7e6ea
children 337400e7a5dd
comparison
equal deleted inserted replaced
604:ec59443af135 605:98cb887364d3
187 187
188 // These definitions specify the actual bit encodings of the sparc 188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs 190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning 'dont go here'. 192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until 193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is 194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up. 195 // fixed up.
196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()); 196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg());
197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next()); 197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next());
460 // Must be visible to the DFA in dfa_sparc.cpp 460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp ); 461 extern bool can_branch_register( Node *bol, Node *cmp );
462 462
463 // Macros to extract hi & lo halves from a long pair. 463 // Macros to extract hi & lo halves from a long pair.
464 // G0 is not part of any long pair, so assert on that. 464 // G0 is not part of any long pair, so assert on that.
465 // Prevents accidently using G1 instead of G0. 465 // Prevents accidentally using G1 instead of G0.
466 #define LONG_HI_REG(x) (x) 466 #define LONG_HI_REG(x) (x)
467 #define LONG_LO_REG(x) (x) 467 #define LONG_LO_REG(x) (x)
468 468
469 %} 469 %}
470 470
1429 return size; // Self copy; no move 1429 return size; // Self copy; no move
1430 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1430 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1431 1431
1432 #ifndef _LP64 1432 #ifndef _LP64
1433 // In the LP64 build, all registers can be moved as aligned/adjacent 1433 // In the LP64 build, all registers can be moved as aligned/adjacent
1434 // pairs, so there's never any need to move the high bits seperately. 1434 // pairs, so there's never any need to move the high bits separately.
1435 // The 32-bit builds have to deal with the 32-bit ABI which can force 1435 // The 32-bit builds have to deal with the 32-bit ABI which can force
1436 // all sorts of silly alignment problems. 1436 // all sorts of silly alignment problems.
1437 1437
1438 // Check for integer reg-reg copy. Hi bits are stuck up in the top 1438 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1439 // 32-bits of a 64-bit register, but are needed in low bits of another 1439 // 32-bits of a 64-bit register, but are needed in low bits of another
1622 Label L; 1622 Label L;
1623 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1623 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1624 Register temp_reg = G3; 1624 Register temp_reg = G3;
1625 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1625 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1626 1626
1627 // Load klass from reciever 1627 // Load klass from receiver
1628 __ load_klass(O0, temp_reg); 1628 __ load_klass(O0, temp_reg);
1629 // Compare against expected klass 1629 // Compare against expected klass
1630 __ cmp(temp_reg, G5_ic_reg); 1630 __ cmp(temp_reg, G5_ic_reg);
1631 // Branch to miss code, checks xcc or icc depending 1631 // Branch to miss code, checks xcc or icc depending
1632 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1632 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
4147 %} 4147 %}
4148 %} 4148 %}
4149 4149
4150 //----------OPERAND CLASSES---------------------------------------------------- 4150 //----------OPERAND CLASSES----------------------------------------------------
4151 // Operand Classes are groups of operands that are used to simplify 4151 // Operand Classes are groups of operands that are used to simplify
4152 // instruction definitions by not requiring the AD writer to specify seperate 4152 // instruction definitions by not requiring the AD writer to specify separate
4153 // instructions for every form of operand when the instruction accepts 4153 // instructions for every form of operand when the instruction accepts
4154 // multiple operand types with the same basic encoding and format. The classic 4154 // multiple operand types with the same basic encoding and format. The classic
4155 // case of this is memory operands. 4155 // case of this is memory operands.
4156 // Indirect is not included since its use is limited to Compare & Swap 4156 // Indirect is not included since its use is limited to Compare & Swap
4157 opclass memory( indirect, indOffset13, indIndex ); 4157 opclass memory( indirect, indOffset13, indIndex );
6845 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 6845 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
6846 ins_encode( enc_mul_hi(dst,src1,src2)); 6846 ins_encode( enc_mul_hi(dst,src1,src2));
6847 ins_pipe(sdiv_reg_reg); 6847 ins_pipe(sdiv_reg_reg);
6848 %} 6848 %}
6849 6849
6850 // Magic constant, reciprical of 10 6850 // Magic constant, reciprocal of 10
6851 instruct loadConI_x66666667(iRegIsafe dst) %{ 6851 instruct loadConI_x66666667(iRegIsafe dst) %{
6852 effect( DEF dst ); 6852 effect( DEF dst );
6853 6853
6854 size(8); 6854 size(8);
6855 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 6855 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
6856 ins_encode( Set32(0x66666667, dst) ); 6856 ins_encode( Set32(0x66666667, dst) );
6857 ins_pipe(ialu_hi_lo_reg); 6857 ins_pipe(ialu_hi_lo_reg);
6858 %} 6858 %}
6859 6859
6860 // Register Shift Right Arithmatic Long by 32-63 6860 // Register Shift Right Arithmetic Long by 32-63
6861 instruct sra_31( iRegI dst, iRegI src ) %{ 6861 instruct sra_31( iRegI dst, iRegI src ) %{
6862 effect( DEF dst, USE src ); 6862 effect( DEF dst, USE src );
6863 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 6863 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
6864 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 6864 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
6865 ins_pipe(ialu_reg_reg); 6865 ins_pipe(ialu_reg_reg);
9046 9046
9047 //----------PEEPHOLE RULES----------------------------------------------------- 9047 //----------PEEPHOLE RULES-----------------------------------------------------
9048 // These must follow all instruction definitions as they use the names 9048 // These must follow all instruction definitions as they use the names
9049 // defined in the instructions definitions. 9049 // defined in the instructions definitions.
9050 // 9050 //
9051 // peepmatch ( root_instr_name [preceeding_instruction]* ); 9051 // peepmatch ( root_instr_name [preceding_instruction]* );
9052 // 9052 //
9053 // peepconstraint %{ 9053 // peepconstraint %{
9054 // (instruction_number.operand_name relational_op instruction_number.operand_name 9054 // (instruction_number.operand_name relational_op instruction_number.operand_name
9055 // [, ...] ); 9055 // [, ...] );
9056 // // instruction numbers are zero-based using left to right order in peepmatch 9056 // // instruction numbers are zero-based using left to right order in peepmatch