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comparison src/cpu/x86/vm/x86_32.ad @ 605:98cb887364d3

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6810672: Comment typos Summary: I have collected some typos I have found while looking at the code. Reviewed-by: kvn, never
author twisti
date Fri, 27 Feb 2009 13:27:09 -0800
parents dca06e7f503d
children 56aae7be60d4
comparison
equal deleted inserted replaced
604:ec59443af135 605:98cb887364d3
128 128
129 // Specify priority of register selection within phases of register 129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to 130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine 131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as 132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundry (witness the FPR#L's in this list). 133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are 134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP. 135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, 136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, 137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, 138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
5855 %} 5855 %}
5856 %} 5856 %}
5857 5857
5858 //----------OPERAND CLASSES---------------------------------------------------- 5858 //----------OPERAND CLASSES----------------------------------------------------
5859 // Operand Classes are groups of operands that are used as to simplify 5859 // Operand Classes are groups of operands that are used as to simplify
5860 // instruction definitions by not requiring the AD writer to specify seperate 5860 // instruction definitions by not requiring the AD writer to specify separate
5861 // instructions for every form of operand when the instruction accepts 5861 // instructions for every form of operand when the instruction accepts
5862 // multiple operand types with the same basic encoding and format. The classic 5862 // multiple operand types with the same basic encoding and format. The classic
5863 // case of this is memory operands. 5863 // case of this is memory operands.
5864 5864
5865 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, 5865 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
13218 13218
13219 //----------PEEPHOLE RULES----------------------------------------------------- 13219 //----------PEEPHOLE RULES-----------------------------------------------------
13220 // These must follow all instruction definitions as they use the names 13220 // These must follow all instruction definitions as they use the names
13221 // defined in the instructions definitions. 13221 // defined in the instructions definitions.
13222 // 13222 //
13223 // peepmatch ( root_instr_name [preceeding_instruction]* ); 13223 // peepmatch ( root_instr_name [preceding_instruction]* );
13224 // 13224 //
13225 // peepconstraint %{ 13225 // peepconstraint %{
13226 // (instruction_number.operand_name relational_op instruction_number.operand_name 13226 // (instruction_number.operand_name relational_op instruction_number.operand_name
13227 // [, ...] ); 13227 // [, ...] );
13228 // // instruction numbers are zero-based using left to right order in peepmatch 13228 // // instruction numbers are zero-based using left to right order in peepmatch