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comparison src/cpu/x86/vm/x86_32.ad @ 4950:9b8ce46870df

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7145346: VerifyStackAtCalls is broken Summary: Replace call_epilog() encoding with macroassembler use. Moved duplicated code to x86.ad. Fixed return_addr() definition. Reviewed-by: never
author kvn
date Thu, 16 Feb 2012 17:12:49 -0800
parents fd8114661503
children 61b82be3b1ff
comparison
equal deleted inserted replaced
4949:ad3b47344802 4950:9b8ce46870df
1 // 1 //
2 // Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. 2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 // 4 //
5 // This code is free software; you can redistribute it and/or modify it 5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as 6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation. 7 // published by the Free Software Foundation.
338 current_offset += pre_call_FPU_size(); // skip fldcw, if any 338 current_offset += pre_call_FPU_size(); // skip fldcw, if any
339 current_offset += 5; // skip MOV instruction 339 current_offset += 5; // skip MOV instruction
340 current_offset += 1; // skip call opcode byte 340 current_offset += 1; // skip call opcode byte
341 return round_to(current_offset, alignment_required()) - current_offset; 341 return round_to(current_offset, alignment_required()) - current_offset;
342 } 342 }
343
344 #ifndef PRODUCT
345 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
346 st->print("INT3");
347 }
348 #endif
349 343
350 // EMIT_RM() 344 // EMIT_RM()
351 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { 345 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
352 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); 346 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
353 cbuf.insts()->emit_int8(c); 347 cbuf.insts()->emit_int8(c);
1115 1109
1116 Unimplemented(); 1110 Unimplemented();
1117 } 1111 }
1118 1112
1119 #ifndef PRODUCT 1113 #ifndef PRODUCT
1120 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 1114 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1121 implementation( NULL, ra_, false, st ); 1115 implementation( NULL, ra_, false, st );
1122 } 1116 }
1123 #endif 1117 #endif
1124 1118
1125 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1119 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1126 implementation( &cbuf, ra_, false, NULL ); 1120 implementation( &cbuf, ra_, false, NULL );
1127 } 1121 }
1128 1122
1129 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1123 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1130 return implementation( NULL, ra_, true, NULL ); 1124 return implementation( NULL, ra_, true, NULL );
1131 }
1132
1133 //=============================================================================
1134 #ifndef PRODUCT
1135 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1136 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1137 }
1138 #endif
1139
1140 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1141 MacroAssembler _masm(&cbuf);
1142 __ nop(_count);
1143 }
1144
1145 uint MachNopNode::size(PhaseRegAlloc *) const {
1146 return _count;
1147 } 1125 }
1148 1126
1149 1127
1150 //============================================================================= 1128 //=============================================================================
1151 #ifndef PRODUCT 1129 #ifndef PRODUCT
1827 // If method sets FPU control word do it here also 1805 // If method sets FPU control word do it here also
1828 if( Compile::current()->in_24_bit_fp_mode() ) { 1806 if( Compile::current()->in_24_bit_fp_mode() ) {
1829 MacroAssembler masm(&cbuf); 1807 MacroAssembler masm(&cbuf);
1830 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 1808 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1831 } 1809 }
1832 %}
1833
1834 enc_class preserve_SP %{
1835 debug_only(int off0 = cbuf.insts_size());
1836 MacroAssembler _masm(&cbuf);
1837 // RBP is preserved across all calls, even compiled calls.
1838 // Use it to preserve RSP in places where the callee might change the SP.
1839 __ movptr(rbp_mh_SP_save, rsp);
1840 debug_only(int off1 = cbuf.insts_size());
1841 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
1842 %}
1843
1844 enc_class restore_SP %{
1845 MacroAssembler _masm(&cbuf);
1846 __ movptr(rsp, rbp_mh_SP_save);
1847 %} 1810 %}
1848 1811
1849 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 1812 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1850 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 1813 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1851 // who we intended to call. 1814 // who we intended to call.
3792 // representing the register number (i.e. - use a register name) or 3755 // representing the register number (i.e. - use a register name) or
3793 // stack slot. 3756 // stack slot.
3794 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. 3757 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3795 // Otherwise, it is above the locks and verification slot and alignment word 3758 // Otherwise, it is above the locks and verification slot and alignment word
3796 return_addr(STACK - 1 + 3759 return_addr(STACK - 1 +
3797 round_to(1+VerifyStackAtCalls+ 3760 round_to((Compile::current()->in_preserve_stack_slots() +
3798 Compile::current()->fixed_slots(), 3761 Compile::current()->fixed_slots()),
3799 (StackAlignmentInBytes/wordSize))); 3762 stack_alignment_in_slots()));
3800 3763
3801 // Body of function which returns an integer array locating 3764 // Body of function which returns an integer array locating
3802 // arguments either in registers or in stack slots. Passed an array 3765 // arguments either in registers or in stack slots. Passed an array
3803 // of ideal registers called "sig" and a "length" count. Stack-slot 3766 // of ideal registers called "sig" and a "length" count. Stack-slot
3804 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3767 // offsets are based on outgoing arguments, i.e. a CALLER setting up
13421 ins_cost(125); 13384 ins_cost(125);
13422 size(6) ; 13385 size(6) ;
13423 ins_encode( Safepoint_Poll() ); 13386 ins_encode( Safepoint_Poll() );
13424 ins_pipe( ialu_reg_mem ); 13387 ins_pipe( ialu_reg_mem );
13425 %} 13388 %}
13389
13390
13391 // ============================================================================
13392 // This name is KNOWN by the ADLC and cannot be changed.
13393 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13394 // for this guy.
13395 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13396 match(Set dst (ThreadLocal));
13397 effect(DEF dst, KILL cr);
13398
13399 format %{ "MOV $dst, Thread::current()" %}
13400 ins_encode %{
13401 Register dstReg = as_Register($dst$$reg);
13402 __ get_thread(dstReg);
13403 %}
13404 ins_pipe( ialu_reg_fat );
13405 %}
13406
13407
13426 13408
13427 //----------PEEPHOLE RULES----------------------------------------------------- 13409 //----------PEEPHOLE RULES-----------------------------------------------------
13428 // These must follow all instruction definitions as they use the names 13410 // These must follow all instruction definitions as they use the names
13429 // defined in the instructions definitions. 13411 // defined in the instructions definitions.
13430 // 13412 //