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comparison src/cpu/x86/vm/vm_version_x86.hpp @ 14693:9e9af3aa4278

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8031321: Support Intel bit manipulation instructions Summary: Add support for BMI1 instructions Reviewed-by: kvn, roland
author iveresov
date Wed, 12 Mar 2014 11:24:26 -0700
parents b800986664f4
children b51e29501f30 98af1e198e73
comparison
equal deleted inserted replaced
14692:8504393de66b 14693:9e9af3aa4278
139 union ExtCpuid1Ecx { 139 union ExtCpuid1Ecx {
140 uint32_t value; 140 uint32_t value;
141 struct { 141 struct {
142 uint32_t LahfSahf : 1, 142 uint32_t LahfSahf : 1,
143 CmpLegacy : 1, 143 CmpLegacy : 1,
144 : 4, 144 : 3,
145 lzcnt_intel : 1,
145 lzcnt : 1, 146 lzcnt : 1,
146 sse4a : 1, 147 sse4a : 1,
147 misalignsse : 1, 148 misalignsse : 1,
148 prefetchw : 1, 149 prefetchw : 1,
149 : 22; 150 : 22;
249 CPU_TSCINV = (1 << 16), 250 CPU_TSCINV = (1 << 16),
250 CPU_AVX = (1 << 17), 251 CPU_AVX = (1 << 17),
251 CPU_AVX2 = (1 << 18), 252 CPU_AVX2 = (1 << 18),
252 CPU_AES = (1 << 19), 253 CPU_AES = (1 << 19),
253 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions 254 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions
254 CPU_CLMUL = (1 << 21) // carryless multiply for CRC 255 CPU_CLMUL = (1 << 21), // carryless multiply for CRC
256 CPU_BMI1 = (1 << 22),
257 CPU_BMI2 = (1 << 23)
255 } cpuFeatureFlags; 258 } cpuFeatureFlags;
256 259
257 enum { 260 enum {
258 // AMD 261 // AMD
259 CPU_FAMILY_AMD_11H = 0x11, 262 CPU_FAMILY_AMD_11H = 0x11,
421 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { 424 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
422 result |= CPU_AVX; 425 result |= CPU_AVX;
423 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) 426 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
424 result |= CPU_AVX2; 427 result |= CPU_AVX2;
425 } 428 }
429 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
430 result |= CPU_BMI1;
426 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) 431 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
427 result |= CPU_TSC; 432 result |= CPU_TSC;
428 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) 433 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
429 result |= CPU_TSCINV; 434 result |= CPU_TSCINV;
430 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) 435 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
441 result |= CPU_3DNOW_PREFETCH; 446 result |= CPU_3DNOW_PREFETCH;
442 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) 447 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
443 result |= CPU_LZCNT; 448 result |= CPU_LZCNT;
444 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) 449 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
445 result |= CPU_SSE4A; 450 result |= CPU_SSE4A;
451 }
452 // Intel features.
453 if(is_intel()) {
454 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
455 result |= CPU_BMI2;
456 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
457 result |= CPU_LZCNT;
446 } 458 }
447 459
448 return result; 460 return result;
449 } 461 }
450 462
558 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } 570 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; }
559 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } 571 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; }
560 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; } 572 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; }
561 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; } 573 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; }
562 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; } 574 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; }
563 575 static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; }
576 static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; }
564 // Intel features 577 // Intel features
565 static bool is_intel_family_core() { return is_intel() && 578 static bool is_intel_family_core() { return is_intel() &&
566 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } 579 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
567 580
568 static bool is_intel_tsc_synched_at_init() { 581 static bool is_intel_tsc_synched_at_init() {