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comparison src/cpu/x86/vm/x86_64.ad @ 14693:9e9af3aa4278

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8031321: Support Intel bit manipulation instructions Summary: Add support for BMI1 instructions Reviewed-by: kvn, roland
author iveresov
date Wed, 12 Mar 2014 11:24:26 -0700
parents cd5d10655495
children 92aa6797d639
comparison
equal deleted inserted replaced
14692:8504393de66b 14693:9e9af3aa4278
6020 %} 6020 %}
6021 ins_pipe(ialu_reg); 6021 ins_pipe(ialu_reg);
6022 %} 6022 %}
6023 6023
6024 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ 6024 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6025 predicate(UseCountTrailingZerosInstruction);
6026 match(Set dst (CountTrailingZerosI src));
6027 effect(KILL cr);
6028
6029 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6030 ins_encode %{
6031 __ tzcntl($dst$$Register, $src$$Register);
6032 %}
6033 ins_pipe(ialu_reg);
6034 %}
6035
6036 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6037 predicate(!UseCountTrailingZerosInstruction);
6025 match(Set dst (CountTrailingZerosI src)); 6038 match(Set dst (CountTrailingZerosI src));
6026 effect(KILL cr); 6039 effect(KILL cr);
6027 6040
6028 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t" 6041 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6029 "jnz done\n\t" 6042 "jnz done\n\t"
6039 %} 6052 %}
6040 ins_pipe(ialu_reg); 6053 ins_pipe(ialu_reg);
6041 %} 6054 %}
6042 6055
6043 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ 6056 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6057 predicate(UseCountTrailingZerosInstruction);
6058 match(Set dst (CountTrailingZerosL src));
6059 effect(KILL cr);
6060
6061 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6062 ins_encode %{
6063 __ tzcntq($dst$$Register, $src$$Register);
6064 %}
6065 ins_pipe(ialu_reg);
6066 %}
6067
6068 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6069 predicate(!UseCountTrailingZerosInstruction);
6044 match(Set dst (CountTrailingZerosL src)); 6070 match(Set dst (CountTrailingZerosL src));
6045 effect(KILL cr); 6071 effect(KILL cr);
6046 6072
6047 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t" 6073 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6048 "jnz done\n\t" 6074 "jnz done\n\t"
8620 ins_encode(REX_mem(dst), OpcSE(src), 8646 ins_encode(REX_mem(dst), OpcSE(src),
8621 RM_opc_mem(secondary, dst), Con8or32(src)); 8647 RM_opc_mem(secondary, dst), Con8or32(src));
8622 ins_pipe(ialu_mem_imm); 8648 ins_pipe(ialu_mem_imm);
8623 %} 8649 %}
8624 8650
8651 // BMI1 instructions
8652 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
8653 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
8654 predicate(UseBMI1Instructions);
8655 effect(KILL cr);
8656
8657 ins_cost(125);
8658 format %{ "andnl $dst, $src1, $src2" %}
8659
8660 ins_encode %{
8661 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8662 %}
8663 ins_pipe(ialu_reg_mem);
8664 %}
8665
8666 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
8667 match(Set dst (AndI (XorI src1 minus_1) src2));
8668 predicate(UseBMI1Instructions);
8669 effect(KILL cr);
8670
8671 format %{ "andnl $dst, $src1, $src2" %}
8672
8673 ins_encode %{
8674 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8675 %}
8676 ins_pipe(ialu_reg);
8677 %}
8678
8679 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
8680 match(Set dst (AndI (SubI imm_zero src) src));
8681 predicate(UseBMI1Instructions);
8682 effect(KILL cr);
8683
8684 format %{ "blsil $dst, $src" %}
8685
8686 ins_encode %{
8687 __ blsil($dst$$Register, $src$$Register);
8688 %}
8689 ins_pipe(ialu_reg);
8690 %}
8691
8692 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
8693 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8694 predicate(UseBMI1Instructions);
8695 effect(KILL cr);
8696
8697 ins_cost(125);
8698 format %{ "blsil $dst, $src" %}
8699
8700 ins_encode %{
8701 __ blsil($dst$$Register, $src$$Address);
8702 %}
8703 ins_pipe(ialu_reg_mem);
8704 %}
8705
8706 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
8707 %{
8708 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
8709 predicate(UseBMI1Instructions);
8710 effect(KILL cr);
8711
8712 ins_cost(125);
8713 format %{ "blsmskl $dst, $src" %}
8714
8715 ins_encode %{
8716 __ blsmskl($dst$$Register, $src$$Address);
8717 %}
8718 ins_pipe(ialu_reg_mem);
8719 %}
8720
8721 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
8722 %{
8723 match(Set dst (XorI (AddI src minus_1) src));
8724 predicate(UseBMI1Instructions);
8725 effect(KILL cr);
8726
8727 format %{ "blsmskl $dst, $src" %}
8728
8729 ins_encode %{
8730 __ blsmskl($dst$$Register, $src$$Register);
8731 %}
8732
8733 ins_pipe(ialu_reg);
8734 %}
8735
8736 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
8737 %{
8738 match(Set dst (AndI (AddI src minus_1) src) );
8739 predicate(UseBMI1Instructions);
8740 effect(KILL cr);
8741
8742 format %{ "blsrl $dst, $src" %}
8743
8744 ins_encode %{
8745 __ blsrl($dst$$Register, $src$$Register);
8746 %}
8747
8748 ins_pipe(ialu_reg_mem);
8749 %}
8750
8751 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
8752 %{
8753 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
8754 predicate(UseBMI1Instructions);
8755 effect(KILL cr);
8756
8757 ins_cost(125);
8758 format %{ "blsrl $dst, $src" %}
8759
8760 ins_encode %{
8761 __ blsrl($dst$$Register, $src$$Address);
8762 %}
8763
8764 ins_pipe(ialu_reg);
8765 %}
8766
8625 // Or Instructions 8767 // Or Instructions
8626 // Or Register with Register 8768 // Or Register with Register
8627 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) 8769 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8628 %{ 8770 %{
8629 match(Set dst (OrI dst src)); 8771 match(Set dst (OrI dst src));
8849 format %{ "andq $dst, $src\t# long" %} 8991 format %{ "andq $dst, $src\t# long" %}
8850 opcode(0x81, 0x4); /* Opcode 81 /4 id */ 8992 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8851 ins_encode(REX_mem_wide(dst), OpcSE(src), 8993 ins_encode(REX_mem_wide(dst), OpcSE(src),
8852 RM_opc_mem(secondary, dst), Con8or32(src)); 8994 RM_opc_mem(secondary, dst), Con8or32(src));
8853 ins_pipe(ialu_mem_imm); 8995 ins_pipe(ialu_mem_imm);
8996 %}
8997
8998 // BMI1 instructions
8999 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9000 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9001 predicate(UseBMI1Instructions);
9002 effect(KILL cr);
9003
9004 ins_cost(125);
9005 format %{ "andnq $dst, $src1, $src2" %}
9006
9007 ins_encode %{
9008 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9009 %}
9010 ins_pipe(ialu_reg_mem);
9011 %}
9012
9013 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9014 match(Set dst (AndL (XorL src1 minus_1) src2));
9015 predicate(UseBMI1Instructions);
9016 effect(KILL cr);
9017
9018 format %{ "andnq $dst, $src1, $src2" %}
9019
9020 ins_encode %{
9021 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9022 %}
9023 ins_pipe(ialu_reg_mem);
9024 %}
9025
9026 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9027 match(Set dst (AndL (SubL imm_zero src) src));
9028 predicate(UseBMI1Instructions);
9029 effect(KILL cr);
9030
9031 format %{ "blsiq $dst, $src" %}
9032
9033 ins_encode %{
9034 __ blsiq($dst$$Register, $src$$Register);
9035 %}
9036 ins_pipe(ialu_reg);
9037 %}
9038
9039 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9040 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9041 predicate(UseBMI1Instructions);
9042 effect(KILL cr);
9043
9044 ins_cost(125);
9045 format %{ "blsiq $dst, $src" %}
9046
9047 ins_encode %{
9048 __ blsiq($dst$$Register, $src$$Address);
9049 %}
9050 ins_pipe(ialu_reg_mem);
9051 %}
9052
9053 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9054 %{
9055 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9056 predicate(UseBMI1Instructions);
9057 effect(KILL cr);
9058
9059 ins_cost(125);
9060 format %{ "blsmskq $dst, $src" %}
9061
9062 ins_encode %{
9063 __ blsmskq($dst$$Register, $src$$Address);
9064 %}
9065 ins_pipe(ialu_reg_mem);
9066 %}
9067
9068 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9069 %{
9070 match(Set dst (XorL (AddL src minus_1) src));
9071 predicate(UseBMI1Instructions);
9072 effect(KILL cr);
9073
9074 format %{ "blsmskq $dst, $src" %}
9075
9076 ins_encode %{
9077 __ blsmskq($dst$$Register, $src$$Register);
9078 %}
9079
9080 ins_pipe(ialu_reg);
9081 %}
9082
9083 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9084 %{
9085 match(Set dst (AndL (AddL src minus_1) src) );
9086 predicate(UseBMI1Instructions);
9087 effect(KILL cr);
9088
9089 format %{ "blsrq $dst, $src" %}
9090
9091 ins_encode %{
9092 __ blsrq($dst$$Register, $src$$Register);
9093 %}
9094
9095 ins_pipe(ialu_reg);
9096 %}
9097
9098 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9099 %{
9100 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9101 predicate(UseBMI1Instructions);
9102 effect(KILL cr);
9103
9104 ins_cost(125);
9105 format %{ "blsrq $dst, $src" %}
9106
9107 ins_encode %{
9108 __ blsrq($dst$$Register, $src$$Address);
9109 %}
9110
9111 ins_pipe(ialu_reg);
8854 %} 9112 %}
8855 9113
8856 // Or Instructions 9114 // Or Instructions
8857 // Or Register with Register 9115 // Or Register with Register
8858 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) 9116 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)