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comparison src/cpu/x86/vm/assembler_x86.cpp @ 6894:a3ecd773a7b9

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7184394: add intrinsics to use AES instructions Summary: Use new x86 AES instructions for AESCrypt. Reviewed-by: twisti, kvn, roland Contributed-by: tom.deneau@amd.com
author kvn
date Wed, 24 Oct 2012 14:33:22 -0700
parents d804e148cff8
children e522a00b91aa 6ab62ad83507
comparison
equal deleted inserted replaced
6893:b2c669fd8114 6894:a3ecd773a7b9
1005 void Assembler::addss(XMMRegister dst, Address src) { 1005 void Assembler::addss(XMMRegister dst, Address src) {
1006 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1006 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1007 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); 1007 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1008 } 1008 }
1009 1009
1010 void Assembler::aesdec(XMMRegister dst, Address src) {
1011 assert(VM_Version::supports_aes(), "");
1012 InstructionMark im(this);
1013 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1014 emit_byte(0xde);
1015 emit_operand(dst, src);
1016 }
1017
1018 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1019 assert(VM_Version::supports_aes(), "");
1020 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1021 emit_byte(0xde);
1022 emit_byte(0xC0 | encode);
1023 }
1024
1025 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1026 assert(VM_Version::supports_aes(), "");
1027 InstructionMark im(this);
1028 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1029 emit_byte(0xdf);
1030 emit_operand(dst, src);
1031 }
1032
1033 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1034 assert(VM_Version::supports_aes(), "");
1035 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1036 emit_byte(0xdf);
1037 emit_byte(0xC0 | encode);
1038 }
1039
1040 void Assembler::aesenc(XMMRegister dst, Address src) {
1041 assert(VM_Version::supports_aes(), "");
1042 InstructionMark im(this);
1043 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1044 emit_byte(0xdc);
1045 emit_operand(dst, src);
1046 }
1047
1048 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1049 assert(VM_Version::supports_aes(), "");
1050 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1051 emit_byte(0xdc);
1052 emit_byte(0xC0 | encode);
1053 }
1054
1055 void Assembler::aesenclast(XMMRegister dst, Address src) {
1056 assert(VM_Version::supports_aes(), "");
1057 InstructionMark im(this);
1058 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1059 emit_byte(0xdd);
1060 emit_operand(dst, src);
1061 }
1062
1063 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1064 assert(VM_Version::supports_aes(), "");
1065 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1066 emit_byte(0xdd);
1067 emit_byte(0xC0 | encode);
1068 }
1069
1070
1010 void Assembler::andl(Address dst, int32_t imm32) { 1071 void Assembler::andl(Address dst, int32_t imm32) {
1011 InstructionMark im(this); 1072 InstructionMark im(this);
1012 prefix(dst); 1073 prefix(dst);
1013 emit_byte(0x81); 1074 emit_byte(0x81);
1014 emit_operand(rsp, dst, 4); 1075 emit_operand(rsp, dst, 4);
2305 2366
2306 void Assembler::prefix(Prefix p) { 2367 void Assembler::prefix(Prefix p) {
2307 a_byte(p); 2368 a_byte(p);
2308 } 2369 }
2309 2370
2371 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
2372 assert(VM_Version::supports_ssse3(), "");
2373 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2374 emit_byte(0x00);
2375 emit_byte(0xC0 | encode);
2376 }
2377
2378 void Assembler::pshufb(XMMRegister dst, Address src) {
2379 assert(VM_Version::supports_ssse3(), "");
2380 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2381 InstructionMark im(this);
2382 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2383 emit_byte(0x00);
2384 emit_operand(dst, src);
2385 }
2386
2310 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { 2387 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2311 assert(isByte(mode), "invalid value"); 2388 assert(isByte(mode), "invalid value");
2312 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2389 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2313 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66); 2390 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
2314 emit_byte(mode & 0xFF); 2391 emit_byte(mode & 0xFF);
8065 8142
8066 void MacroAssembler::movptr(Address dst, Register src) { 8143 void MacroAssembler::movptr(Address dst, Register src) {
8067 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 8144 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
8068 } 8145 }
8069 8146
8147 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
8148 if (reachable(src)) {
8149 Assembler::movdqu(dst, as_Address(src));
8150 } else {
8151 lea(rscratch1, src);
8152 Assembler::movdqu(dst, Address(rscratch1, 0));
8153 }
8154 }
8155
8070 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { 8156 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
8071 if (reachable(src)) { 8157 if (reachable(src)) {
8072 Assembler::movsd(dst, as_Address(src)); 8158 Assembler::movsd(dst, as_Address(src));
8073 } else { 8159 } else {
8074 lea(rscratch1, src); 8160 lea(rscratch1, src);
8352 if (reachable(src)) { 8438 if (reachable(src)) {
8353 Assembler::xorps(dst, as_Address(src)); 8439 Assembler::xorps(dst, as_Address(src));
8354 } else { 8440 } else {
8355 lea(rscratch1, src); 8441 lea(rscratch1, src);
8356 Assembler::xorps(dst, Address(rscratch1, 0)); 8442 Assembler::xorps(dst, Address(rscratch1, 0));
8443 }
8444 }
8445
8446 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
8447 // Used in sign-bit flipping with aligned address.
8448 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
8449 if (reachable(src)) {
8450 Assembler::pshufb(dst, as_Address(src));
8451 } else {
8452 lea(rscratch1, src);
8453 Assembler::pshufb(dst, Address(rscratch1, 0));
8357 } 8454 }
8358 } 8455 }
8359 8456
8360 // AVX 3-operands instructions 8457 // AVX 3-operands instructions
8361 8458