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comparison src/cpu/sparc/vm/assembler_sparc.inline.hpp @ 0:a61af66fc99e jdk7-b24

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author duke
date Sat, 01 Dec 2007 00:00:00 +0000
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1 /*
2 * Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
26 jint& stub_inst = *(jint*) branch;
27 stub_inst = patched_branch(target - branch, stub_inst, 0);
28 }
29
30 #ifndef PRODUCT
31 inline void MacroAssembler::pd_print_patched_instruction(address branch) {
32 jint stub_inst = *(jint*) branch;
33 print_instruction(stub_inst);
34 ::tty->print("%s", " (unresolved)");
35 }
36 #endif // PRODUCT
37
38 inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); }
39
40
41 // inlines for SPARC assembler -- dmu 5/97
42
43 inline void Assembler::check_delay() {
44 # ifdef CHECK_DELAY
45 guarantee( delay_state != at_delay_slot, "must say delayed() when filling delay slot");
46 delay_state = no_delay;
47 # endif
48 }
49
50 inline void Assembler::emit_long(int x) {
51 check_delay();
52 AbstractAssembler::emit_long(x);
53 }
54
55 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) {
56 relocate(rtype);
57 emit_long(x);
58 }
59
60 inline void Assembler::emit_data(int x, RelocationHolder const& rspec) {
61 relocate(rspec);
62 emit_long(x);
63 }
64
65
66 inline void Assembler::add( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2) ); }
67 inline void Assembler::add( Register s1, int simm13a, Register d, relocInfo::relocType rtype ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rtype ); }
68 inline void Assembler::add( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec ); }
69 inline void Assembler::add( const Address& a, Register d, int offset) { add( a.base(), a.disp() + offset, d, a.rspec(offset)); }
70
71 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt); has_delay_slot(); }
72 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { bpr( c, a, p, s1, target(L)); }
73
74 inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
75 inline void Assembler::fb( Condition c, bool a, Label& L ) { fb(c, a, target(L)); }
76
77 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); }
78 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { fbp(c, a, cc, p, target(L)); }
79
80 inline void Assembler::cb( Condition c, bool a, address d, relocInfo::relocType rt ) { v8_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(cb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
81 inline void Assembler::cb( Condition c, bool a, Label& L ) { cb(c, a, target(L)); }
82
83 inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
84 inline void Assembler::br( Condition c, bool a, Label& L ) { br(c, a, target(L)); }
85
86 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); }
87 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { bp(c, a, cc, p, target(L)); }
88
89 inline void Assembler::call( address d, relocInfo::relocType rt ) { emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt); has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); }
90 inline void Assembler::call( Label& L, relocInfo::relocType rt ) { call( target(L), rt); }
91
92 inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); }
93 inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
94
95 inline void Assembler::jmpl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
96 inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); has_delay_slot(); }
97
98 inline void Assembler::jmpl( Address& a, Register d, int offset) { jmpl( a.base(), a.disp() + offset, d, a.rspec(offset)); }
99
100
101 inline void Assembler::ldf( FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); }
102 inline void Assembler::ldf( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
103
104 inline void Assembler::ldf( FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) { relocate(a.rspec(offset)); ldf( w, a.base(), a.disp() + offset, d); }
105
106 inline void Assembler::ldfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
107 inline void Assembler::ldfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
108 inline void Assembler::ldxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
109 inline void Assembler::ldxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
110
111 inline void Assembler::ldc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | rs2(s2) ); }
112 inline void Assembler::ldc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
113 inline void Assembler::lddc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | rs2(s2) ); }
114 inline void Assembler::lddc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
115 inline void Assembler::ldcsr( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | rs2(s2) ); }
116 inline void Assembler::ldcsr( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
117
118 inline void Assembler::ldsb( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2) ); }
119 inline void Assembler::ldsb( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
120
121 inline void Assembler::ldsh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2) ); }
122 inline void Assembler::ldsh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
123 inline void Assembler::ldsw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2) ); }
124 inline void Assembler::ldsw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
125 inline void Assembler::ldub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2) ); }
126 inline void Assembler::ldub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
127 inline void Assembler::lduh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2) ); }
128 inline void Assembler::lduh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
129 inline void Assembler::lduw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2) ); }
130 inline void Assembler::lduw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
131
132 inline void Assembler::ldx( Register s1, Register s2, Register d) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2) ); }
133 inline void Assembler::ldx( Register s1, int simm13a, Register d) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
134 inline void Assembler::ldd( Register s1, Register s2, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2) ); }
135 inline void Assembler::ldd( Register s1, int simm13a, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
136
137 #ifdef _LP64
138 // Make all 32 bit loads signed so 64 bit registers maintain proper sign
139 inline void Assembler::ld( Register s1, Register s2, Register d) { ldsw( s1, s2, d); }
140 inline void Assembler::ld( Register s1, int simm13a, Register d) { ldsw( s1, simm13a, d); }
141 #else
142 inline void Assembler::ld( Register s1, Register s2, Register d) { lduw( s1, s2, d); }
143 inline void Assembler::ld( Register s1, int simm13a, Register d) { lduw( s1, simm13a, d); }
144 #endif
145
146
147 inline void Assembler::ld( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ld( a.base(), a.disp() + offset, d ); }
148 inline void Assembler::ldsb( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsb( a.base(), a.disp() + offset, d ); }
149 inline void Assembler::ldsh( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsh( a.base(), a.disp() + offset, d ); }
150 inline void Assembler::ldsw( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsw( a.base(), a.disp() + offset, d ); }
151 inline void Assembler::ldub( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldub( a.base(), a.disp() + offset, d ); }
152 inline void Assembler::lduh( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); lduh( a.base(), a.disp() + offset, d ); }
153 inline void Assembler::lduw( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); lduw( a.base(), a.disp() + offset, d ); }
154 inline void Assembler::ldd( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldd( a.base(), a.disp() + offset, d ); }
155 inline void Assembler::ldx( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldx( a.base(), a.disp() + offset, d ); }
156
157
158 inline void Assembler::ldstub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | rs2(s2) ); }
159 inline void Assembler::ldstub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
160
161
162 inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
163 inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
164
165 inline void Assembler::prefetch(const Address& a, PrefetchFcn f, int offset) { v9_only(); relocate(a.rspec(offset)); prefetch(a.base(), a.disp() + offset, f); }
166
167
168 inline void Assembler::rett( Register s1, Register s2 ) { emit_long( op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
169 inline void Assembler::rett( Register s1, int simm13a, relocInfo::relocType rt) { emit_data( op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); has_delay_slot(); }
170
171 inline void Assembler::sethi( int imm22a, Register d, RelocationHolder const& rspec ) { emit_data( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); }
172
173 // pp 222
174
175 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2) ); }
176 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
177
178 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) { relocate(a.rspec(offset)); stf(w, d, a.base(), a.disp() + offset); }
179
180 inline void Assembler::stfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
181 inline void Assembler::stfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
182 inline void Assembler::stxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
183 inline void Assembler::stxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
184
185 // p 226
186
187 inline void Assembler::stb( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2) ); }
188 inline void Assembler::stb( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
189 inline void Assembler::sth( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2) ); }
190 inline void Assembler::sth( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
191 inline void Assembler::stw( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2) ); }
192 inline void Assembler::stw( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
193
194
195 inline void Assembler::stx( Register d, Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2) ); }
196 inline void Assembler::stx( Register d, Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
197 inline void Assembler::std( Register d, Register s1, Register s2) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2) ); }
198 inline void Assembler::std( Register d, Register s1, int simm13a) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
199
200 inline void Assembler::st( Register d, Register s1, Register s2) { stw(d, s1, s2); }
201 inline void Assembler::st( Register d, Register s1, int simm13a) { stw(d, s1, simm13a); }
202
203 inline void Assembler::stb( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stb( d, a.base(), a.disp() + offset); }
204 inline void Assembler::sth( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); sth( d, a.base(), a.disp() + offset); }
205 inline void Assembler::stw( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stw( d, a.base(), a.disp() + offset); }
206 inline void Assembler::st( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); st( d, a.base(), a.disp() + offset); }
207 inline void Assembler::std( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); std( d, a.base(), a.disp() + offset); }
208 inline void Assembler::stx( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stx( d, a.base(), a.disp() + offset); }
209
210 // v8 p 99
211
212 inline void Assembler::stc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | rs2(s2) ); }
213 inline void Assembler::stc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
214 inline void Assembler::stdc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | rs2(s2) ); }
215 inline void Assembler::stdc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
216 inline void Assembler::stcsr( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | rs2(s2) ); }
217 inline void Assembler::stcsr( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
218 inline void Assembler::stdcq( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | rs2(s2) ); }
219 inline void Assembler::stdcq( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
220
221
222 // pp 231
223
224 inline void Assembler::swap( Register s1, Register s2, Register d) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2) ); }
225 inline void Assembler::swap( Register s1, int simm13a, Register d) { v9_dep(); emit_data( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
226
227 inline void Assembler::swap( Address& a, Register d, int offset ) { relocate(a.rspec(offset)); swap( a.base(), a.disp() + offset, d ); }
228
229
230 // Use the right loads/stores for the platform
231 inline void MacroAssembler::ld_ptr( Register s1, Register s2, Register d ) {
232 #ifdef _LP64
233 Assembler::ldx( s1, s2, d);
234 #else
235 Assembler::ld( s1, s2, d);
236 #endif
237 }
238
239 inline void MacroAssembler::ld_ptr( Register s1, int simm13a, Register d ) {
240 #ifdef _LP64
241 Assembler::ldx( s1, simm13a, d);
242 #else
243 Assembler::ld( s1, simm13a, d);
244 #endif
245 }
246
247 inline void MacroAssembler::ld_ptr( const Address& a, Register d, int offset ) {
248 #ifdef _LP64
249 Assembler::ldx( a, d, offset );
250 #else
251 Assembler::ld( a, d, offset );
252 #endif
253 }
254
255 inline void MacroAssembler::st_ptr( Register d, Register s1, Register s2 ) {
256 #ifdef _LP64
257 Assembler::stx( d, s1, s2);
258 #else
259 Assembler::st( d, s1, s2);
260 #endif
261 }
262
263 inline void MacroAssembler::st_ptr( Register d, Register s1, int simm13a ) {
264 #ifdef _LP64
265 Assembler::stx( d, s1, simm13a);
266 #else
267 Assembler::st( d, s1, simm13a);
268 #endif
269 }
270
271 inline void MacroAssembler::st_ptr( Register d, const Address& a, int offset) {
272 #ifdef _LP64
273 Assembler::stx( d, a, offset);
274 #else
275 Assembler::st( d, a, offset);
276 #endif
277 }
278
279 // Use the right loads/stores for the platform
280 inline void MacroAssembler::ld_long( Register s1, Register s2, Register d ) {
281 #ifdef _LP64
282 Assembler::ldx(s1, s2, d);
283 #else
284 Assembler::ldd(s1, s2, d);
285 #endif
286 }
287
288 inline void MacroAssembler::ld_long( Register s1, int simm13a, Register d ) {
289 #ifdef _LP64
290 Assembler::ldx(s1, simm13a, d);
291 #else
292 Assembler::ldd(s1, simm13a, d);
293 #endif
294 }
295
296 inline void MacroAssembler::ld_long( const Address& a, Register d, int offset ) {
297 #ifdef _LP64
298 Assembler::ldx(a, d, offset );
299 #else
300 Assembler::ldd(a, d, offset );
301 #endif
302 }
303
304 inline void MacroAssembler::st_long( Register d, Register s1, Register s2 ) {
305 #ifdef _LP64
306 Assembler::stx(d, s1, s2);
307 #else
308 Assembler::std(d, s1, s2);
309 #endif
310 }
311
312 inline void MacroAssembler::st_long( Register d, Register s1, int simm13a ) {
313 #ifdef _LP64
314 Assembler::stx(d, s1, simm13a);
315 #else
316 Assembler::std(d, s1, simm13a);
317 #endif
318 }
319
320 inline void MacroAssembler::st_long( Register d, const Address& a, int offset ) {
321 #ifdef _LP64
322 Assembler::stx(d, a, offset);
323 #else
324 Assembler::std(d, a, offset);
325 #endif
326 }
327
328 // Functions for isolating 64 bit shifts for LP64
329
330 inline void MacroAssembler::sll_ptr( Register s1, Register s2, Register d ) {
331 #ifdef _LP64
332 Assembler::sllx(s1, s2, d);
333 #else
334 Assembler::sll(s1, s2, d);
335 #endif
336 }
337
338 inline void MacroAssembler::sll_ptr( Register s1, int imm6a, Register d ) {
339 #ifdef _LP64
340 Assembler::sllx(s1, imm6a, d);
341 #else
342 Assembler::sll(s1, imm6a, d);
343 #endif
344 }
345
346 inline void MacroAssembler::srl_ptr( Register s1, Register s2, Register d ) {
347 #ifdef _LP64
348 Assembler::srlx(s1, s2, d);
349 #else
350 Assembler::srl(s1, s2, d);
351 #endif
352 }
353
354 inline void MacroAssembler::srl_ptr( Register s1, int imm6a, Register d ) {
355 #ifdef _LP64
356 Assembler::srlx(s1, imm6a, d);
357 #else
358 Assembler::srl(s1, imm6a, d);
359 #endif
360 }
361
362 // Use the right branch for the platform
363
364 inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
365 if (VM_Version::v9_instructions_work())
366 Assembler::bp(c, a, icc, p, d, rt);
367 else
368 Assembler::br(c, a, d, rt);
369 }
370
371 inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {
372 br(c, a, p, target(L));
373 }
374
375
376 // Branch that tests either xcc or icc depending on the
377 // architecture compiled (LP64 or not)
378 inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
379 #ifdef _LP64
380 Assembler::bp(c, a, xcc, p, d, rt);
381 #else
382 MacroAssembler::br(c, a, p, d, rt);
383 #endif
384 }
385
386 inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {
387 brx(c, a, p, target(L));
388 }
389
390 inline void MacroAssembler::ba( bool a, Label& L ) {
391 br(always, a, pt, L);
392 }
393
394 // Warning: V9 only functions
395 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
396 Assembler::bp(c, a, cc, p, d, rt);
397 }
398
399 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) {
400 Assembler::bp(c, a, cc, p, L);
401 }
402
403 inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
404 if (VM_Version::v9_instructions_work())
405 fbp(c, a, fcc0, p, d, rt);
406 else
407 Assembler::fb(c, a, d, rt);
408 }
409
410 inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {
411 fb(c, a, p, target(L));
412 }
413
414 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
415 Assembler::fbp(c, a, cc, p, d, rt);
416 }
417
418 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) {
419 Assembler::fbp(c, a, cc, p, L);
420 }
421
422 inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); }
423 inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); }
424
425 // Call with a check to see if we need to deal with the added
426 // expense of relocation and if we overflow the displacement
427 // of the quick call instruction./
428 // Check to see if we have to deal with relocations
429 inline void MacroAssembler::call( address d, relocInfo::relocType rt ) {
430 #ifdef _LP64
431 intptr_t disp;
432 // NULL is ok because it will be relocated later.
433 // Must change NULL to a reachable address in order to
434 // pass asserts here and in wdisp.
435 if ( d == NULL )
436 d = pc();
437
438 // Is this address within range of the call instruction?
439 // If not, use the expensive instruction sequence
440 disp = (intptr_t)d - (intptr_t)pc();
441 if ( disp != (intptr_t)(int32_t)disp ) {
442 relocate(rt);
443 Address dest(O7, (address)d);
444 sethi(dest, /*ForceRelocatable=*/ true);
445 jmpl(dest, O7);
446 }
447 else {
448 Assembler::call( d, rt );
449 }
450 #else
451 Assembler::call( d, rt );
452 #endif
453 }
454
455 inline void MacroAssembler::call( Label& L, relocInfo::relocType rt ) {
456 MacroAssembler::call( target(L), rt);
457 }
458
459
460
461 inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); }
462 inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); }
463
464 // prefetch instruction
465 inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) {
466 if (VM_Version::v9_instructions_work())
467 Assembler::bp( never, true, xcc, pt, d, rt );
468 }
469 inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); }
470
471
472 // clobbers o7 on V8!!
473 // returns delta from gotten pc to addr after
474 inline int MacroAssembler::get_pc( Register d ) {
475 int x = offset();
476 if (VM_Version::v9_instructions_work())
477 rdpc(d);
478 else {
479 Label lbl;
480 Assembler::call(lbl, relocInfo::none); // No relocation as this is call to pc+0x8
481 if (d == O7) delayed()->nop();
482 else delayed()->mov(O7, d);
483 bind(lbl);
484 }
485 return offset() - x;
486 }
487
488
489 // Note: All MacroAssembler::set_foo functions are defined out-of-line.
490
491
492 // Loads the current PC of the following instruction as an immediate value in
493 // 2 instructions. All PCs in the CodeCache are within 2 Gig of each other.
494 inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) {
495 intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip;
496 #ifdef _LP64
497 Unimplemented();
498 #else
499 Assembler::sethi( thepc & ~0x3ff, reg, internal_word_Relocation::spec((address)thepc));
500 Assembler::add(reg,thepc & 0x3ff, reg, internal_word_Relocation::spec((address)thepc));
501 #endif
502 return thepc;
503 }
504
505 inline void MacroAssembler::load_address( Address& a, int offset ) {
506 assert_not_delayed();
507 #ifdef _LP64
508 sethi(a);
509 add(a, a.base(), offset);
510 #else
511 if (a.hi() == 0 && a.rtype() == relocInfo::none) {
512 set(a.disp() + offset, a.base());
513 }
514 else {
515 sethi(a);
516 add(a, a.base(), offset);
517 }
518 #endif
519 }
520
521
522 inline void MacroAssembler::split_disp( Address& a, Register temp ) {
523 assert_not_delayed();
524 a = a.split_disp();
525 Assembler::sethi(a.hi(), temp, a.rspec());
526 add(a.base(), temp, a.base());
527 }
528
529
530 inline void MacroAssembler::load_contents( Address& a, Register d, int offset ) {
531 assert_not_delayed();
532 sethi(a);
533 ld(a, d, offset);
534 }
535
536
537 inline void MacroAssembler::load_ptr_contents( Address& a, Register d, int offset ) {
538 assert_not_delayed();
539 sethi(a);
540 ld_ptr(a, d, offset);
541 }
542
543
544 inline void MacroAssembler::store_contents( Register s, Address& a, int offset ) {
545 assert_not_delayed();
546 sethi(a);
547 st(s, a, offset);
548 }
549
550
551 inline void MacroAssembler::store_ptr_contents( Register s, Address& a, int offset ) {
552 assert_not_delayed();
553 sethi(a);
554 st_ptr(s, a, offset);
555 }
556
557
558 // This code sequence is relocatable to any address, even on LP64.
559 inline void MacroAssembler::jumpl_to( Address& a, Register d, int offset ) {
560 assert_not_delayed();
561 // Force fixed length sethi because NativeJump and NativeFarCall don't handle
562 // variable length instruction streams.
563 sethi(a, /*ForceRelocatable=*/ true);
564 jmpl(a, d, offset);
565 }
566
567
568 inline void MacroAssembler::jump_to( Address& a, int offset ) {
569 jumpl_to( a, G0, offset );
570 }
571
572
573 inline void MacroAssembler::set_oop( jobject obj, Register d ) {
574 set_oop(allocate_oop_address(obj, d));
575 }
576
577
578 inline void MacroAssembler::set_oop_constant( jobject obj, Register d ) {
579 set_oop(constant_oop_address(obj, d));
580 }
581
582
583 inline void MacroAssembler::set_oop( Address obj_addr ) {
584 assert(obj_addr.rspec().type()==relocInfo::oop_type, "must be an oop reloc");
585 load_address(obj_addr);
586 }
587
588
589 inline void MacroAssembler::load_argument( Argument& a, Register d ) {
590 if (a.is_register())
591 mov(a.as_register(), d);
592 else
593 ld (a.as_address(), d);
594 }
595
596 inline void MacroAssembler::store_argument( Register s, Argument& a ) {
597 if (a.is_register())
598 mov(s, a.as_register());
599 else
600 st_ptr (s, a.as_address()); // ABI says everything is right justified.
601 }
602
603 inline void MacroAssembler::store_ptr_argument( Register s, Argument& a ) {
604 if (a.is_register())
605 mov(s, a.as_register());
606 else
607 st_ptr (s, a.as_address());
608 }
609
610
611 #ifdef _LP64
612 inline void MacroAssembler::store_float_argument( FloatRegister s, Argument& a ) {
613 if (a.is_float_register())
614 // V9 ABI has F1, F3, F5 are used to pass instead of O0, O1, O2
615 fmov(FloatRegisterImpl::S, s, a.as_float_register() );
616 else
617 // Floats are stored in the high half of the stack entry
618 // The low half is undefined per the ABI.
619 stf(FloatRegisterImpl::S, s, a.as_address(), sizeof(jfloat));
620 }
621
622 inline void MacroAssembler::store_double_argument( FloatRegister s, Argument& a ) {
623 if (a.is_float_register())
624 // V9 ABI has D0, D2, D4 are used to pass instead of O0, O1, O2
625 fmov(FloatRegisterImpl::D, s, a.as_double_register() );
626 else
627 stf(FloatRegisterImpl::D, s, a.as_address());
628 }
629
630 inline void MacroAssembler::store_long_argument( Register s, Argument& a ) {
631 if (a.is_register())
632 mov(s, a.as_register());
633 else
634 stx(s, a.as_address());
635 }
636 #endif
637
638 inline void MacroAssembler::clrb( Register s1, Register s2) { stb( G0, s1, s2 ); }
639 inline void MacroAssembler::clrh( Register s1, Register s2) { sth( G0, s1, s2 ); }
640 inline void MacroAssembler::clr( Register s1, Register s2) { stw( G0, s1, s2 ); }
641 inline void MacroAssembler::clrx( Register s1, Register s2) { stx( G0, s1, s2 ); }
642
643 inline void MacroAssembler::clrb( Register s1, int simm13a) { stb( G0, s1, simm13a); }
644 inline void MacroAssembler::clrh( Register s1, int simm13a) { sth( G0, s1, simm13a); }
645 inline void MacroAssembler::clr( Register s1, int simm13a) { stw( G0, s1, simm13a); }
646 inline void MacroAssembler::clrx( Register s1, int simm13a) { stx( G0, s1, simm13a); }
647
648 // returns if membar generates anything, obviously this code should mirror
649 // membar below.
650 inline bool MacroAssembler::membar_has_effect( Membar_mask_bits const7a ) {
651 if( !os::is_MP() ) return false; // Not needed on single CPU
652 if( VM_Version::v9_instructions_work() ) {
653 const Membar_mask_bits effective_mask =
654 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
655 return (effective_mask != 0);
656 } else {
657 return true;
658 }
659 }
660
661 inline void MacroAssembler::membar( Membar_mask_bits const7a ) {
662 // Uniprocessors do not need memory barriers
663 if (!os::is_MP()) return;
664 // Weakened for current Sparcs and TSO. See the v9 manual, sections 8.4.3,
665 // 8.4.4.3, a.31 and a.50.
666 if( VM_Version::v9_instructions_work() ) {
667 // Under TSO, setting bit 3, 2, or 0 is redundant, so the only value
668 // of the mmask subfield of const7a that does anything that isn't done
669 // implicitly is StoreLoad.
670 const Membar_mask_bits effective_mask =
671 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
672 if ( effective_mask != 0 ) {
673 Assembler::membar( effective_mask );
674 }
675 } else {
676 // stbar is the closest there is on v8. Equivalent to membar(StoreStore). We
677 // do not issue the stbar because to my knowledge all v8 machines implement TSO,
678 // which guarantees that all stores behave as if an stbar were issued just after
679 // each one of them. On these machines, stbar ought to be a nop. There doesn't
680 // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it,
681 // it can't be specified by stbar, nor have I come up with a way to simulate it.
682 //
683 // Addendum. Dave says that ldstub guarantees a write buffer flush to coherent
684 // space. Put one here to be on the safe side.
685 Assembler::ldstub(SP, 0, G0);
686 }
687 }